JP2002009111A - Method for mounting semiconductor flip chip - Google Patents

Method for mounting semiconductor flip chip

Info

Publication number
JP2002009111A
JP2002009111A JP2000186439A JP2000186439A JP2002009111A JP 2002009111 A JP2002009111 A JP 2002009111A JP 2000186439 A JP2000186439 A JP 2000186439A JP 2000186439 A JP2000186439 A JP 2000186439A JP 2002009111 A JP2002009111 A JP 2002009111A
Authority
JP
Japan
Prior art keywords
binder layer
flip chip
semiconductor flip
curing
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000186439A
Other languages
Japanese (ja)
Inventor
Atsuo Sasaki
敦夫 佐々木
Kenji Katsuki
謙治 香月
Takao Shioyama
隆雄 塩山
Kanta Nokita
寛太 野北
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsui High Tec Inc
Original Assignee
Mitsui High Tec Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsui High Tec Inc filed Critical Mitsui High Tec Inc
Priority to JP2000186439A priority Critical patent/JP2002009111A/en
Publication of JP2002009111A publication Critical patent/JP2002009111A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping

Landscapes

  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a method for mounting semiconductor flip chip which can pass reliability tests by reducing stress and improving connecting strength in an bonding interface, and preventing failures in dimensional accuracy and planarity. SOLUTION: On a surface of a conductor circuit substrate 12, that is, an organic resin substrate on which a conductor circuit pattern 11 equipped with a plurality of connecting terminals 15 is formed, thermosetting resin binder is applied and a binder layer 18 is formed. Then, the semiconductor flip chip 22 with a plurality of electrode bumps 21 is mounted on the binder layer 18 with the face down. The chip is pressed and the binder layer 18 is spread by applying predetermined pressure to form an electrical conducting circuit by pressure welding the electrode bump 21 to the connecting terminal 15. After that, the required number of gradational thermosetting processes are conducted on the binder layer 18 with the semiconductor flip chip 22 being applied with pressure.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体フリップ・
チップと導体回路基板の電極間がダイレクト接続又は媒
体接続された半導体フリップ・チップの実装方法に関
し、特に、半導体フリップ・チップと導体回路基板との
間に介在する熱硬化性樹脂バインダーの加熱硬化作業手
順の改良に関する。
The present invention relates to a semiconductor flip-flop.
The present invention relates to a method of mounting a semiconductor flip chip in which a chip and an electrode of a conductive circuit board are directly connected or medium-connected, and particularly to a heat curing operation of a thermosetting resin binder interposed between the semiconductor flip chip and the conductive circuit board. Regarding improvement of procedure.

【0002】[0002]

【従来の技術】近年、半導体装置の超小型化や高速化、
高周波化等に対応する目的で、半導体チップの電極パッ
ドに電極バンプが形成された半導体フリップ・チップを
フェースダウン状態で導体回路基板(インターポーザ)
上に直接実装する半導体フリップ・チップの実装方法が
実用化されている。例えば、特開平5−175280号
公報に開示されているように、導体回路基板の接続端子
と半導体フリップ・チップの電極パッドとの電気的接続
が、導体回路基板を覆っている粘着型熱硬化性薄膜部材
を貫通してなされると共に、粘着型熱硬化性薄膜部材を
加熱して、その硬化収縮力によって半導体フリップ・チ
ップの電極バンプが導体回路基板の接続端子に圧接接続
されて電気的導通回路を形成すると共に、圧接接続状態
を維持する封止を行う構成とされている。
2. Description of the Related Art In recent years, ultra-small and high-speed semiconductor devices have been developed.
A semiconductor flip chip with electrode bumps formed on the electrode pads of a semiconductor chip in a face-down state for the purpose of responding to higher frequencies etc.
A method of mounting a semiconductor flip chip directly mounted on the semiconductor chip has been put to practical use. For example, as disclosed in Japanese Patent Application Laid-Open No. 5-175280, an electrical connection between a connection terminal of a conductor circuit board and an electrode pad of a semiconductor flip chip is made of an adhesive-type thermosetting resin covering the conductor circuit board. The adhesive is formed through the thin-film member, and the adhesive-type thermosetting thin-film member is heated, and the curing shrinkage force causes the electrode bumps of the semiconductor flip chip to be pressed and connected to the connection terminals of the conductive circuit board, thereby forming an electrically conductive circuit. Is formed, and sealing is performed to maintain the press-connection state.

【0003】更に、最近では半導体フリップ・チップの
実装方法として、半導体フリップ・チップと導体回路基
板の間隙に液状の熱硬化性樹脂バインダーを充填し、こ
れを加熱硬化してバインダー層を形成し、封止するアン
ダフィリング方式が提案されている。このアンダフィリ
ング方式としては、バインダー層の粘度を下げてバイン
ダー層の流れ性をよくして充填効果を高めると共に、導
体回路基板に含まれるガスやバインダー層中に含まれる
ボイドを除去するために、60〜80℃に加熱されたス
テージ上に導体回路基板を固定して予備加熱を行い、 a)半導体フリップ・チップをフェースダウン状態で加
圧して実装を行った後に、ディスペンサーシリジンのニ
ードルの先端から60〜80℃に加熱された液状の熱硬
化性樹脂バインダーを、半導体フリップ・チップと導体
回路基板との間隙に供給し、所定の硬化温度で加熱硬化
させる方法、 b)導体回路基板上の半導体フリップ・チップを搭載す
る中央部分に、予め60〜80℃に加熱された液状の熱
硬化性樹脂バインダーを適量載せてバインダー層を形成
しておき、半導体チップの電極パッドにAuボールボン
ディングバンプが形成された半導体フリップ・チップを
バインダー上にフェースダウン状態で上から押し付けて
バインダー層を押し広げて加熱硬化させる方法、のいず
れかにより、半導体フリップ・チップの電極バンプを導
体回路基板の接続端子に圧接接続すると共に、これらを
封止する半導体フリップ・チップの実装方法が実用化さ
れている。
Further, recently, as a mounting method of a semiconductor flip chip, a liquid thermosetting resin binder is filled in a gap between the semiconductor flip chip and the conductive circuit board, and this is heated and cured to form a binder layer. An underfilling method for sealing has been proposed. As this underfilling method, in order to reduce the viscosity of the binder layer, improve the flowability of the binder layer and enhance the filling effect, and to remove the gas contained in the conductive circuit board and the voids contained in the binder layer, A conductor circuit board is fixed on a stage heated to 60 to 80 ° C., and preheating is performed. A) After mounting the semiconductor flip chip by pressing the semiconductor flip chip in a face-down state, the tip of the needle of the dispenser silidine A method in which a liquid thermosetting resin binder heated to 60 to 80 ° C. is supplied to a gap between the semiconductor flip chip and the conductive circuit board and is heated and cured at a predetermined curing temperature; An appropriate amount of a liquid thermosetting resin binder preheated to 60 to 80 ° C. is placed on a center portion where the semiconductor flip chip is mounted, and the binder is mounted. A semiconductor flip chip in which an Au ball bonding bump is formed on an electrode pad of a semiconductor chip on a binder, pressing the semiconductor flip chip from above with the face down state, spreading the binder layer and curing by heating. Either way, a method of mounting a semiconductor flip chip that press-connects electrode bumps of a semiconductor flip chip to connection terminals of a conductive circuit board and seals them has been put to practical use.

【0004】そして、半導体フリップ・チップの実装に
使用される熱硬化性樹脂バインダーは、例えば、主成分
がエポキシ樹脂で、2μm程度の粒子のフィラーを含
み、ガラス転移点温度Tgが150〜170℃、熱膨張
係数がガラス転移点温度Tg以下で33〜45ppm/
℃、ガラス転移点温度Tgを超えると110〜120p
pm/℃の硬化物特性を有し、液状の状態で粘度が90
0〜1100cps程度の特性を有する硬化温度が26
0℃のエポキシ系熱硬化性樹脂バインダーが多く使用さ
れている。
[0004] The thermosetting resin binder used for mounting the semiconductor flip chip is, for example, an epoxy resin as a main component, containing a filler having a particle size of about 2 µm, and having a glass transition temperature Tg of 150 to 170 ° C. Having a thermal expansion coefficient of 33 to 45 ppm /
℃, 110-120p when exceeding the glass transition temperature Tg
pm / ° C and has a viscosity of 90 in liquid state
Curing temperature having a characteristic of about 0 to 1100 cps is 26
Epoxy thermosetting resin binders at 0 ° C. are often used.

【0005】上記b)の硬化方法を用いた半導体フリッ
プ・チップの実装方法の一例について説明する。例えば
図5(A)に示すように、半導体装置30を形成する場
合、樹脂基板からなる導体回路基板31上に半導体フリ
ップ・チップ32をフェースダウン状態で実装するが、
その工程は、 (1)半導体チップ33の複数の電極パッド34のそれ
ぞれに、例えばAuボールボンディングバンプからなる
電極バンプ35が形成された半導体フリップ・チップ3
2を準備する(電極バンプ形成工程)。 (2)有機系銅張り樹脂基板の一例であるガラスBTレ
ジン基板(ビスマレイミドとトリアジンを主成分とする
樹脂基板で、ガラス転移点温度Tg=180〜230
℃、熱膨張係数α=13〜17ppm/℃)の両面の銅
箔をエッチング加工して、導体リードや半導体搭載部を
有する所定の導体回路パターン36が形成された、例え
ばガラスBTレジンベースの導体回路基板31を準備す
る(導体回路基板形成工程)。 (3)その導体回路基板31上の半導体フリップ・チッ
プ32を搭載する中央部分に予めエポキシ系熱硬化性樹
脂バインダーを適量載せてバインダー層37を形成する
(バインダー塗布工程)。 (4)バインダー層37が形成された導体回路基板31
を加熱ステージに固定して80℃程度に昇温し、バイン
ダー層37の粘度を下げ、バインダー層37の流れ性を
よくして充填効果を高めると共に、導体回路基板31に
含まれるガスやバインダー層37中に含まれるボイドを
除去するための予熱を行う(予熱工程)。
An example of a method for mounting a semiconductor flip chip using the curing method b) will be described. For example, as shown in FIG. 5A, when a semiconductor device 30 is formed, a semiconductor flip chip 32 is mounted face down on a conductive circuit board 31 made of a resin substrate.
The steps are as follows: (1) A semiconductor flip chip 3 in which an electrode bump 35 made of, for example, an Au ball bonding bump is formed on each of a plurality of electrode pads 34 of a semiconductor chip 33
2 is prepared (electrode bump formation step). (2) A glass BT resin substrate (a resin substrate containing bismaleimide and triazine as main components, which is an example of an organic copper-clad resin substrate, and having a glass transition temperature Tg of 180 to 230)
For example, a glass BT resin-based conductor in which a predetermined conductor circuit pattern 36 having conductor leads and a semiconductor mounting portion is formed by etching a copper foil on both sides having a thermal expansion coefficient α of 13 to 17 ppm / ° C. A circuit board 31 is prepared (conductor circuit board forming step). (3) An appropriate amount of an epoxy-based thermosetting resin binder is previously placed on the center of the conductive circuit board 31 where the semiconductor flip chip 32 is to be mounted to form a binder layer 37 (binder coating step). (4) Conductive circuit board 31 on which binder layer 37 is formed
Is fixed on a heating stage, the temperature is raised to about 80 ° C., the viscosity of the binder layer 37 is reduced, the flowability of the binder layer 37 is improved, and the filling effect is improved. Preheating for removing voids contained in 37 is performed (preheating step).

【0006】(5)予熱された導体回路基板31のバイ
ンダー層37に半導体フリップ・チップ32を位置決め
載置して所定の加圧力で、これを押圧してバインダー層
37を押し広げ、導体回路基板31に設けた接続端子パ
ッド38に電極バンプ35を圧接接続させて電気的導通
回路を形成する(実装工程)。 (6)図6に示すように、半導体フリップ・チップ32
を加圧した状態で加熱し、3秒間に260℃のエポキシ
系熱硬化性樹脂バインダーの硬化温度に上昇させる(加
熱工程)。 (7)エポキシ系熱硬化性樹脂バインダーの硬化温度
(260℃)で11秒間保持して、バインダー層37を
硬化率95〜100%に硬化させる(熱硬化工程)。 (8)その後、20秒間に80℃に冷却し、放置する
(冷却工程)。 このようにして、半導体フリップ・チップ32の電極パ
ッド34と導体回路基板31の接続端子パッド38との
間の電気的導通回路が形成されると共に、これらを保持
した状態で半導体フリップ・チップ32が導体回路基板
31に封止実装される。
(5) The semiconductor flip chip 32 is positioned and mounted on the binder layer 37 of the preheated conductive circuit board 31 and is pressed with a predetermined pressing force to spread the binder layer 37, thereby expanding the conductive circuit board. The electrode bumps 35 are pressed into contact with the connection terminal pads 38 provided on the base 31 to form an electrical conduction circuit (mounting step). (6) As shown in FIG. 6, the semiconductor flip chip 32
Is heated in a pressurized state to raise the curing temperature of the epoxy-based thermosetting resin binder to 260 ° C. in 3 seconds (heating step). (7) The binder layer 37 is cured at a curing rate of 95 to 100% by keeping the epoxy-based thermosetting resin binder at a curing temperature (260 ° C.) for 11 seconds (thermal curing step). (8) Then, it is cooled to 80 ° C. for 20 seconds and left (cooling step). In this way, an electrical conduction circuit is formed between the electrode pads 34 of the semiconductor flip chip 32 and the connection terminal pads 38 of the conductive circuit board 31, and the semiconductor flip chip 32 is held while holding these. It is sealed and mounted on the conductive circuit board 31.

【0007】[0007]

【発明が解決しようとする課題】しかしながら、半導体
フリップ・チップ32と導体回路基板31との間隙に充
填された液状のバインダー層37を上記従来の加熱硬化
条件で熱硬化させて半導体フリップ・チップ32を実装
する場合、有機系樹脂基板の一例であるガラスBTレジ
ン基板からなる導体回路基板31は、バインダー層37
の硬化温度の260℃に上昇されるので、導体回路基板
31のガラス転移点温度Tg(180〜230℃)より
温度が高くなる。そのため、導体回路基板31は軟化
し、図5(A)に矢印Aで示すように、導体回路基板3
1に伸びが生じた状態でバインダー層37は所定の硬化
率(95〜98%)に達し、バインダー層37は硬化収
縮する。そして、冷却されて導体回路基板31のガラス
転移点温度Tg(180〜230℃)より温度が下がる
と、導体回路基板31も硬化収縮する。そして、導体回
路基板31とバインダー層37及び半導体フリップ・チ
ップ32とバインダー層37との接着界面に熱膨張係数
差に起因する応力が残留すると共に、図5(B)に矢印
Bで示す収縮力により反りが発生する。更に剛性が大で
フレキシビリティに欠ける接続端子パッド38と電極バ
ンプ35の圧接接合部にも応力が残留する。
However, the liquid binder layer 37 filled in the gap between the semiconductor flip chip 32 and the conductive circuit board 31 is heat-cured under the above-mentioned conventional heat-curing conditions, so that the semiconductor flip chip 32 is hardened. Is mounted, the conductive circuit board 31 made of a glass BT resin substrate, which is an example of an organic resin substrate, is provided with a binder layer 37.
Is raised to a curing temperature of 260 ° C., the temperature becomes higher than the glass transition point temperature Tg (180 to 230 ° C.) of the conductive circuit board 31. Therefore, the conductive circuit board 31 softens, and as shown by the arrow A in FIG.
In a state where the elongation occurs in 1, the binder layer 37 reaches a predetermined curing rate (95 to 98%), and the binder layer 37 cures and contracts. Then, when the temperature is lowered below the glass transition point temperature Tg (180 to 230 ° C.) of the conductive circuit board 31, the conductive circuit board 31 also cures and contracts. Then, a stress due to a difference in thermal expansion coefficient remains at the bonding interface between the conductive circuit board 31 and the binder layer 37 and between the semiconductor flip chip 32 and the binder layer 37, and a contraction force indicated by an arrow B in FIG. Causes warpage. Furthermore, stress remains at the press-bonded junction between the connection terminal pad 38 and the electrode bump 35, which has high rigidity and lacks flexibility.

【0008】その結果として、PCT(Pressur
e Cracker Test:温度110℃、湿度8
5%、500時間)、TCT(Temperature
Cycle Test:125℃/−55℃、100
0Cycle)の加熱により残留応力が解放されて、平
坦性(反り)、密着性、電気的接続性等の信頼性試験に
対応(合格)できないという問題があった。したがっ
て、信頼性試験に対応するためには、それぞれの接着界
面での応力低減と接続強度を向上させることが必要とさ
れていた。本発明はこのような事情に鑑みてなされたも
ので、接着界面での応力低減と接続強度とを向上させ、
寸法精度、平坦度(コブラナリティ)の不良の発生を防
ぎ、信頼性試験に対応することができる半導体フリップ
・チップの実装方法を提供することを目的とする。
As a result, PCT (Pressur)
e Cracker Test: Temperature 110 ° C, Humidity 8
5%, 500 hours), TCT (Temperature)
Cycle Test: 125 ° C / -55 ° C, 100
0 cycle), the residual stress is released, and there is a problem that the reliability test such as flatness (warpage), adhesion, and electrical connection cannot be performed (passed). Therefore, in order to cope with the reliability test, it is necessary to reduce the stress at each bonding interface and improve the connection strength. The present invention has been made in view of such circumstances, and improves stress reduction and connection strength at the bonding interface,
An object of the present invention is to provide a method of mounting a semiconductor flip chip which can prevent the occurrence of defects in dimensional accuracy and flatness (coplanarity) and can respond to a reliability test.

【0009】[0009]

【課題を解決するための手段】前記目的に沿う本発明に
係る半導体フリップ・チップの実装方法は、有機系樹脂
基板上に複数の接続端子を備えた導体回路パターンが形
成された導体回路基板の表面に、熱硬化性樹脂バインダ
ーを塗布してバインダー層を形成し、導体回路基板の接
続端子に対応する複数の電極バンプを備える半導体フリ
ップ・チップをバインダー層上にフェースダウン状態で
位置決め搭載する仮接着を行って、半導体フリップ・チ
ップを所定の加圧力で押圧してバインダー層を押し広
げ、接続端子に電極バンプを圧接接続させて電気的導通
回路を形成した後、前記半導体フリップ・チップを加圧
した状態でバインダー層に所要回数の段階加熱硬化処理
を行い、半導体フリップ・チップを導体回路基板上に実
装する構成としている。
According to the present invention, there is provided a method for mounting a semiconductor flip chip, comprising the steps of: forming a conductive circuit pattern having a plurality of connection terminals on an organic resin substrate; A thermosetting resin binder is applied to the surface to form a binder layer, and a semiconductor flip chip having a plurality of electrode bumps corresponding to the connection terminals of the conductive circuit board is positioned and mounted face down on the binder layer. After bonding, the semiconductor flip chip is pressed with a predetermined pressing force to spread the binder layer, and the electrode bumps are pressed and connected to the connection terminals to form an electrical conduction circuit. Then, the semiconductor flip chip is applied. In this configuration, the binder layer is subjected to the required number of steps of heat-curing while pressed, and the semiconductor flip chip is mounted on a conductive circuit board. .

【0010】上記のように、所定回数の段階加熱硬化処
理を行うことによって、所定の仮硬化温度で所定時間維
持して所要の硬化率に仮加熱硬化処理されたバインダー
層は、導体回路基板を補強するように機能するため、そ
の後、バインダー層を所定の本硬化温度で所定時間維持
して所要の硬化率に本加熱硬化処理しても、導体回路基
板の延びが減少し、半導体フリップ・チップと導体回路
基板の接続界面及び接続端子と電極バンプの圧接接合部
の残留応力が低減されて、実装後の半導体装置の反りや
変形を防止することができる。
As described above, the binder layer, which has been subjected to the predetermined number of steps of the heat-curing treatment to maintain the predetermined temporary-curing temperature at a predetermined time for a predetermined period of time and to have a predetermined curing rate, is used as a binder for the conductive circuit board. Even after the binder layer is maintained at a predetermined full-curing temperature for a predetermined time and then subjected to a full-curing treatment to a required curing rate, the extension of the conductive circuit board is reduced, and the semiconductor flip chip Stress at the connection interface between the semiconductor device and the conductive circuit board and at the press-bonded junction between the connection terminal and the electrode bump can be reduced, and the semiconductor device after mounting can be prevented from warping or deforming.

【0011】本発明に係る半導体フリップ・チップの実
装方法において、バインダー層の段階加熱硬化処理は、
バインダー層の硬化率が70〜80%になる仮硬化温度
に上昇させ、所定時間の間、仮硬化温度を維持してバイ
ンダー層を硬化させる第1の段階加熱硬化処理と、更に
バインダー層の硬化率が90〜100%になる本硬化温
度に上昇させ、所定時間の間、本硬化温度を維持してバ
インダー層を硬化させる第2の段階加熱硬化処理とから
なる構成としてもよい。
[0011] In the method for mounting a semiconductor flip chip according to the present invention, the step heat curing of the binder layer is performed by:
A first-stage heat-curing process of raising the binder layer to a temporary curing temperature at which the curing rate becomes 70 to 80% and maintaining the temporary curing temperature for a predetermined time to cure the binder layer, and further curing the binder layer It may be configured to include a second stage heat-curing treatment in which the binder layer is cured while maintaining the full-curing temperature for a predetermined time by increasing the full-curing temperature at which the rate becomes 90 to 100%.

【0012】この場合、第1の段階加熱硬化処理と第2
の段階加熱硬化処理とで段階加熱硬化処理を行って実装
する構成とし、例えば本硬化温度が260℃のバインダ
ー層を2秒間加熱して本硬化温度よりも低い200〜2
40℃(好ましくは220℃)の仮硬化温度に昇温し、
この状態を5秒間維持してバインダー層を硬化率70〜
80%に硬化する第1の段階加熱硬化処理を行い、導体
回路基板は70〜80%の硬化率のバインダー層によっ
て補強されて一体化されているので、その後、第2の段
階加熱硬化処理で本硬化温度の260℃に昇温して、バ
インダー層を所定の硬化率に硬化させても応力の残留を
低減させることが可能となる。なお、バインダー層の硬
化率が70%未満の低い硬化率では、導体回路基板がバ
インダー層によって実質的に補強されないので、第2の
段階加熱硬化処理での導体回路基板の変形は小さくなら
ない。
In this case, the first stage heat curing treatment and the second stage
And a stage heat-curing process is carried out in the step-heat curing process. For example, a binder layer having a main curing temperature of 260 ° C. is heated for 2 seconds to be 200 to 2 lower than the main curing temperature.
Heating to a temporary curing temperature of 40 ° C (preferably 220 ° C),
This state is maintained for 5 seconds to cure the binder layer at a curing rate of 70 to 70%.
A first-stage heat-curing process of curing to 80% is performed, and the conductor circuit board is reinforced and integrated by a binder layer having a curing rate of 70 to 80%. Even when the temperature is raised to the main curing temperature of 260 ° C. to cure the binder layer to a predetermined curing rate, it is possible to reduce the residual stress. At a low curing rate of less than 70% of the binder layer, the conductor circuit board is not substantially reinforced by the binder layer, so that the deformation of the conductor circuit board in the second-stage heat curing treatment does not become small.

【0013】本発明に係る半導体フリップ・チップの実
装方法において、バインダー層の本硬化温度が導体回路
基板のガラス転移点温度よりも高く設定されてもよい。
上記のように、バインダー層の本硬化温度を高く設定す
ることにより、硬化反応が更に促進されるので、硬化時
間の短縮が可能となり、半導体フリップ・チップの実装
時間の短縮が可能となる。更に、硬化時間が短縮される
ので加熱温度による半導体フリップ・チップに与えるダ
メージを低減することができる。
In the method for mounting a semiconductor flip chip according to the present invention, the main curing temperature of the binder layer may be set higher than the glass transition point temperature of the conductive circuit board.
As described above, by setting the main curing temperature of the binder layer high, the curing reaction is further promoted, so that the curing time can be shortened, and the mounting time of the semiconductor flip chip can be shortened. Further, since the curing time is shortened, damage to the semiconductor flip chip caused by the heating temperature can be reduced.

【0014】[0014]

【発明の実施の形態】続いて、添付した図面を参照しつ
つ、本発明を具体化した実施の形態につき説明し、本発
明の理解に供する。ここに、図1は本発明の一実施の形
態に係る半導体フリップ・チップの実装方法を用いて製
造される半導体装置の側面図、図2(A)、(B)はそ
れぞれ同半導体フリップ・チップの実装方法の途中の工
程で形成される半導体パッケージの側面図、導体回路基
板フレームの平面図、図3は同半導体フリップ・チップ
の実装方法に用いる熱硬化樹脂からなるバインダーの硬
化率を示す説明図、図4は同半導体フリップ・チップの
実装方法の硬化工程の時間と温度変化の関係を示す説明
図である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the accompanying drawings to provide an understanding of the present invention. Here, FIG. 1 is a side view of a semiconductor device manufactured by using the semiconductor flip chip mounting method according to one embodiment of the present invention, and FIGS. 2A and 2B are the same semiconductor flip chip, respectively. 3 is a side view of a semiconductor package formed in a process in the middle of the mounting method, a plan view of a conductive circuit board frame, and FIG. 3 is an explanatory view showing a curing rate of a binder made of a thermosetting resin used in the mounting method of the semiconductor flip chip. FIGS. 4A and 4B are explanatory diagrams showing the relationship between the time of the curing step and the temperature change in the semiconductor flip chip mounting method.

【0015】図1に示すように、本発明の一実施の形態
に係る半導体フリップ・チップの実装方法を用いて形成
される半導体装置10は、有機系樹脂基板の一例であ
る、例えば0.1〜0.4mm程度で、その表面に銅箔
を有するガラスBTレジン銅張り基板の銅箔にエッチン
グ加工を施すことにより、所定の導体回路パターン11
(図2(A)、(B)参照)が形成されたガラスBTレ
ジン基板をベースとする導体回路基板12を備えてい
る。そして、導体回路パターン11は、中央部にダミー
パッド13を有し、その周囲に複数の導体リード14を
配列し、各導体リード14の半導体搭載面(上面)側の
一端部の表面に金めっきが施された接続端子の一部であ
る内部接続端子パッド15が形成されている。また、導
体回路基板12の実装面(下面)側にはアレイ状に配置
された接続端子の一部である外部接続端子ランド16が
形成され、外部接続端子ランド16はスルーホール17
を介して内部接続端子パッド15と電気的に接続されて
いる。
As shown in FIG. 1, a semiconductor device 10 formed by using a method for mounting a semiconductor flip chip according to one embodiment of the present invention is an example of an organic resin substrate, for example, 0.1%. By etching the copper foil of a glass BT resin copper-clad substrate having a copper foil on its surface to a predetermined conductor circuit pattern 11
A conductive circuit board 12 based on a glass BT resin substrate on which (see FIGS. 2A and 2B) is formed is provided. The conductor circuit pattern 11 has a dummy pad 13 in the center, a plurality of conductor leads 14 arranged around the dummy pad 13, and gold plating on the surface of one end of each conductor lead 14 on the semiconductor mounting surface (upper surface) side. The internal connection terminal pad 15 which is a part of the connection terminal provided with is formed. On the mounting surface (lower surface) side of the conductive circuit board 12, an external connection terminal land 16 which is a part of the connection terminals arranged in an array is formed.
And is electrically connected to the internal connection terminal pad 15 via.

【0016】導体回路パターン11上には、例えばエポ
キシ樹脂を主体とする熱硬化樹脂からなる熱硬化樹脂バ
インダー(以下、バインダーという)を塗布し、硬化さ
せた所要の硬化物特性を有するバインダー層18が形成
されている。なお、エポキシ樹脂を主体とする熱硬化樹
脂は、例えば図3に示すように、220℃(仮硬化温
度)で5秒間加熱したときに硬化率が70〜80%(平
均75%)となり、260℃(本硬化温度)で5秒間加
熱したときに、硬化率が90〜100%になるように構
成されている。また、バインダーは、例えばエポキシ樹
脂を主体とし、フィラー、硬化剤、反応性希釈剤を含む
構成の熱硬化性エポキシ樹脂バインダーとされており、
硬化温度が260℃で、しかもガラス転移点温度が15
0℃〜170℃で、且つ熱膨張係数がガラス転移点温度
以下のとき33〜45ppm/℃、ガラス転移点温度以
上のとき110〜120ppm/℃の硬化物特性を有
し、更には、液状のときの粘度が900〜1100cp
sの特性を有している。
A thermosetting resin binder (hereinafter, referred to as a binder) made of, for example, a thermosetting resin mainly composed of an epoxy resin is applied on the conductive circuit pattern 11 and cured to form a binder layer 18 having required cured material characteristics. Are formed. As shown in FIG. 3, for example, the thermosetting resin mainly composed of epoxy resin has a curing rate of 70 to 80% (average 75%) when heated at 220 ° C. (temporary curing temperature) for 5 seconds. When heated at 5 ° C. (main curing temperature) for 5 seconds, the curing rate is 90 to 100%. In addition, the binder is, for example, a thermosetting epoxy resin binder having a configuration containing an epoxy resin as a main component, a filler, a curing agent, and a reactive diluent,
Curing temperature of 260 ° C and glass transition temperature of 15
It has a cured product characteristic of 33 to 45 ppm / ° C when the thermal expansion coefficient is 0 ° C to 170 ° C and the thermal expansion coefficient is lower than the glass transition temperature, and 110 to 120 ppm / ° C when the thermal expansion coefficient is higher than the glass transition temperature. When the viscosity is 900-1100cp
s.

【0017】更に、バインダー層18の上には、半導体
チップ19の複数の能動素子面に形成された複数の電極
パッド20を下向きに、すなわち電極パッド20に設け
た、一例としてAuボールボンディングバンプからなる
電極バンプ21を設けた半導体フリップ・チップ22を
フェースダウンの状態に実装している。そして、半導体
フリップ・チップ22と導体回路基板12とをバインダ
ー層18によって接合し、樹脂封止した半導体装置10
を構成している。このとき、電極バンプ21はバインダ
ー層18によって導体リード14に設けた内部接続端子
パッド15に機械的接触されて電気的導通回路を形成す
ると共に、バインダー層18は硬化して電気的導通回路
を保持し、電気的接続とアンダーフィル機能を兼備して
いる。
Further, on the binder layer 18, a plurality of electrode pads 20 formed on a plurality of active element surfaces of the semiconductor chip 19 are provided downward, that is, provided on the electrode pads 20, for example, from Au ball bonding bumps. The semiconductor flip chip 22 provided with the electrode bumps 21 is mounted face down. Then, the semiconductor flip chip 22 and the conductive circuit board 12 are joined by the binder layer 18 and the semiconductor device 10 sealed with resin is formed.
Is composed. At this time, the electrode bumps 21 are brought into mechanical contact with the internal connection terminal pads 15 provided on the conductor leads 14 by the binder layer 18 to form an electrical conduction circuit, and the binder layer 18 is cured to hold the electrical conduction circuit. In addition, it has both an electrical connection and an underfill function.

【0018】ここで、本発明の一実施の形態に係る半導
体フリップ・チップの実装方法を用いた半導体装置の製
造方法について、図4を参照しながら説明する。半導体
装置10は、バンプ形成工程、導体回路基板形成工程
と、半導体フリップ・チップの実装方法を構成するバイ
ンダー層塗布工程、予熱工程、実装工程、第1の段階加
熱硬化処理工程、第2の段階加熱硬化処理工程、冷却工
程及び分割工程を経て製造される。すなわち、 (1)半導体チップ19の複数の電極パッド20のそれ
ぞれに、例えばAuボールボンディングバンプからなる
電極バンプ21が形成された半導体フリップ・チップ2
2を準備する(バンプ形成工程)。 (2)有機系樹脂基板の一例である表裏面に銅箔を有す
るガラスBTレジン銅張り基板(ガラス転移点温度Tg
=180〜230℃、熱膨張係数α=17ppm/℃)
の銅箔にエッチング加工を施すことにより、所定の導体
回路パターン11が短冊状(図2(A)、(B)参照)
又はマトリックス状に複数個配置されたガラスBTレジ
ン基板をベースとする導体回路基板フレーム23を準備
する(導体回路基板形成工程)。
Here, a method of manufacturing a semiconductor device using the method of mounting a semiconductor flip chip according to one embodiment of the present invention will be described with reference to FIG. The semiconductor device 10 includes a bump forming step, a conductive circuit board forming step, a binder layer applying step, a preheating step, a mounting step, a first-step heat-curing step, and a second step, which constitute a semiconductor flip-chip mounting method. It is manufactured through a heat curing process, a cooling process, and a dividing process. (1) A semiconductor flip chip 2 in which an electrode bump 21 made of, for example, an Au ball bonding bump is formed on each of a plurality of electrode pads 20 of a semiconductor chip 19.
2 is prepared (bump forming step). (2) A glass BT resin copper-clad substrate having a copper foil on the front and back surfaces as an example of an organic resin substrate (glass transition temperature Tg
= 180-230 ° C, coefficient of thermal expansion α = 17ppm / ° C)
By performing etching on the copper foil, a predetermined conductor circuit pattern 11 is formed in a strip shape (see FIGS. 2A and 2B).
Alternatively, a conductive circuit board frame 23 based on a plurality of glass BT resin boards arranged in a matrix is prepared (conductor circuit board forming step).

【0019】(3)導体回路基板フレーム23の各ダミ
ーパッド13上に予め液状の熱硬化性エポキシ樹脂から
なるバインダーを適量載せてバインダー層18を形成す
る(バインダー層塗布工程)。 (4)バインダー層18が形成された導体回路基板フレ
ーム23を加熱ステージに固定して80℃程度に昇温
し、バインダー層18の粘度を下げ、バインダー層18
の流れ性をよくして充填効果を高めると共に、導体回路
基板フレーム23に含まれるガスやバインダー層18中
に含まれるボイドを除去するための予熱を行う(予熱工
程)。 (5)予熱された導体回路基板フレーム23のバインダ
ー層18に半導体フリップ・チップ22を位置決め載置
して仮接着を行った後、所定の加圧力でこれを押圧して
バインダー層18を押し広げ、内部接続端子パッド15
に電極バンプ21を圧接接続させて電気的導通回路を形
成する(実装工程)。
(3) An appropriate amount of a binder made of a liquid thermosetting epoxy resin is previously placed on each dummy pad 13 of the conductive circuit board frame 23 to form a binder layer 18 (binder layer coating step). (4) The conductor circuit board frame 23 on which the binder layer 18 is formed is fixed on a heating stage, and the temperature is raised to about 80 ° C. to lower the viscosity of the binder layer 18.
And the preheating for removing the gas contained in the conductive circuit board frame 23 and the voids contained in the binder layer 18 is performed (preheating step). (5) After the semiconductor flip chip 22 is positioned and mounted on the binder layer 18 of the preheated conductive circuit board frame 23 to perform temporary bonding, the semiconductor flip chip 22 is pressed with a predetermined pressing force to spread the binder layer 18. , Internal connection terminal pad 15
The electrode bumps 21 are press-connected to form an electrically conductive circuit (mounting step).

【0020】(6)次に、半導体フリップ・チップ22
を加圧した状態で、2秒間に220℃のバインダー層1
8の仮硬化温度に上昇させる第1の加熱を行い、その仮
硬化温度で5秒間維持して硬化反応を進めて硬化率75
%の第1の熱硬化を行う仮加熱硬化処理、すなわち第1
の段階加熱硬化処理を行う(第1の段階加熱硬化処理工
程)。 (7)第1の段階加熱硬化処理を行った後、1秒間に2
60℃のバインダー層18の本硬化温度に上昇させる第
2の加熱を行い、更に260℃の温度を5秒間維持して
硬化反応を進め、硬化率100%の第2の熱硬化を行う
本加熱硬化処理、すなわち第2の段階加熱硬化処理を行
い、半導体フリップ・チップ22を導体回路基板フレー
ム23に封止した複数の半導体パッケージ24を形成す
る(第2の段階加熱処理工程)。 (8)その後、半導体パッケージ24を20秒間に80
℃に冷却し、放置する(冷却工程)。 (9)複数の半導体パッケージ24が形成された導体回
路基板フレーム23を各半導体フリップ・チップ22毎
にダイシングカットして個々に分割された半導体装置1
0を形成する(分割工程)。
(6) Next, the semiconductor flip chip 22
Under pressure, the binder layer 1 at 220 ° C. for 2 seconds.
The first heating for raising the temporary curing temperature of 8 is performed, the curing reaction is continued at the temporary curing temperature for 5 seconds, and the curing rate is increased to 75%.
% Of the first heat curing, ie, the first heat curing,
Is performed (first step heat curing treatment step). (7) After performing the first stage heat curing treatment, 2 seconds per second
The second heating is performed to raise the final curing temperature of the binder layer 18 at 60 ° C., and the curing reaction is further performed while maintaining the temperature at 260 ° C. for 5 seconds to perform the second thermal curing at a curing rate of 100%. A curing process, that is, a second stage heat curing process is performed to form a plurality of semiconductor packages 24 in which the semiconductor flip chips 22 are sealed in the conductive circuit board frame 23 (second stage heat treatment step). (8) Then, the semiconductor package 24 is moved to 80 for 20 seconds.
C. and left to stand (cooling step). (9) The semiconductor device 1 in which the conductor circuit board frame 23 on which the plurality of semiconductor packages 24 are formed is cut by dicing for each semiconductor flip chip 22 and individually divided.
0 is formed (dividing step).

【0021】上記工程を経て、導体回路基板フレーム2
3と半導体フリップ・チップ22は半導体パッケージ2
4として、半導体フリップ・チップ22と導体回路基板
12の内部接続端子パッド15との間の電気的導通回路
を保持された状態で一体的に封止され、更に各半導体フ
リップ・チップ22毎に分割されて裏面側に外部接続端
子ランド16が露出した半導体装置10が形成される。
なお、本発明に係る半導体フリップ・チップの実装方法
を用いて形成された10個の半導体装置について、信頼
性試験項目のPCT(Pressure Cracke
r Test)を温度が110℃、湿度が85%、気圧
が1.2atm、500時間の条件で行った結果では全
数(10/10)が合格となり、TCT(Temper
ature Cycle Test)を温度125℃/
−55℃、1000Cycleの条件で行った結果でも
全数(10/10)が合格となり、品質の高い半導体装
置が得られた。
Through the above steps, the conductive circuit board frame 2
3 and the semiconductor flip chip 22 are in the semiconductor package 2
As 4, the semiconductor flip chip 22 and the internal connection terminal pad 15 of the conductive circuit board 12 are integrally sealed while holding an electrical conduction circuit, and further divided into each semiconductor flip chip 22. Thus, the semiconductor device 10 in which the external connection terminal lands 16 are exposed on the back surface side is formed.
For ten semiconductor devices formed by using the semiconductor flip chip mounting method according to the present invention, PCT (Pressure Crack) of reliability test items was used.
r Test) at a temperature of 110 ° C., a humidity of 85%, a pressure of 1.2 atm and a pressure of 500 hours, all of the test pieces (10/10) passed, and the TCT (Temper
Nature Cycle Test) at a temperature of 125 ° C /
Even when the test was performed under the conditions of −55 ° C. and 1000 cycles, all (10/10) passed, and a high-quality semiconductor device was obtained.

【0022】以上、本発明を一実施の形態に係る半導体
フリップ・チップの実装方法について説明してきたが、
本発明は、何ら前記の実施の形態に記載の構成に限定さ
れるものではなく、特許請求の範囲に記載されている事
項の範囲内で考えられるその他の実施の形態や変形例も
含むものである。例えば、導体回路基板上の半導体フリ
ップ・チップを搭載する中央部分に設けたダミーパッド
に予めバインダー層を適量載せておき、Auボールボン
ディングバンプを有する半導体フリップ・チップを上か
ら押し付けて、バインダー層を押し広げて硬化する方法
の外に、半導体フリップ・チップを実装後に、ディスペ
ンサーシリジンのニードルの先端からバインダー層を導
体回路基板と半導体フリップ・チップとの間の間隙に供
給して、バインダー層を硬化させる方法であってもよ
い。
While the present invention has been described with respect to a method for mounting a semiconductor flip chip according to one embodiment,
The present invention is not at all limited to the configuration described in the above embodiment, but includes other embodiments and modifications that can be considered within the scope of the matters described in the claims. For example, an appropriate amount of a binder layer is previously placed on a dummy pad provided at a central portion of a conductive circuit board on which a semiconductor flip chip is mounted, and a semiconductor flip chip having an Au ball bonding bump is pressed from above to remove the binder layer. In addition to the method of spreading and curing, after mounting the semiconductor flip chip, a binder layer is supplied to the gap between the conductive circuit board and the semiconductor flip chip from the tip of the needle of the dispenser silidine, and the binder layer is supplied. A curing method may be used.

【0023】更に、前記実施の形態ではガラスBTレジ
ンベースの導体回路基板を用いた構成としたが、導体回
路基板としてガラスクロスエポキシ導体回路基板(グレ
ード:FR−4、5)、ガラスクロスポリエステル回路
基板(グレード:FR−6)を用いた構成とすることも
できる。また、前記実施の形態では半導体フリップ・チ
ップを有機系樹脂基板上に搭載して半導体装置を形成す
るCOB(Chip On Board)タイプについ
て説明したが、本発明に係る半導体フリップ・チップの
実装方法は、半導体チップの上に半導体フリップ・チッ
プを重ねるCOC(Chip On Chip)、半導
体チップが配列されたウエハの上に半導体フリップ・チ
ップが配列されたウエハを重ねるWOW(Wafer
On Wafer)、BGA(Ball Grid A
rray)タイプのCSP(Chip Scale P
ackage)、リードフレーム等に半導体フリップ・
チップを搭載するCOF(ChipOn Frame)
にも適用できる。
Further, in the above-described embodiment, the configuration using the glass BT resin-based conductor circuit board is adopted. However, as the conductor circuit board, a glass cloth epoxy conductor circuit board (grade: FR-4, 5), a glass cloth polyester circuit is used. A configuration using a substrate (grade: FR-6) can also be used. In the above-described embodiment, the COB (Chip On Board) type in which the semiconductor device is formed by mounting the semiconductor flip chip on the organic resin substrate has been described. However, the method for mounting the semiconductor flip chip according to the present invention is described below. A COC (Chip On Chip) in which a semiconductor flip chip is stacked on a semiconductor chip, and a WOW (Wafer) in which a wafer in which semiconductor flip chips are arranged is stacked on a wafer in which semiconductor chips are arranged.
On Wafer), BGA (Ball Grid A)
(rray) type CSP (Chip Scale P)
package), semiconductor flip
COF (ChipOn Frame) with chip mounted
Also applicable to

【0024】[0024]

【発明の効果】請求項1〜3記載の半導体フリップ・チ
ップの実装方法においては、導体回路パターンが形成さ
れた有機系樹脂基板からなる導体回路基板の表面に、熱
硬化性樹脂バインダーを塗布してバインダー層を形成
し、半導体フリップ・チップをバインダー層上にフェー
スダウン状態で位置決め搭載し、半導体フリップ・チッ
プを所定の加圧力で押圧してバインダー層を押し広げる
と共に電気的導通回路を形成した後、前記半導体フリッ
プ・チップを加圧した状態でバインダー層に所要回数の
段階加熱硬化処理を行う。したがって、バインダー層は
仮加熱硬化処理で所定の硬化率(例えば70〜80%)
に硬化されて導体回路基板を補強するように機能し、本
硬化工程で硬化されても、半導体フリップ・チップと導
体回路基板との接着界面及び半導体フリップ・チップの
電極バンプと導体回路基板の接続端子の圧接接合部の残
留応力が低減されると共に、接着強度を向上させ、半導
体装置の状態で反りや変形を防止できる。その結果、寸
法精度や平坦度の不良を防ぐ信頼性の高い半導体フリッ
プ・チップの実装方法を提供できる。
According to the semiconductor flip chip mounting method of the present invention, a thermosetting resin binder is applied to the surface of a conductive circuit board made of an organic resin substrate on which a conductive circuit pattern is formed. The semiconductor flip chip was positioned and mounted face down on the binder layer, and the semiconductor flip chip was pressed with a predetermined pressing force to spread the binder layer and form an electrical conduction circuit. Thereafter, the binder layer is subjected to a required number of steps of heat curing while the semiconductor flip chip is pressed. Therefore, the binder layer has a predetermined curing rate (for example, 70 to 80%) in the temporary heat curing treatment.
It functions to reinforce the conductive circuit board by being hardened, and even if it is hardened in the main curing step, the bonding interface between the semiconductor flip chip and the conductive circuit board and the connection between the electrode bump of the semiconductor flip chip and the conductive circuit board It is possible to reduce the residual stress at the press-bonded portion of the terminal, improve the adhesive strength, and prevent the semiconductor device from being warped or deformed. As a result, it is possible to provide a highly reliable method of mounting a semiconductor flip chip that prevents defects in dimensional accuracy and flatness.

【0025】特に、請求項2記載の半導体フリップ・チ
ップの実装方法においては、バインダー層の段階加熱硬
化処理は、バインダー層の硬化率が70〜80%になる
仮硬化温度を維持してバインダー層を硬化させる第1の
段階加熱硬化処理と、更にバインダー層の硬化率が90
〜100%になる本硬化温度を維持してバインダー層を
硬化させる第2の段階加熱硬化処理とからなる構成とし
ているので、第1の段階加熱硬化処理で導体回路基板と
バインダー層との一体化が進み、第2の段階加熱硬化処
理でバインダー層が本硬化しても、半導体装置の残留応
力が低減され、反りや変形を防止できる。
In particular, in the method for mounting a semiconductor flip chip according to the second aspect, the step heat curing of the binder layer is performed by maintaining a temporary curing temperature at which the curing rate of the binder layer is 70 to 80%. And a first-stage heat-curing treatment for curing
Since the second-stage heat-curing treatment for curing the binder layer while maintaining the main curing temperature of about 100% is performed, the integration of the conductive circuit board and the binder layer is performed in the first-stage heat-curing treatment. Even if the binder layer is fully cured in the second-stage heat curing treatment, the residual stress of the semiconductor device is reduced, and warpage and deformation can be prevented.

【0026】請求項3記載の半導体フリップ・チップの
実装方法においては、バインダー層の本硬化温度が導体
回路基板のガラス転移点温度よりも高く設定されている
ので、バインダー層の硬化温度を高く設定することによ
り、硬化反応が更に促進され、硬化時間の短縮が可能と
なり、半導体フリップ・チップの実装時間の短縮が可能
となる。更に、硬化時間が短縮されるので加熱温度によ
る半導体フリップ・チップに与えるダメージを低減し、
半導体装置の信頼性を向上させることができる。
In the method for mounting a semiconductor flip chip according to the third aspect, the hardening temperature of the binder layer is set higher because the main curing temperature of the binder layer is set higher than the glass transition temperature of the conductive circuit board. By doing so, the curing reaction is further accelerated, the curing time can be shortened, and the mounting time of the semiconductor flip chip can be shortened. Furthermore, since the curing time is shortened, damage to the semiconductor flip chip caused by the heating temperature is reduced,
The reliability of the semiconductor device can be improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施の形態に係る半導体フリップ・
チップの実装方法を用いて製造される半導体装置の側面
図である。
FIG. 1 shows a semiconductor flip device according to an embodiment of the present invention.
It is a side view of the semiconductor device manufactured using the mounting method of a chip.

【図2】(A)、(B)はそれぞれ同半導体フリップ・
チップの実装方法の途中の工程で用いられる半導体パッ
ケージの側面図、導体回路基板フレームの平面図であ
る。
FIGS. 2A and 2B are semiconductor flip-flops, respectively.
FIG. 3 is a side view of a semiconductor package used in a process in the middle of a chip mounting method, and a plan view of a conductive circuit board frame.

【図3】同半導体フリップ・チップの実装方法に用いる
バインダー層の硬化率を示す説明図である。
FIG. 3 is an explanatory diagram showing a curing rate of a binder layer used in the method for mounting the semiconductor flip chip.

【図4】同半導体フリップ・チップの実装方法の硬化工
程の時間と温度変化の状態を示す説明図である。
FIG. 4 is an explanatory diagram showing a state of time and temperature change in a curing step of the semiconductor flip chip mounting method.

【図5】(A)、(B)はそれぞれ従来例に係る半導体
フリップ・チップの実装方法を用いて製造される半導体
装置の側面図、同半導体装置の変形状態を示す側面図で
ある。
FIGS. 5A and 5B are a side view of a semiconductor device manufactured by using a semiconductor flip chip mounting method according to a conventional example and a side view showing a deformed state of the semiconductor device.

【図6】従来例に係る半導体フリップ・チップの実装方
法の硬化工程の時間と温度変化の状態を示す説明図であ
る。
FIG. 6 is an explanatory view showing a state of a time and a temperature change in a curing step of a mounting method of a semiconductor flip chip according to a conventional example.

【符号の説明】[Explanation of symbols]

10:半導体装置、11:半導体回路パターン、12:
導体回路基板、13:ダミーパッド、14:導体リー
ド、15:内部接続端子パッド、16:外部接続端子ラ
ンド、17:スルーホール、18バインダー層、19:
半導体チップ、20:電極パッド、21:電極バンプ、
22:半導体フリップ・チップ、23:導体回路基板フ
レーム、24:半導体パッケージ
10: semiconductor device, 11: semiconductor circuit pattern, 12:
Conductor circuit board, 13: dummy pad, 14: conductor lead, 15: internal connection terminal pad, 16: external connection terminal land, 17: through hole, 18 binder layer, 19:
Semiconductor chip, 20: electrode pad, 21: electrode bump,
22: semiconductor flip chip, 23: conductive circuit board frame, 24: semiconductor package

───────────────────────────────────────────────────── フロントページの続き (72)発明者 塩山 隆雄 福岡県北九州市八幡西区小嶺2丁目10−1 株式会社三井ハイテック内 (72)発明者 野北 寛太 福岡県北九州市八幡西区小嶺2丁目10−1 株式会社三井ハイテック内 Fターム(参考) 5F044 KK02 LL11 LL15 RR19 5F061 AA01 BA03 CA05 CB03 CB13 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Takao Shioyama 10-10-1 Komine, Yawatanishi-ku, Kitakyushu-shi, Fukuoka Mitsui High-Tech Co., Ltd. Mitsui High-Tech Co., Ltd. F-term (reference) 5F044 KK02 LL11 LL15 RR19 5F061 AA01 BA03 CA05 CB03 CB13

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 有機系樹脂基板上に複数の接続端子を備
えた導体回路パターンが形成された導体回路基板の表面
に、熱硬化性樹脂バインダーを塗布してバインダー層を
形成し、前記導体回路基板の前記接続端子に対応する複
数の電極バンプを備える半導体フリップ・チップを前記
バインダー層上にフェースダウン状態で位置決め搭載す
る仮接着を行って、前記半導体フリップ・チップを所定
の加圧力で押圧して前記バインダー層を押し広げ、前記
接続端子に前記電極バンプを圧接接続させて電気的導通
回路を形成した後、前記半導体フリップ・チップを加圧
した状態で前記バインダー層に所要回数の段階加熱硬化
処理を行い、前記半導体フリップ・チップを前記導体回
路基板上に実装する構成としたことを特徴とする半導体
フリップ・チップの実装方法。
And a binder layer formed by applying a thermosetting resin binder to a surface of a conductive circuit board on which a conductive circuit pattern having a plurality of connection terminals is formed on an organic resin substrate. The semiconductor flip chip having a plurality of electrode bumps corresponding to the connection terminals of the substrate is temporarily bonded by positioning and mounting the semiconductor flip chip face down on the binder layer, and the semiconductor flip chip is pressed with a predetermined pressing force. After spreading the binder layer and pressing the electrode bumps to the connection terminals to form an electrical conduction circuit, the semiconductor flip chip is pressurized and the binder layer is heat-cured a required number of times while being hardened. Performing a process and mounting the semiconductor flip chip on the conductive circuit board. Implementation method.
【請求項2】 請求項1記載の半導体フリップ・チップ
の実装方法において、前記バインダー層の前記段階加熱
硬化処理は、前記バインダー層の硬化率が70〜80%
になる仮硬化温度に上昇させ、所定時間の間、前記仮硬
化温度を維持して前記バインダー層を硬化させる第1の
段階加熱硬化処理と、更に前記バインダー層の硬化率が
90〜100%になる本硬化温度に上昇させ、所定時間
の間、前記本硬化温度を維持して前記バインダー層を硬
化させる第2の段階加熱硬化処理とからなる構成とした
ことを特徴とする半導体フリップ・チップの実装方法。
2. The method for mounting a semiconductor flip chip according to claim 1, wherein the step of heating and curing the binder layer has a curing rate of 70 to 80% of the binder layer.
And a first-step heat-curing treatment of curing the binder layer while maintaining the temporary curing temperature for a predetermined time, and further reducing the curing rate of the binder layer to 90 to 100%. A second stage heat-curing process of raising the main curing temperature to a predetermined temperature and maintaining the main curing temperature for a predetermined time to cure the binder layer. Implementation method.
【請求項3】 請求項1又は2記載の半導体フリップ・
チップの実装方法において、前記バインダー層の本硬化
温度が前記導体回路基板のガラス転移点温度よりも高く
設定されていることを特徴とする半導体フリップ・チッ
プの実装方法。
3. The semiconductor flip according to claim 1, wherein
A method of mounting a semiconductor flip chip, wherein a main curing temperature of the binder layer is set higher than a glass transition temperature of the conductive circuit board.
JP2000186439A 2000-06-21 2000-06-21 Method for mounting semiconductor flip chip Pending JP2002009111A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000186439A JP2002009111A (en) 2000-06-21 2000-06-21 Method for mounting semiconductor flip chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000186439A JP2002009111A (en) 2000-06-21 2000-06-21 Method for mounting semiconductor flip chip

Publications (1)

Publication Number Publication Date
JP2002009111A true JP2002009111A (en) 2002-01-11

Family

ID=18686600

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000186439A Pending JP2002009111A (en) 2000-06-21 2000-06-21 Method for mounting semiconductor flip chip

Country Status (1)

Country Link
JP (1) JP2002009111A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004030075A1 (en) * 2002-09-26 2004-04-08 Renesas Technology Corp. Method for manufacturing semiconductor device
US7413935B2 (en) 2004-01-15 2008-08-19 Seiko Epson Corporation Semiconductor device and method of fabricating the same
JP2012009676A (en) * 2010-06-25 2012-01-12 Japan Radio Co Ltd Chip mounting method
JP2016162985A (en) * 2015-03-05 2016-09-05 ルネサスエレクトロニクス株式会社 Semiconductor device manufacturing method
CN112277216A (en) * 2020-08-25 2021-01-29 深圳阿珂法先进科技有限公司 Processing method for improving combination of optical fiber sensor and epoxy resin adhesive

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004030075A1 (en) * 2002-09-26 2004-04-08 Renesas Technology Corp. Method for manufacturing semiconductor device
US7572674B2 (en) 2002-09-26 2009-08-11 Renesas Technology Corp. Method for manufacturing semiconductor device
US7413935B2 (en) 2004-01-15 2008-08-19 Seiko Epson Corporation Semiconductor device and method of fabricating the same
JP2012009676A (en) * 2010-06-25 2012-01-12 Japan Radio Co Ltd Chip mounting method
JP2016162985A (en) * 2015-03-05 2016-09-05 ルネサスエレクトロニクス株式会社 Semiconductor device manufacturing method
CN112277216A (en) * 2020-08-25 2021-01-29 深圳阿珂法先进科技有限公司 Processing method for improving combination of optical fiber sensor and epoxy resin adhesive

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