TWI234213B - Chip package structure and process for fabricating the same - Google Patents
Chip package structure and process for fabricating the same Download PDFInfo
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- TWI234213B TWI234213B TW092129523A TW92129523A TWI234213B TW I234213 B TWI234213 B TW I234213B TW 092129523 A TW092129523 A TW 092129523A TW 92129523 A TW92129523 A TW 92129523A TW I234213 B TWI234213 B TW I234213B
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- 238000000034 method Methods 0.000 title claims abstract description 19
- 230000008569 process Effects 0.000 title abstract description 11
- 239000000463 material Substances 0.000 claims abstract description 26
- 235000012431 wafers Nutrition 0.000 claims description 171
- 239000005022 packaging material Substances 0.000 claims description 77
- 238000004806 packaging method and process Methods 0.000 claims description 47
- 238000001746 injection moulding Methods 0.000 claims description 22
- 238000012858 packaging process Methods 0.000 claims description 20
- 238000012546 transfer Methods 0.000 claims description 19
- 229910000679 solder Inorganic materials 0.000 claims description 14
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- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 3
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- 238000007796 conventional method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000013007 heat curing Methods 0.000 description 1
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- 239000004065 semiconductor Substances 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
1234213 五、發明說明α) 【發明所屬之技術領域】 本發明是有關於一種晶片封裝結構及其製程，且特別 是有關於一種行動通訊所需之超薄型（U 1 t r a t h i η )的晶片 封裝（Chip packaging)結構及其製程。 【先前技術】 在高度情報化社會的今日，可攜式電子裝置 (Portable electric device)的市場不斷地急速擴張著。 晶片封裝技術亦需配合電子裝置的數位化、網路化、區域 連接化以及使用人性化的趨勢發展。為達成上述的要求， 必須強化電子元件的高速處理化、多功能化、積集 (I n t e g r a t i〇η )化、小型輕量化及低價化等多方面的要 求，於是晶片封裝技術也跟著朝向微型化、高密度化發 展。其中，覆晶接合（Flip Chip bonding, F/C bonding) 技術由於係以凸塊（B u m p )與載板（C a r r i e r )接合，較習知 導線連結（W i r e b ο n d i n g )法大幅縮短了配線長度，有助晶 片與載板間訊號傳遞速度的提昇，因此已漸成為高密度封 裝的主流。 第1圖繪示為習知採覆晶接合技術的晶片封裝結構之 剖面圖。請參照第1圖，晶片5 0具有一主動表面5 2 ，且主 動表面52上更配置有多個焊墊（圖未示）。載板80之表面上 配置有多個接點（圖未示）。多個凸塊6 0係配置於主動表面 5 2上之焊墊上，且凸塊6 0係藉由晶片5 0之焊墊以及載板8 0 之接點而電性連接於晶片5 0與載板8 0之間。其中，載板8 0 遠離晶片5 0之表面更配置有多個陣列排列之焊球（S ο 1 d e r1234213 V. Description of the invention α) [Technical field to which the invention belongs] The present invention relates to a chip packaging structure and a manufacturing process thereof, and more particularly to an ultra-thin (U 1 trathi η) chip package required for mobile communication. (Chip packaging) structure and process. [Previous Technology] In today's highly informative society, the market for portable electric devices continues to expand rapidly. Chip packaging technology also needs to cooperate with the trend of digitalization, networking, regional connection, and user-friendly use of electronic devices. In order to meet the above-mentioned requirements, it is necessary to strengthen the various requirements of high-speed processing, multifunctionalization, integration, miniaturization, and low cost of electronic components. Therefore, chip packaging technology is also moving toward micro High-density development. Among them, because Flip Chip bonding (F / C bonding) technology uses bumps and Carriers to bond, it greatly shortens the wiring compared to the conventional wire bonding method. Length, which helps to improve the signal transmission speed between the chip and the carrier, has gradually become the mainstream of high-density packaging. FIG. 1 is a cross-sectional view of a chip package structure using a conventional flip-chip bonding technology. Referring to FIG. 1, the wafer 50 has an active surface 5 2, and a plurality of solder pads (not shown) are further disposed on the active surface 52. A plurality of contacts (not shown) are arranged on the surface of the carrier plate 80. The plurality of bumps 60 are arranged on the pads on the active surface 52, and the bumps 60 are electrically connected to the wafer 50 and the carrier through the pads of the wafer 50 and the contacts of the carrier board 80. Board between 80. Among them, the surface of the carrier plate 8 0 far from the wafer 50 is further provided with a plurality of solder balls arranged in an array (S ο 1 d e r
11846twf.ptd 第8頁 1234213 五、發明說明（2) b a 1 1 ) 6 0 ’亦即晶片封裝結構1 〇係採用球格陣列封裝（B a 1 1 Grid Array packaging, BGA packaging)，以使晶片去寸裝 結構10能與印刷電路板（Printed circuit board, PC B)電 性連接。 為了保護晶片5 0使其免於受到濕氣的破壞，同時保護 連接晶片5 0與載板8 0的凸塊6 0 ，使其免於受到剪切應力 (Shear ί o r c e )破壞，因此更形成一封裝材料層7 0於晶片 5 0與載板8 0之間。習知形成封裝材料層7 0之方式係利用毛 細現象，將黏度較低的液態封裝材料填入晶片5 0與載板8 0 之間的覆晶接合間隙，之後再將封裝材料硬化。 承上所述，晶片封裝結構1 0較習知導線連結式的晶片 封裝結構具有更佳電氣性能，且厚度亦符合行動通信裝置 等元件所需的超薄要求。但是，封裝材料填入覆晶接合間 隙所需之時間較長，不符合產業界對產能的要求。而且， 由於封裝材料係藉助自然的毛細現象填入覆晶接合間隙， 因此晶片5 0與載板8 0之間凸塊6 0的數目、排列方式與覆晶 接合間隙的大小，都會影響封裝材料的流動性，導致封裝 材料填入不完全而形成空洞，進而影響封裝信賴度 (Reliability) 〇 此外，由於晶片5 0係直接暴露於外界，因此在標記 (M a r k i n g )晶片特性於晶片5 0表面時，或是在藉由真空吸 附晶片5 0以移動晶片封裝結構1 0時，都很容易造成晶片5 0 的破壞。為改善此缺點，更產生了另一習知晶片封裝結 構。第2 A圖與第2 B圖即繪示另一種習知採覆晶接合技術的11846twf.ptd Page 8 1234213 V. Description of the invention (2) ba 1 1) 6 0 ', that is, the chip package structure 1 〇 uses ball grid array packaging (B a 1 1 Grid Array packaging, BGA packaging), so that the chip The de-inching structure 10 can be electrically connected to a printed circuit board (PC B). In order to protect the wafer 50 from being damaged by moisture, and to protect the bumps 60 connecting the wafer 50 and the carrier plate 80 from the shear stress, it is further formed. A packaging material layer 70 is between the chip 50 and the carrier board 80. The conventional way to form the packaging material layer 70 is to use a capillary phenomenon to fill a chip-on-chip bonding gap between the wafer 50 and the carrier plate 80 with a low-viscosity liquid packaging material, and then harden the packaging material. As mentioned above, the chip package structure 10 has better electrical performance than the conventional wire-connected chip package structure, and the thickness also meets the ultra-thin requirements required for components such as mobile communication devices. However, it takes a long time for the packaging material to fill the flip-chip bonding gap, which does not meet the industry's requirements for capacity. In addition, since the packaging material fills the flip-chip bonding gap with the help of natural capillary phenomena, the number of bumps 60, the arrangement manner of the wafer 50 and the carrier plate 80, and the size of the flip-chip bonding gap will affect the packaging material. The fluidity of the package leads to incomplete filling of the packaging material and the formation of voids, which in turn affects the reliability of the package. In addition, since the wafer 50 is directly exposed to the outside, the characteristics of the marking wafer are on the surface of the wafer 50. At times, or when the wafer packaging structure 10 is moved by vacuum-absorbing the wafer 50, the wafer 50 is easily damaged. To improve this disadvantage, another conventional chip packaging structure has been created. Figures 2A and 2B show another conventional technique for flip chip bonding.
11846twf.ptd 第9頁 1234213 五、發明說明（3) 晶片封裝結構之剖面圖。請參照第2 A圖，晶片封裝結構1 2 係於第1圖之晶片封裝結構1 0上更增加一頂部模封層（0 v e r m ο 1 d ) 7 2，以保護晶片5 0在進行標記與移動時不受到破 壞。 但是，形成頂部模封層7 2所需之製程時間將相對造成 產能下降，而且在封裝材料層7 0與頂部模封層7 2之介面亦 容易發生介面剝離（D e 1 a m i n a t i ο η )的現象，進而降低晶片 封裝結構1 2之可靠度。 因此，根據第2 Α圖之晶片封裝結構1 2進行改進，第2 Β 圖之晶片封裝結構1 4亦被揭露。晶片封裝結構1 4由於係一 次形成封裝材料層74 ’以覆盖晶片50與載板8 0並填充封裝 材料於晶片5 0與載板8 0之間，因此可避免發生介面剝離的 缺點。但是，若欲採用移轉注模（T r a n s f e r m ο 1 d )成形法 形成封裝材料層7 4 ’則一般在晶片上方之封裝材料層7 4之 厚度需設計在0 . 2毫米以上，以避免膠材填充不完全，如 此將無法滿足行動通信裝置所需的超薄要求。 【發明内容】 因此，本發明的目的就是在提供一晶片封裝結構及其 製程，適於提升晶片封裝結構之產能與可靠度，且滿足行 動通信裝置所需之超薄尺寸。 基於上述目的，本發明提出一種晶片封裝結構，主要 係由一載板、一晶片與一封裝材料層所構成。其中’晶片 具有一主動表面，主動表面上配置有多個凸塊。晶片係以 主動表面朝向載板而覆晶接合於載板上，且電性連接至載11846twf.ptd Page 9 1234213 V. Description of the invention (3) A cross-sectional view of a chip package structure. Please refer to FIG. 2A. The chip package structure 1 2 is based on the chip package structure 10 of FIG. 1 and a top mold layer (0 verm ο 1 d) 7 2 is added to protect the chip 50 during marking and No damage when moving. However, the process time required to form the top mold layer 7 2 will relatively reduce the production capacity, and the interface between the packaging material layer 70 and the top mold layer 7 2 is also prone to interface peeling (D e 1 aminati ο η). Phenomenon, thereby reducing the reliability of the chip package structure 12. Therefore, the chip package structure 12 in FIG. 2A is improved, and the chip package structure 14 in FIG. 2B is also disclosed. Since the chip package structure 14 is formed with the packaging material layer 74 'once to cover the wafer 50 and the carrier board 80 and fill the packaging material between the wafer 50 and the carrier board 80, the disadvantage of interface peeling can be avoided. However, if the transfer material (T ransferm ο 1 d) forming method is to be used to form the packaging material layer 7 4 ′, the thickness of the packaging material layer 74 above the wafer generally needs to be designed at 0.2 mm or more to avoid the glue material. The padding is incomplete, so it will not meet the ultra-thin requirements required for mobile communication devices. [Summary of the Invention] Therefore, an object of the present invention is to provide a chip packaging structure and a manufacturing process thereof, which are suitable for improving the productivity and reliability of the chip packaging structure and satisfying the ultra-thin size required for a mobile communication device. Based on the above objectives, the present invention proposes a chip packaging structure, which is mainly composed of a carrier board, a wafer, and a packaging material layer. The 'wafer has an active surface, and a plurality of bumps are arranged on the active surface. The chip is bonded to the carrier with the active surface facing the carrier, and is electrically connected to the carrier.
11846twf.ptd 第10頁 1234213 五、發明說明（4) 板。封裝材料層係填充於晶片與載板之間且覆蓋晶片與載 板。 而且，封裝材料層位於晶片與載板之間的部份具有一 第一厚度，封裝材料層位於晶片上方的部份具有一第二厚 度。其中，第二厚度係介於第一厚度的0 . 5〜2倍之間。 基於上述目的，本發明再提出一種晶片封裝結構，主 要係由一載板、一晶片組與一封裝材料層所構成。其中’ 晶片組係配置於載板上並與載板電性連接。晶片組主要係 由多個晶片所構成，且其中至少有一晶片係覆晶接合於載 板或其他晶片上，並且維持一覆晶接合間隙。封裝材料層 係完全填充於覆晶接合間隙内且覆蓋晶片組與載板。 而且，覆晶接合間隙内之封裝材料層具有一第一厚 度，晶片組上方之封裝材料層具有一第二厚度。其中，第 二厚度係介於第一厚度的0 . 5〜2倍之間。 另外，本實施例之晶片組主要例如係由一第i晶片與 一第二晶片所構成。其中，第一晶片具有一第一主動表 面，且第一晶片係以第一主動表面背向載板而配置於載板 上。第二晶片具有一第二主動表面，第二主動表面上配置 有多數個凸塊。第二晶片係以第二主動表面朝向第一晶片 而覆晶接合於第一晶片上，並電性連接至第一晶片。而凸 塊係維持覆晶接合間隙。 此外，晶片組例如更包括多條導線。其中，每條導線 之兩端例如係分別電性連接第一晶片與載板。 此外，本實施例之晶片組亦可主要由一第一晶片、一11846twf.ptd Page 10 1234213 V. Description of Invention (4) Board. The packaging material layer is filled between the wafer and the carrier board and covers the wafer and the carrier board. Moreover, a portion of the packaging material layer located between the wafer and the carrier board has a first thickness, and a portion of the packaging material layer located above the wafer has a second thickness. Wherein, the second thickness is between 0.5 and 2 times the first thickness. Based on the above object, the present invention further proposes a chip packaging structure, which is mainly composed of a carrier board, a chip set, and a packaging material layer. Among them, the chip set is disposed on the carrier board and electrically connected to the carrier board. The chip set is mainly composed of multiple wafers, and at least one of the wafers is bonded to a carrier or other wafers, and a flip-chip bonding gap is maintained. The packaging material layer is completely filled in the flip-chip bonding gap and covers the chipset and the carrier. Moreover, the packaging material layer in the flip-chip bonding gap has a first thickness, and the packaging material layer above the chipset has a second thickness. Wherein, the second thickness is between 0.5 and 2 times the first thickness. In addition, the wafer set of this embodiment is mainly composed of an i-th wafer and a second wafer, for example. The first chip has a first active surface, and the first chip is disposed on the carrier board with the first active surface facing away from the carrier board. The second wafer has a second active surface, and a plurality of bumps are disposed on the second active surface. The second chip is flip-chip bonded to the first chip with the second active surface facing the first chip, and is electrically connected to the first chip. The bumps maintain the flip-chip bonding gap. In addition, the chipset further includes a plurality of wires, for example. The two ends of each wire are electrically connected to the first chip and the carrier board, respectively. In addition, the chip set of this embodiment may be mainly composed of a first chip, a
11846twf.ptd 第11頁 1234213 五、 發明說明（5) 第 二 晶 片 與 — 第 二 晶 片 所 構 成 〇 其 中 j 第 一 晶 片 具 有 一 第 一 主 動 表 面 第 一 主 動 表 面 上 配 置 有 多 個 第 一 凸 塊 〇 第 一 晶 片 係 以 第 一 主 動 表 面 朝 向 載 板 而 覆 晶 接 合 於 載 板 上 並 電 性 連 接 至 載 板 〇 第 二 晶 片 具 有 — 第 二 主 動 表 面 且 第 二 晶 片 係 以 第 二 主 動 表 面 背 向 第 一 晶 片 而 配 置 於 第 — 晶 片 上 〇 第 二 晶 片 具 有 一 第 二 主 動 表 面 ， 第 主 動 表 面 上 配 置 有 多 個 第 二 凸 塊 〇 第 二 晶 片 係 以 第 --- 主 動 表 面 朝 向 第 二 晶 片 而 覆 晶 接 合 於 第 二 晶 片 上 並 電 性 連 接 至 第 二 晶 片 〇 而 第 一 凸 塊 與 第 二 凸 塊 係 維 持 覆 晶 接 合 間 隙 〇 此 外 晶 片 組 例 如 更 包 括 多 條 導 線 〇 其 中 每 條 導 線 之 兩 端 例 如 係 分 別 電 性 連 接 第 二 晶 片 與 載 板 〇 在 上 述 晶 片 封 裝 結 構 之 兩 種 實 施 例 中 ， 封 裝 材 料 層 之 最 大 材 料 粒 徑 例 如 係 小 於 第 一 厚 度 之0. 5倍c ，晶片封裝結 構 例 如 更 包 括 多 個 焊 球 與 至 少 一 被 動 元 件 〇 其 中 5 焊 球 例 如 係 陣 列 排 列 地 配 置 於 載 板 未 配 置 晶 片 之 表 面 上 〇 被 動 元 件 例 如 係 配 置 於 載 板 上 9 且 與 載 板 電 性 連 接 〇 載 板 例 如 係 —· 封 裝 基 材 或 一 導 線 架 Ο 基 於 上 述 的 本 發 明 另 提 出 一 種 晶 片 封 裝 製 程 9 主 要 包 括 下 列 步 驟 ; (a )提供- -載板與多個晶片： ’每個晶片 分 別 具 有 一 主 動 表 面 至 少 —· 主 動 表 面 上 配 置 有 多 個 凸 塊 〇 (b )使^ 晶片與載板電性連接1 0 ( c ) 形 成 一 封 裝 材 料 層 於 晶 片 與 載 板 之 間 9 且 覆 蓋 晶 片 與 載 板 〇 其 中 封 裝 材 料 層 位 於 晶 片 與 載 板 之 間 的 部 份 具 有 一 第 厚 度 1 封 裝 材 料 層 位 於 晶 片 上 方 的 部 份 具 有 第 厚11846twf.ptd Page 11 1234213 V. Description of the invention (5) The second wafer and-the second wafer are constituted, where j the first wafer has a first active surface and a plurality of first bumps are arranged on the first active surface. The first wafer has a first active surface facing the carrier board and is flip-chip bonded to the carrier board and is electrically connected to the carrier board. The second wafer has a second active surface and the second wafer has the second active surface facing away from the first One wafer is disposed on the first wafer. The second wafer has a second active surface, and a plurality of second bumps are disposed on the first active surface. The second wafer is covered with the first active surface facing the second wafer. The die is bonded on the second wafer and is electrically connected to the second wafer. The first bump and the second bump maintain a flip-chip bonding gap. In addition, the wafer set includes, for example, a plurality of wafers. The two ends of each wire, for example, are electrically connected to the second chip and the carrier board respectively. In the two embodiments of the chip packaging structure described above, the maximum material particle diameter of the packaging material layer is, for example, less than 0 of the first thickness. 5 times c, the chip package structure, for example, further includes a plurality of solder balls and at least one passive component. Among them, 5 solder balls are arranged in an array on the surface of the carrier plate without the wafer. Passive components are arranged on the carrier plate, for example. 9 and is electrically connected to the carrier board. The carrier board is, for example, a packaging substrate or a lead frame. Based on the above-mentioned present invention, another chip packaging process 9 is proposed, which mainly includes the following steps; (a) provide-carrier board and multi- Each wafer: 'Each wafer has an active surface at least-a plurality of bumps are arranged on the active surface 0 (b) so that ^ the wafer and the carrier board are electrically connected 1 0 (c) to form Encapsulation material layer between the wafer and the carrier's 9 and the cover wafer and the carrier square wherein the encapsulating material layer located between the wafer and the carrier of the portion parts has a first thickness of a package material layer is located on parts of portion having the wafer side has a first thickness
11846twf.ptd 第12頁 1234213 五、發明說明（6) 度。第二厚度係介於第一厚度的〇 . 5〜2倍之間。 此外，形成封裝材料層的方法例如係一減壓移轉注模 成形法。形成封裝材料層後例如更包括對載板進行切割， 以形成多個晶片封裝結構。而且，進行減壓移轉注模成形 法之壓力例如係保持在2 0毫米-汞柱（m m - H g 〇 r T 〇 r r )以 下，溫度例如至少較凸塊之熔點低攝氏1 0度。封裝材料層 之最大材料粒徑係小於第一厚度之0 . 5倍。 綜上所述，根據本發明所提出之晶片封裝結構及其製 程，由於晶片上覆蓋有封裝材料層（亦即頂部模封層），因 此可避免直接標記晶片特性於晶片上，以及移動晶片封裝 結構時直接接觸晶片，進而降低晶片損壞的機率。而且， 由於晶片上下之封裝材料層係一次完成，因此可縮短製程 時間進而增加產能。另外，經過尺寸最佳化設計之頂部模 封層厚度，則可確保封裝製程的可靠度。 為讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細 說明如下。 【實施方式】11846twf.ptd Page 12 1234213 V. Description of the invention (6) Degree. The second thickness is between 0.5 and 2 times the first thickness. In addition, the method of forming the packaging material layer is, for example, a reduced-pressure transfer injection molding method. Forming the packaging material layer further includes, for example, cutting the carrier board to form a plurality of chip packaging structures. Further, the pressure for performing the decompression transfer injection molding method is, for example, kept below 20 mm-Hg (m m-H g ○ r T ○ r r), and the temperature is, for example, at least 10 degrees Celsius lower than the melting point of the bump. The maximum material particle size of the packaging material layer is less than 0.5 times the first thickness. In summary, according to the chip packaging structure and the process of the present invention, since the wafer is covered with a layer of packaging material (ie, the top mold layer), it is possible to avoid directly marking the characteristics of the wafer on the wafer and moving the chip package The structure directly contacts the wafer, thereby reducing the chance of wafer damage. In addition, since the packaging material layer above and below the wafer is completed at one time, the process time can be shortened and the productivity can be increased. In addition, the thickness of the top mold layer is optimized to ensure the reliability of the packaging process. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, preferred embodiments are described below in detail with the accompanying drawings, as follows. [Embodiment]
第3圖繪示為根據本發明所提出之第一較佳實施例的 晶片封裝結構之剖面圖。請參照第3圖，晶片封裝結構1 0 0 主要係由一載板1 8 0、一晶片1 5 0與一封裝材料層1 7 0所構 成。其中，載板1 8 0例如係有機基板、陶瓷基板、可撓性 基板等封裝基材，亦或是例如覆晶式四方扁平封裝（F 1 i p Chip Quad Flat Non-leaded packaging, F/C QFNFIG. 3 is a cross-sectional view of a chip package structure according to a first preferred embodiment of the present invention. Referring to FIG. 3, the chip package structure 100 is mainly composed of a carrier board 180, a chip 150, and a packaging material layer 170. Among them, the carrier board 180 is, for example, an packaging substrate such as an organic substrate, a ceramic substrate, or a flexible substrate, or it may be, for example, a flip chip quad flat non-leaded packaging (F / C QFN).
11846twf.ptd 第13頁 1234213 五、發明說明（7) packaging)等封裝製程所使用之導線架（Lead frame)。載 板1 8 0之上下表面例如具有多個接點（圖未示）。 晶片1 5 0具有一主動表面1 5 2 ，且晶片1 5 0係以主動表 面1 5 2朝向載板1 8 0而覆晶接合於載板1 8 0之上表面上。晶 片1 5 0之主動表面上例如配置有多個焊墊（圖未示），多個 凸塊1 6 0係配置於晶片1 5 0之主動表面1 5 2上之焊墊上。晶 片1 5 0係藉由焊墊上之凸塊1 6 0而電性連接至載板1 8 0。亦 即，本實施例之晶片封裝結構1 0 0中至少包括了 一晶片 1 5 0，且此晶片1 5 0係採用覆晶接合技術接合於載板1 8 0之 上表面上。然而，除了此晶片1 5 0之外，本實施例亦可在 封裝結構1 0 0中的載板1 8 0上設置其他晶片或其他元件 (component )，如電阻、電容等被動元件。 此外，封裝材料層1 7 0係填充於晶片1 5 0與載板1 8 0之 間，並且覆蓋晶片1 5 0裸露之表面以及載板1 8 0之上表面。 因此，不論是在後續製程中欲在晶片封裝結構1 0 0上標記 一些晶片特性，或是欲以真空吸附方式移動晶片封裝結構 1 0 0時，都不需擔心會破壞晶片1 5 0之背面，同時獲得清晰 之標記效果。 同樣請參照第3圖，本實施例中，封裝材料層1 7 0位於 晶片1 5 0與載板1 8 0之間的部份具有一第一厚度T 1 ，封裝材 料層1 7 0位於晶片1 5 0上方的部份（亦即頂部模封層）具有一 第二厚度T2。其中，第二厚度T2係介於第一厚度T1的0.5 〜2倍之間。 晶片封裝結構1 0 0例如更包括多個陣列排列之焊球1 9 011846twf.ptd Page 13 1234213 V. Description of the invention (7) Packaging) and other lead frames used in packaging processes. The upper and lower surfaces of the carrier plate 180 have, for example, a plurality of contacts (not shown). The chip 150 has an active surface 15 2, and the chip 150 is bonded to the upper surface of the carrier plate 180 with the active surface 15 2 facing the carrier plate 180. For example, a plurality of solder pads (not shown) are arranged on the active surface of the wafer 150, and a plurality of bumps 160 are disposed on the solder pads on the active surface 15 of the wafer 150. The wafer 150 is electrically connected to the carrier board 180 through the bump 160 on the solder pad. That is, the wafer package structure 100 of this embodiment includes at least one wafer 150, and the wafer 150 is bonded to the upper surface of the carrier board 180 using a flip-chip bonding technology. However, in addition to the chip 150, in this embodiment, other chips or other components (such as resistors, capacitors, and other passive components) may be provided on the carrier board 180 in the package structure 100. In addition, the packaging material layer 170 is filled between the wafer 150 and the carrier board 180 and covers the exposed surface of the wafer 150 and the upper surface of the carrier board 180. Therefore, no matter if you want to mark some chip characteristics on the chip packaging structure 100 in the subsequent process, or if you want to move the chip packaging structure 100 by vacuum suction, you do not need to worry about damaging the back of the chip 150. And get a clear marking effect. Please also refer to FIG. 3. In this embodiment, a portion between the packaging material layer 170 located between the wafer 150 and the carrier plate 180 has a first thickness T1, and the packaging material layer 170 located on the wafer The part above 150 (ie, the top mold layer) has a second thickness T2. The second thickness T2 is between 0.5 and 2 times the first thickness T1. The chip package structure 1 0 0 further includes a plurality of solder balls arranged in an array 1 9 0
11846twf.ptd 第14頁 1234213 五、發明說明（8) 與至少一被動元件1 9 5 ◦其中，焊球1 9 0例如係配置於載板 1 8 0下表面之接點上。焊球1 9 0係提供晶片封裝結構1 0 0之 後例如與印刷電路板電性連接之用途。被動元件1 9 5例如 係配置於載板1 8 0之上表面上，且與載板1 8 0電性連接。 值得注意的是，本發明不同於第2 A圖之習知晶片封裝 結構，本發明之晶片封裝結構1 〇 〇中，各部分之封裝材料 層係一次成形，因此可避免在分次成形之封裝材料的介面 上發生介面剝離。而且，封裝材料層1 7 0之最大材料粒徑 例如係小於第一厚度之0 . 5倍。 第4圖與第5圖繪示為根據本發明所提出之第二較佳實 施例的晶片封裝結構之剖面圖。請共同參照第4圖與第5 圖，晶片封裝結構2 0 0主要係由一載板2 8 0 、一晶片組2 50 與一封裝材料層2 7 0所構成。其中，晶片組2 5 0主要係由多 個晶片所構成，且其中至少有一晶片係以覆晶接合技術接 合於載板2 8 0或其他晶片上。因此，晶片組2 5 0内至少存在 一覆晶接合間隙2 5 6 ，覆晶接合間隙2 5 6係由採用覆晶接合 之晶片上的凸塊所形成。封裝材料層2 7 0係充滿於覆晶接 合間隙2 5 6内，且覆蓋晶片組2 5 0所裸露之表面以及載板 1 80 上。 而且，覆晶接合間隙2 5 6内之封裝材料層2 7 0具有一第 一厚度T1 ，晶片組2 5 0上方之封裝材料層2 7 0具有一第二厚 度T2。其中，第二厚度T2係介於第一厚度T1的0.5〜2倍之 間。 請參照第4圖，本較佳實施例之晶片組2 5 0主要例如係11846twf.ptd Page 14 1234213 V. Description of the invention (8) and at least one passive component 195 ◦ Among them, the solder ball 190 is, for example, arranged on a contact on the lower surface of the carrier plate 180. The solder ball 190 is provided for use after the chip package structure 100, for example, for electrical connection with a printed circuit board. The passive component 195 is, for example, disposed on the upper surface of the carrier board 180 and is electrically connected to the carrier board 180. It is worth noting that the present invention is different from the conventional wafer packaging structure of FIG. 2A. In the wafer packaging structure 1000 of the present invention, the packaging material layers of each part are formed at one time, so the packaging can be avoided in the divided molding. Interface peeling occurred on the interface of the material. Moreover, the maximum material particle diameter of the packaging material layer 170 is, for example, less than 0.5 times the first thickness. 4 and 5 are cross-sectional views of a chip package structure according to a second preferred embodiment of the present invention. Please refer to FIG. 4 and FIG. 5 together. The chip package structure 200 is mainly composed of a carrier board 2 80, a chip group 2 50, and a packaging material layer 2 70. Among them, the chip set 250 is mainly composed of a plurality of wafers, and at least one of the chips is bonded to a carrier board 280 or other wafers by a flip-chip bonding technology. Therefore, at least one flip-chip bonding gap 2 5 6 exists in the wafer group 250, and the flip-chip bonding gap 2 56 is formed by bumps on the wafer using flip-chip bonding. The packaging material layer 270 is filled in the flip-chip bonding gap 256 and covers the exposed surface of the chipset 250 and the carrier plate 1 80. Moreover, the encapsulation material layer 270 in the flip-chip bonding gap 256 has a first thickness T1, and the encapsulation material layer 270 above the chipset 250 has a second thickness T2. The second thickness T2 is between 0.5 and 2 times the first thickness T1. Please refer to FIG. 4. The chipset 2 50 of the preferred embodiment is mainly
11846twf.ptd 第15頁 1234213 五、發明說明（9) 由一第一晶片250a與一第二晶片250b所構成。其中，各元 件之配置關係如下所述。第一晶片2 5 0 a具有一第一主動表 面252a ，且第一晶片250a係以第一主動表面252a朝上而配 置於載板2 8 0上。第二晶片2 5 0 b具有一第二主動表面 252b，第二主動表面252b上配置有多數個凸塊260。第二 晶片2 5 0 b係以第二主動表面2 5 2 b朝向第一晶片2 5 0 a而覆晶 接合於第一晶片2 5 0 a上，並電性連接至第一晶片2 5 0 a。而 凸塊2 6 0係維持覆晶接合間隙2 5 6。 此外，晶片組2 5 0例如更包括多條導線2 5 4b。載板2 80 之表面上例如配置有多個接點（圖未示），第一晶片2 5 0 a之 第一主動表面252a以及第二晶片250b之第二主動表面252b 上例如配置有多個焊墊（圖未示）。第二晶片2 5 0 b之凸塊 2 6 0即維持覆晶接合間隙2 5 6於第一晶片2 5 0 a與第二晶片 2 5 0 b之間。換言之，第二晶片2 5 0 b係以覆晶接合技術接合 於第一晶片250a之第一主動表面252a上。每條導線254b之 兩端例如係分別電性連接第一晶片2 5 0 a之焊墊與載板2 8 0 之接點。 請參照第5圖，本較佳實施例之晶片組2 5 0例如係由一 第一晶片2 5 0 a 、一第二晶片2 5 0 b與一第三晶片2 5 0 c所構 成。晶片組2 5 0例如更包括多條導線2 5 4b。其中，各元件 之配置關係如下所述。第一晶片2 5 0 a係配置於載板2 8 0 上，且第一晶片250a具有一第一主動表面252a ，第一主動 表面252a上配置有多個第一凸塊260a。第一晶片250a係以 第一主動表面2 5 2 a朝向載板2 8 0而覆晶接合於載板2 8 0上，11846twf.ptd Page 15 1234213 V. Description of the invention (9) It consists of a first wafer 250a and a second wafer 250b. Among them, the arrangement relationship of each element is as follows. The first wafer 250a has a first active surface 252a, and the first wafer 250a is disposed on the carrier plate 280 with the first active surface 252a facing upward. The second wafer 250b has a second active surface 252b, and a plurality of bumps 260 are disposed on the second active surface 252b. The second wafer 2 5 0 b is bonded to the first wafer 2 5 0 a with the second active surface 2 5 2 b facing the first wafer 2 5 0 a and is electrically connected to the first wafer 2 5 0 a. The bump 2 6 0 maintains the flip-chip bonding gap 2 5 6. In addition, the chip set 2 50 further includes, for example, a plurality of wires 2 5 4b. For example, a plurality of contacts (not shown) are arranged on the surface of the carrier plate 2 80. For example, a plurality of first active surfaces 252a of the first chip 250a and a second active surface 252b of the second chip 250b are disposed. Pad (not shown). The bump 2 60 of the second wafer 2 5 0 b maintains the flip-chip bonding gap 2 5 6 between the first wafer 2 50 a and the second wafer 2 5 0 b. In other words, the second wafer 250b is bonded to the first active surface 252a of the first wafer 250a by a flip-chip bonding technique. The two ends of each wire 254b are, for example, electrically connected to the contacts of the soldering pad of the first chip 250a and the carrier 2800 respectively. Referring to FIG. 5, the wafer set 2 50 of the preferred embodiment is composed of a first wafer 2 50 a, a second wafer 2 5 0 b, and a third wafer 2 5 0 c, for example. The chip set 2 5 0 further includes a plurality of wires 2 5 4b, for example. Among them, the arrangement relationship of each element is as follows. The first wafer 250a is disposed on the carrier board 280, and the first wafer 250a has a first active surface 252a. A plurality of first bumps 260a are disposed on the first active surface 252a. The first chip 250a is bonded to the carrier plate 2 8 0 with the first active surface 2 5 2 a facing the carrier plate 2 8 0.
11846twf.ptd 第16頁 1234213 五、發明說明（10) 並電性連接至載板280。第二晶片250b具有一第二主動表 面252b ，第二主動表面252b係背向第一晶片250a。而且， 多條導線2 5 4 b係連接於第二晶片2 5 0 b之第二主動表面2 5 2 b 上的焊墊，以及載板2 8 0的接點之間，以電性連接第二晶 片250b與載板2 80 。第三晶片250c具有一第三主動表面 252c ，第三主動表面252c上配置有多個第二凸塊260b。第 三晶片250c係以第三主動表面252c朝向第二晶片250b而覆 晶接合於第二晶片2 5 0 b上，並電性連接至第二晶片2 5 0 b。 而第一凸塊2 6 0 a與第二凸塊2 6 0 b係維持覆晶接合間隙 2 5 6。換言之，第三晶片2 5 0 c係以覆晶接合技術接合於第 二晶片2 5 0 b之第二主動表面2 5 2 b ，第一晶片2 5 0 a係以覆晶 接合技術接合於載板2 5 0 b之表面。 在本實施例中，由於晶片封裝機構中具有多個覆晶接 合間隙，因此晶片組上方之封裝材料層的厚度應控制在大 於較小之覆晶接合間隙的0 . 5倍，以及小於較大之覆晶接 合間隙的2倍之間，以符合本發明之特徵精神。 在本發明所提出之第二較佳實施例中，與第一較佳實 施例相較主要係增加晶片之數量，同時不限定所有晶片皆 採用覆晶接合技術與載板接合。本發明之最主要特徵仍在 於晶片封裝結構中至少包括一晶片，且此晶片係採用覆晶 接合技術與載板或是其他晶片接合。而且，晶片上方之封 裝材料層的厚度係介於覆晶接合間隙的〇 . 5〜2倍之間。只 要符合上述主要特徵之任何實施樣態，皆應屬於本發明所 欲保護之範圍。 III 1 11846twf.ptd 第17頁 1234213 五、發明說明（π) 以下將介紹本發明所提出之較佳實施例的晶片封裝製 程，並且詳細介紹其實施方式。晶片封裝製程主要包括下 列步驟：（a )提供一載板與多個晶片，每個晶片分別具有 一主動表面，至少一主動表面上配置有多個凸塊。（b)使 晶片與載板電性連接。（d )形成一封裝材料層於些晶片與 載板上，並使封裝材料層填充於晶片與載板之間。 完成此晶片封裝製程所得到之晶片封裝結構具有下列 特徵。第6 A圖繪示為根據本發明所提出之較佳實施例的晶 片封裝製程之成品的剖面圖。請參照第6 A圖，封裝材料層 1 7 0位於晶片1 5 0與載板1 8 0之間的部份具有一第一厚度 T 1 ，封裝材料層1 8 0位於晶片1 5 0上方的部份具有一第二厚 度T 2。第二厚度係介於第一厚度的0 . 5〜2倍之間。 第6 B圖繪示為根據本發明所提出之較佳實施例的晶片 封裝製程之成品經切割後的剖面圖。請共同參照第6 A圖與 第6 B圖，為符合量產所需，本較佳實施例之封裝製程在形 成封裝材料層1 7 0後，例如更沿切割線L進行切割，以形成 多個晶片封裝結構1 0 0。其中，每個晶片封裝結構1 0 0至少 包括一個晶片1 5 0 。另外，雖然在第6 A圖中繪示之封裝材 料層1 7 0係連接為一體，但亦可調整製程模具，形成多個 互相獨立之封裝材料層1 7 0，亦即在切割線部份不形成封 裝材料層，以縮短後續切割所需之時間。 值得注意的是，在根據本發明所提出之較佳實施例的 晶片封裝製程中，形成封裝材料層的方法例如係一減壓移 轉注模成形法。減壓移轉注模成形法係指將欲封裝之晶片11846twf.ptd Page 16 1234213 V. Description of the invention (10) It is electrically connected to the carrier board 280. The second wafer 250b has a second active surface 252b, and the second active surface 252b faces away from the first wafer 250a. In addition, a plurality of wires 2 5 4 b are electrically connected to the pads on the second active surface 2 5 2 b of the second chip 2 50 b and the contacts of the carrier board 2 0 0 to electrically connect the Two wafers 250b and a carrier plate 2 80. The third wafer 250c has a third active surface 252c, and a plurality of second bumps 260b are disposed on the third active surface 252c. The third wafer 250c is flip-chip bonded to the second wafer 250b with the third active surface 252c facing the second wafer 250b, and is electrically connected to the second wafer 250b. The first bump 2 6 0 a and the second bump 2 6 0 b maintain a flip-chip bonding gap 2 5 6. In other words, the third wafer 2 5 0 c is bonded to the second active surface 2 5 2 b of the second wafer 2 5 0 b by a flip-chip bonding technique, and the first wafer 2 5 0 a is bonded to the carrier by a flip-chip bonding technique. The surface of the plate 2 5 0 b. In this embodiment, since there are multiple flip-chip bonding gaps in the chip packaging mechanism, the thickness of the packaging material layer above the chip set should be controlled to be 0.5 times larger than the smaller flip-chip bonding gap and smaller than The chip-to-chip bonding gap is twice as high as the characteristic spirit of the present invention. In the second preferred embodiment proposed in the present invention, the number of wafers is mainly increased compared with the first preferred embodiment, and at the same time, it is not limited that all wafers are bonded to the carrier board by flip-chip bonding technology. The most important feature of the present invention is that at least one wafer is included in the chip packaging structure, and the wafer is bonded to a carrier board or other wafers using a flip-chip bonding technology. Moreover, the thickness of the packaging material layer above the wafer is between 0.5 and 2 times the flip-chip bonding gap. Any embodiment that meets the above-mentioned main features should fall within the protection scope of the present invention. III 1 11846twf.ptd Page 17 1234213 V. Description of the Invention (π) The following will describe the chip packaging process of the preferred embodiment of the present invention, and its implementation mode will be described in detail. The chip packaging process mainly includes the following steps: (a) providing a carrier board and a plurality of wafers, each of which has an active surface, and at least one active surface is provided with a plurality of bumps. (B) The chip and the carrier are electrically connected. (D) forming a packaging material layer on the wafers and the carrier board, and filling the packaging material layer between the wafer and the carrier board. The chip packaging structure obtained by completing this chip packaging process has the following characteristics. FIG. 6A is a cross-sectional view of a finished product of a wafer packaging process according to a preferred embodiment of the present invention. Please refer to FIG. 6A. The portion between the packaging material layer 170 located between the wafer 150 and the carrier plate 180 has a first thickness T1, and the packaging material layer 180 located above the wafer 150 The portion has a second thickness T 2. The second thickness is between 0.5 and 2 times the first thickness. FIG. 6B is a cross-sectional view of a finished product of a chip packaging process according to a preferred embodiment of the present invention after cutting. Please refer to FIG. 6A and FIG. 6B together. In order to meet the needs of mass production, the packaging process of the preferred embodiment after forming the packaging material layer 170, for example, cutting along the cutting line L to form multiple Chip package structure 100. Wherein, each of the chip package structures 100 includes at least one chip 150. In addition, although the packaging material layer 170 shown in Figure 6A is connected as a whole, the process mold can also be adjusted to form multiple independent packaging material layers 170, that is, in the cutting line portion No packaging material layer is formed to reduce the time required for subsequent cutting. It is worth noting that, in the chip packaging process according to the preferred embodiment of the present invention, the method of forming the packaging material layer is, for example, a reduced pressure injection molding method. Decompression transfer injection molding method refers to the wafer to be packaged
11846twf.ptd 第18頁 1234213 五、發明說明（12) 結構放入模具，在模具進入減壓狀態後，於模具内導入熱 熔融材料，並進行加熱加壓處理使樹脂硬化的一種處理方 式。一般移轉注模成形法易造成覆晶接合間隙或頂部模封 層的封裝材料填充不足，若使模具内的減壓狀態保持在2 0 毫米-汞柱以下則可獲得較佳之封裝效果，減壓狀態之最 佳值在1 0毫米-汞柱以下。 第7圖繪示為根據本發明所提出之較佳實施例的晶片 封裝結構於減壓移轉注模成形模具中形成封裝材料層的剖 面圖。請參照第7圖，移轉注模成形設備（圖未示）可依所 需的封裝型式放置適合的模具3 0 0，模具3 0 0主要係由上模 具3 1 0與下模具3 2 0所構成。當上模具3 1 0與下模具3 2 0合模 時，為達到較有效率之真空效果，合模步驟係首先將上模 具310、下模具3 2 0與模具3 0 0内之真空橡膠封環3 3 0輕微接 觸。接著，以抽真空幫浦（圖未示）經由抽真空管路3 7 0進 行模具腔3 4 0内的減壓真空處理。然後，投入膠餅 (t a b 1 e t)(圖未示）於注膠管路3 5 0内，並維持1〜5秒以提 高空間内的真空度，同時提升模具内之溫度以使膠餅成為 熱熔融狀態之封裝材料。最後，將上模具3 1 0與下模具3 2 0 完全密合，同時拉起柱塞（p 1 u n g e r ) 3 6 0，以導入熱熔融狀 態之封裝材料，使其分別自第一路徑P 1與第二路徑P 2填滿 於模具腔3 4 0内，完成減壓移轉注模成形。 其中，晶片1 5 0上方之第一間隙G 1係介於晶片1 5 0下方 之第二間隙G 2之0 . 5〜2倍。減壓移轉注模成形在進行時， 將成形溫度控制在低於凸塊1 6 0之熔點至少攝氏1 0度為11846twf.ptd Page 18 1234213 V. Description of the invention (12) The structure is placed in a mold. After the mold enters a reduced pressure state, a hot melt material is introduced into the mold, and the resin is hardened by heat and pressure treatment. The general transfer injection molding method is likely to cause insufficient filling of the sealing material of the flip-chip bonding gap or the top mold sealing layer. If the decompression state in the mold is kept below 20 mm-Hg, a better packaging effect can be obtained and the pressure can be reduced The optimum value of the state is below 10 mm-Hg. Fig. 7 is a cross-sectional view showing a chip packaging structure forming a packaging material layer in a reduced-pressure transfer injection molding mold according to a preferred embodiment of the present invention. Please refer to Figure 7. The transfer injection molding equipment (not shown) can place the appropriate mold 3 0 0 according to the required package type. The mold 3 0 0 is mainly composed of the upper mold 3 1 0 and the lower mold 3 2 0. Make up. When the upper mold 3 1 0 and the lower mold 3 2 0 are closed, in order to achieve a more efficient vacuum effect, the mold clamping step is to firstly vacuum the rubber seals in the upper mold 310, the lower mold 3 2 0 and the mold 3 0 0. Ring 3 3 0 makes slight contact. Next, a vacuum pump (not shown) is used to perform a vacuum reduction process in the mold cavity 3 40 through the vacuum line 3 70. Then, put in the cake (tab 1 et) (not shown) in the injection pipe 3 50 and maintain it for 1 to 5 seconds to increase the vacuum in the space, while increasing the temperature in the mold to make the cake hot Packaging material in molten state. Finally, the upper mold 3 1 0 and the lower mold 3 2 0 are completely in close contact with each other, and at the same time, the plunger (p 1 unger) 3 6 0 is pulled up to introduce the packaging material in a hot-melt state from the first path P 1 And the second path P 2 is filled in the mold cavity 3 40 to complete the decompression transfer injection molding. The first gap G1 above the wafer 150 is 0.5 to 2 times the second gap G2 below the wafer 150. During the decompression transfer injection molding process, the molding temperature is controlled to be lower than the melting point of the bump 160, at least 10 degrees Celsius.
11846twf.ptd 第19頁 1234213 五、發明說明（13) 佳，成形溫度高過於此時，相對於成形時熔融狀態之封裝 材料對晶片1 5 0所產生之壓力，凸塊1 6 0對於晶片1 5 0與載 板1 8 0覆晶接合強度不夠，容易在減壓移轉注模成形的過 程中發生晶片1 5 0脫落等現象。 而且，若晶片1 5 0上方之第一間隙G 1係小於晶片1 5 0下 方之第二間隙G 2之0 . 5倍，則熔融狀態之封裝材料會先行 填滿覆晶接合間隙，並阻塞頂部模封層遠離注膠管路3 5 0 之一側，使空氣殘留於晶片上方而來不及形成完整之頂部 模封層。若晶片1 5 0上方之第一間隙G 1係大於晶片1 5 0下方 之第二間隙G 2之2倍，則熔融狀態之封裝材料會先行進入 晶片1 5 0上方形成頂部模封層，並阻塞覆晶接合間隙遠離 注膠管路3 5 0之一側，使空氣殘留於覆晶接合間隙内而無 法以封裝材料完全填充於覆晶接合間隙内。不論是上述兩 種狀況其中之一發生，皆會影響晶片封裝結構之可靠度。 習知因錫鉛凸塊所產生的覆晶接合間隙為5 0〜9 0微 米，例如8 0微米的覆晶接合間隙時，頂部模封層之較佳厚 度為4 0〜1 6 0微米。若使用金凸塊，覆晶接合間隙一般為 1 0〜4 0微米，例如2 0微米的覆晶接合間隙時，頂部模封層 之較佳厚度以1 0〜4 0微米的數值最佳。 另外，根據本發明所提出之較佳實施例的晶片封裝製 程中，所使用之封裝材料之最大粒徑例如係小於覆晶接合 間隙之0 . 5倍。若所使用之封裝材料之最大粒徑大於覆晶 接合間隙之0 . 5倍時，覆晶接合間隙或頂部模封層的封裝 材料填充較為困難，甚至會造成填充不完全的情形。11846twf.ptd Page 19 1234213 V. Description of the invention (13) Good, the forming temperature is too high at this time, compared with the pressure generated by the packaging material in the molten state during forming on the wafer 1 50, the bump 1 6 0 for wafer 1 The bonding strength between the 50 and the carrier 180 is not sufficient, and the phenomenon of the wafer 150 falling off during the process of pressure reduction transfer injection molding is easy to occur. Moreover, if the first gap G1 above the wafer 150 is 0.5 times smaller than the second gap G2 below the wafer 150, the packaging material in the molten state will first fill the flip-chip bonding gap and block. The top mold layer is far away from one side of the injection pipe 3 50, so that air remains on the wafer and it is too late to form a complete top mold layer. If the first gap G 1 above the wafer 150 is twice as large as the second gap G 2 below the wafer 150, the molten packaging material will enter the wafer 150 above the top to form a top mold layer, and Blocking the flip-chip bonding gap away from one side of the glue injection pipe 3 50, leaving air in the flip-chip bonding gap and unable to completely fill the flip-chip bonding gap with the packaging material. Whether one of these two conditions occurs will affect the reliability of the chip package structure. It is known that the flip-chip bonding gap generated by the tin-lead bump is 50 to 90 micrometers. For example, when the flip-chip bonding gap of 80 micrometers is used, the preferred thickness of the top mold layer is 40 to 160 micrometers. If gold bumps are used, the flip-chip bonding gap is generally 10 to 40 micrometers. For example, when the flip-chip bonding gap is 20 micrometers, the preferred thickness of the top mold layer is the best value of 10 to 40 micrometers. In addition, in the chip packaging process according to the preferred embodiment of the present invention, the maximum particle diameter of the packaging material used is, for example, less than 0.5 times the flip-chip bonding gap. If the maximum particle size of the packaging material used is greater than 0.5 times the flip-chip bonding gap, it is difficult to fill the packaging material of the flip-chip bonding gap or the top mold layer, which may even cause incomplete filling.
11846twf.ptd 第20頁 1234213 五、發明說明（14) 若只為獲得薄型晶片封裝結構，如第2 A圖所示，只要 先形成頂部模封層，再削減頂部模封層之厚度即可。但若 是若要達到與本發明相同之4 0〜1 6 0微米的頂部模封層厚 度，一般的移轉注模成形法（非減壓）及一般的封裝材料 (最大粒徑7 0微米以上）則無法達成，且易造成填充不完 〇 本發明所提出之較佳實施例的晶片封裝製程係採用 2 0 0 1年日本專利J P 3 9 2 6 9 8所揭露之技術。但是，本發明針 對其封裝尺寸進行最佳化，以使晶片封裝結構具有最佳之 封裝可靠度。 以下將敘述本發明之實際應用例與對照例的實施條 件，以及所獲得之實施結果。 【實例1】將面積大小為8毫米X 8毫米，具1 2 0個共晶錫鉛 凸塊（熔點攝氏1 8 3度、間距為0 . 2 5毫米）、厚度0 . 3毫米之 晶片，以4 X 4的矩陣排列方式搭載於面積5 0毫米X 5 0毫 米、厚度0.2毫米的載板上，載板為FR-5材質。形成封裝 材料層後各切成1 0 . 5毫米X 1 0 . 5毫米的大小。晶片與載板 的覆晶接合間隙為7 0〜7 5微米，以4 5毫米X 4 5毫米X 0 . 5 毫米大小的成形模具進行注模，並以真空幫浦使空間呈現 減壓狀態，再以7 0 kg f /平方公分進行3分鐘的移轉注模成 形處理即可獲得第6 A圖，接著進行熱硬化處理（ρ 〇 s t c u r i n g )，以攝氏1 7 5度烘烤5小時。之後將矩陣狀排列的 載板進行切割，便能獲得第3圖已被覆加工的覆晶晶片型 晶片尺寸封裝（Chip Scale package, CSP)裝置。11846twf.ptd Page 20 1234213 V. Description of the invention (14) If only to obtain a thin chip package structure, as shown in Figure 2A, as long as the top mold layer is formed, then the thickness of the top mold layer can be reduced. However, if it is to achieve the same thickness of the top mold layer of 40 to 160 micrometers as the present invention, a general transfer injection molding method (non-decompression) and a general packaging material (with a maximum particle size of 70 micrometers or more) It cannot be achieved, and it is easy to cause incomplete filling. The chip packaging process of the preferred embodiment proposed by the present invention uses the technology disclosed in Japanese Patent JP 3 9 2 6 98 of 2001. However, the present invention optimizes the package size so that the chip package structure has the best package reliability. The implementation conditions of the practical application examples and comparative examples of the present invention, and the implementation results obtained will be described below. [Example 1] A wafer having an area of 8 mm X 8 mm, with 120 eutectic tin-lead bumps (melting point of 18 3 degrees Celsius, pitch of 0.25 mm), and a thickness of 0.3 mm, It is mounted in a 4 x 4 matrix arrangement on a carrier board with an area of 50 mm x 50 mm and a thickness of 0.2 mm. The carrier board is made of FR-5. After forming the packaging material layer, cut each into a size of 10.5 mm X 10.5 mm. The chip-to-chip bonding gap between the wafer and the carrier board is 70 to 75 micrometers, and injection molding is performed using a forming mold having a size of 45 mm X 45 mm X 0.5 mm, and the space is decompressed with a vacuum pump. Then, a transfer injection molding process at 70 kg f / cm 2 for 3 minutes can be used to obtain the 6A diagram, followed by a heat curing process (ρ ostcuring), and baking at 175 ° C for 5 hours. Then, the carrier plates arranged in a matrix are cut to obtain a flip chip type chip scale package (CSP) device which has been processed as shown in FIG. 3.
11846twf.ptd 第21頁 1234213 五、發明說明（15) 移轉注模成形時之其他條件、材料特性如第8圖，裝置評 鑑結果如第9圖與第1 0圖所示。 【對照例1】使用與實例1相同之封裝基板、以一般商品化 之液態底部充填材料（u n d e r f i 1 1 )(松下電工（股）製 C V 5 1 8 3 F )進行覆晶接合間隙之填充。填充材料在一定的條 件下硬化後，使用與應用例1相同之模具製造如第2 A圖之 半導體裝置，其成形結果如第9圖與第1 0圖所示。 【對照例2】使用與實例1相同之封裝基板，除了沒有以真 空幫浦進行減壓處理之外其他均相同，所得晶片封裝結構 如第3圖，其結果如第9圖與第10圖所示。 【實例2】除將實例1的減壓程度變更成第8圖所示外，其 他均相同，所得晶片封裝結構為第3圖，其結果如第9圖與 第1 0圖所示。 【實例3】除將實例1的減壓程度變更成第8圖所示外，其 他均相同，所得晶片封裝結構為第3圖，其結果如第9圖與 第1 0圖所示。 【實例4】除將實例1的成形溫度變更成如第8圖所示外， 其他均相同，所得晶片封裝結構為第3圖，其結果如第9圖 與第1 0圖所示。 【實例5】除將實例1的成形溫度變更成如第8圖所示外， 其他均相同，所得晶片封裝結構為第3圖，其結果如第9圖 與第1 0圖所示。 【對照例3】除將實例1所使用之材料最大粒徑變更成如第 8圖所不外’其他均相同’所得晶片封裝結構為弟3圖’11846twf.ptd Page 21 1234213 V. Description of the invention (15) Other conditions and material characteristics during transfer injection molding are shown in Figure 8 and the results of device evaluation are shown in Figure 9 and Figure 10. [Comparative Example 1] The same package substrate as in Example 1 was used, and a general commercial liquid underfill material (u n d e r f i 1 1) (CV 5 1 8 3 F, manufactured by Matsushita Electric Works Co., Ltd.) was used to fill the flip-chip bonding gap. After the filling material is hardened under certain conditions, a semiconductor device as shown in FIG. 2A is manufactured using the same mold as in Application Example 1. The molding results are shown in FIGS. 9 and 10. [Comparative Example 2] The same package substrate as in Example 1 was used, except that no vacuum pump was used for decompression treatment. The obtained chip package structure is shown in Figure 3, and the results are shown in Figure 9 and Figure 10. Show. [Example 2] Except that the degree of decompression of Example 1 was changed to that shown in Fig. 8, everything else was the same. The obtained chip package structure was shown in Fig. 3. The results are shown in Fig. 9 and Fig. 10. [Example 3] Except that the degree of decompression of Example 1 was changed to that shown in Fig. 8, everything else was the same. The obtained chip package structure was shown in Fig. 3. The results are shown in Fig. 9 and Fig. 10. [Example 4] Except that the molding temperature of Example 1 was changed to that shown in FIG. 8, everything else was the same. The obtained chip package structure was shown in FIG. 3, and the results were shown in FIGS. 9 and 10. [Example 5] Except that the molding temperature of Example 1 was changed to that shown in FIG. 8, everything else was the same. The obtained chip package structure was shown in FIG. 3, and the results were shown in FIGS. 9 and 10. [Comparative Example 3] Except that the maximum particle size of the material used in Example 1 was changed to what is not shown in FIG. 8 ', the others are the same.
11846twf.ptd 第22頁 1234213 五、發明說明（16) 其結果如第9圖與第1 0圖所示。 【對照例4】除將實例1所使用之材料最大粒徑變更成如第 8圖所示外，其他均相同，所得晶片封裝結構為第3圖， 其結果如第9圖與第1 0圖所示。 【實例6】除將實例1的封裝厚度由0。5亳米變更成0 . 4 2毫 米外，其他均相同，所得晶片封裝結構為第3圖，其結果 如第9圖與第1 0圖所示。 40毫米 其結果如 65毫米 其結果如 【對照例5】除將實例1 ，6的封裝厚度變更成0 外，其他均相同，所得晶片封裝結構為第3圖 第9圖與第10圖所示。 【對照例6】除將實例1 ，6的封裝厚度變更成0 外，其他均相同，所得晶片封裝結構為第3圖： 第9圖與第1 0圖所示。 【實例7】將0 · 2 5毫米間距8 0 0個共晶錫鉛凸塊（熔點攝氏 1 8 3度）列狀排列形成的面積8毫米X 8毫米、厚度0 . 2毫米 的晶片，搭載於面積3 5毫米X 3 5毫米、厚度0 . 4毫米的載 板上，載板為F R - 5材質。晶片與載板的覆晶接合間隙為8 0 〜8 5微米，以2 7 X 2 7 X 0 . 4毫米空間大小的成形模具進行 注模，並在實例1相同的條件下進行處理，即可獲得具頂 部模封層之覆晶晶片型BGA，裝置評鑑之結果如第9圖與第 1 0圖所示。 綜上所述，根據本發明所提出之較佳實施例的晶片封 裝結構及其製程具有下列優點： (1 )晶片上方覆蓋有封裝材料層，可維持良好的標記11846twf.ptd Page 22 1234213 V. Description of the invention (16) The results are shown in Figure 9 and Figure 10. [Comparative Example 4] Except that the maximum particle size of the material used in Example 1 was changed to that shown in Fig. 8, everything else was the same. The obtained chip package structure was shown in Fig. 3, and the results are shown in Fig. 9 and Fig. 10 As shown. [Example 6] Except that the package thickness of Example 1 was changed from 0.5 mm to 0.42 mm, everything else was the same. The resulting chip package structure is shown in Figure 3, and the results are shown in Figures 9 and 10 As shown. The result of 40 mm is 65 mm, and the result is [Comparative Example 5] Except that the package thickness of Examples 1 and 6 is changed to 0, the others are the same. The obtained chip package structure is shown in Figs. 3, 9 and 10. . [Comparative Example 6] Except that the package thicknesses of Examples 1 and 6 were changed to 0, everything else was the same. The resulting chip package structure is shown in Figure 3: Figures 9 and 10. [Example 7] A wafer with an area of 8 mm X 8 mm and a thickness of 0.2 mm was formed by arranging 800 eutectic tin-lead bumps (melting point 183 degrees Celsius) at a pitch of 0.5 mm at a distance of 0.2 mm. On a carrier board with an area of 35 mm X 3.5 mm and a thickness of 0.4 mm, the carrier board is made of FR-5. The chip-to-chip bonding gap between the wafer and the carrier board is 80 to 85 micrometers, and injection molding is performed using a forming mold with a space size of 2 7 X 2 7 X 0.4 mm, and the processing is performed under the same conditions as in Example 1. A flip-chip wafer-type BGA with a top mold layer was obtained, and the results of the device evaluation are shown in FIG. 9 and FIG. 10. In summary, the chip packaging structure and the manufacturing process thereof according to the preferred embodiment of the present invention have the following advantages: (1) The chip is covered with a packaging material layer, which can maintain a good mark
11846twf.ptd 第23頁 1234213 五、發明說明（17) 效果，而不需擔心造成晶片之破壞，移動晶片封裝結構時 亦同。 (2 )滿足行動通信裝置所需之超薄尺寸。 (3 )封裝材料層不會有空洞形成，具有極佳封裝可靠 度。 (4 )縮短封裝所需時間，進而提高封裝產能。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍内，當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。11846twf.ptd Page 23 1234213 V. Description of the invention (17) The effect without worrying about the damage to the chip, and the same is true when moving the chip package structure. (2) Meet the ultra-thin size required for mobile communication devices. (3) There will be no void formation in the packaging material layer, which has excellent packaging reliability. (4) The time required for packaging is shortened, thereby increasing the packaging capacity. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application.
11846twf.ptd 第24頁 1234213 圖式簡單說明 第1圖繪示為習知採覆晶接合技術的晶片封裝結構之 剖面圖。 第2 A圖與第2 B圖繪示為另一種習知採覆晶接合技術的 晶片封裝結構之剖面圖。 第3圖繪示為根據本發明所提出之第一較佳實施例的 晶片封裝結構之剖面圖。 第4圖與第5圖繪示為根據本發明所提出之第二較佳實 施例的晶片封裝結構之剖面圖。 第6 A圖繪示為根據本發明所提出之較佳實施例的晶片 封裝製程之成品的剖面圖。 第6 B圖繪示為根據本發明所提出之較佳實施例的晶片 封裝製程之成品經切割後的剖面圖。 第7圖繪示為根據本發明所提出之較佳實施例的晶片 封裝結構於減壓移轉注模成形模具中形成封裝材料層的剖 面圖 。 第8圖繪示為移轉注模成形時之其他條件與材料特性 如〇 第9圖繪示為移轉注模成形後所得之頂部模封層厚度 (斷面切割之測定結果）。 第1 0圖繪示為移轉注模成形後所得之結果（含裝置性 能與信賴度）。 【圖式標示說明】 1 0 、1 2 、1 4 :晶片封裝結構 5 0 ·晶片11846twf.ptd Page 24 1234213 Brief Description of Drawings Figure 1 shows a cross-sectional view of a chip package structure using conventional flip-chip bonding technology. Figures 2A and 2B are cross-sectional views of another conventional chip packaging structure using flip-chip bonding technology. FIG. 3 is a cross-sectional view of a chip package structure according to a first preferred embodiment of the present invention. 4 and 5 are cross-sectional views of a chip package structure according to a second preferred embodiment of the present invention. FIG. 6A is a cross-sectional view of a finished product of a chip packaging process according to a preferred embodiment of the present invention. FIG. 6B is a cross-sectional view of a finished product of a chip packaging process according to a preferred embodiment of the present invention after cutting. FIG. 7 is a cross-sectional view of a chip packaging structure forming a packaging material layer in a decompression transfer injection molding mold according to a preferred embodiment of the present invention. Fig. 8 shows other conditions and material characteristics during transfer injection molding. Fig. 9 shows the thickness of the top molding layer (measurement result of cross-section cutting) obtained after transfer injection molding. Figure 10 shows the results (including device performance and reliability) obtained after transfer injection molding. [Schematic description] 1 0, 1 2 and 1 4: Chip package structure 5 0 · Wafer
11846twf.ptd 第25頁 1234213 圖式簡單說明 52 :主動表面 6 0 :凸塊 7 〇、7 4 :封裝材料層 72 頂 部模封層 80 載 板 90 焊 球 1 0 0、2 0 0 :晶片封裝結構 1 5 0 ·晶片 1 5 2 :主動表面 1 6 0、2 6 0 :凸塊 1 7 0、2 7 0 :封裝材料層 1 8 0、2 8 0 :載板 1 9 0、2 9 0 :焊球 1 9 5、2 9 5 :被動元件 2 5 0 a :第一晶片 2 5 0 b :第二晶片 2 5 0 c :第三晶片 252a :第一主動表面 25 2b :第二主動表面 25 2c :第三主動表面 2 5 4 b :導線 2 5 6 :覆晶接合間隙 2 6 0 a ··第一凸塊 260b :第二凸塊11846twf.ptd Page 25 1234213 Brief description of the diagram 52: Active surface 6 0: Bump 7 0, 7 4: Packaging material layer 72 Top mold layer 80 Carrier board 90 Solder ball 1 0 0, 2 0 0: Chip package Structure 15 0 · Wafer 1 5 2: Active surface 16 0, 2 6 0: Bump 1 7 0, 2 7 0: Encapsulation material layer 1 8 0, 2 8 0: Carrier board 1 9 0, 2 9 0 : Solder ball 1 9 5 and 2 9 5: passive element 2 5 0 a: first wafer 2 5 0 b: second wafer 2 5 0 c: third wafer 252 a: first active surface 25 2b: second active surface 25 2c: third active surface 2 5 4 b: wire 2 5 6: flip-chip bonding gap 2 6 0 a · first bump 260b: second bump
11846twf.ptd 第26頁 1234213 圖式簡單說明 T1 ： 第- -厚 度 T2 ： 第二 二厚 度 300 模 具 31 0 上 模具 320 下 模具 330 真 空橡膠 封環 340 模 具腔 350 注 膠管路 360 柱 塞 370 抽 真空管 路 P1 ·· 第- -路 徑 P2 ： 第二 二路 徑 G1 ： 第- -間 隙 G2 ： 第二 二間 隙 L :切割 線11846twf.ptd Page 26 1234213 Brief description of the drawing T1:--thickness T2: second thickness 300 mold 31 0 upper mold 320 lower mold 330 vacuum rubber seal ring 340 mold cavity 350 injection tube 360 plunger 370 vacuum tube Road P1 ··--Path P2: Second and Second Path G1:--Gap G2: Second and Second Gap L: Cutting Line
11846twf.ptd 第27頁11846twf.ptd Page 27
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Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/707,683 US7230331B2 (en) | 2003-04-22 | 2004-01-05 | Chip package structure and process for fabricating the same |
| US11/462,369 US20060261499A1 (en) | 2003-04-22 | 2006-08-04 | Chip package structure |
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| Application Number | Priority Date | Filing Date | Title |
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| JP2003117506A JP2004327554A (en) | 2003-04-22 | 2003-04-22 | Semiconductor device and its manufacturing process |
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| TW200423267A TW200423267A (en) | 2004-11-01 |
| TWI234213B true TWI234213B (en) | 2005-06-11 |
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| TW (1) | TWI234213B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7551455B2 (en) | 2006-05-04 | 2009-06-23 | Cyntec Co., Ltd. | Package structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006210566A (en) * | 2005-01-27 | 2006-08-10 | Akita Denshi Systems:Kk | Semiconductor device |
| JP5031403B2 (en) * | 2007-03-01 | 2012-09-19 | 京セラケミカル株式会社 | Epoxy resin composition for sealing, resin-encapsulated semiconductor device and manufacturing method thereof |
| JP6415822B2 (en) * | 2014-02-10 | 2018-10-31 | アサヒ・エンジニアリング株式会社 | Apparatus and method for resin molding |
| JP2022002260A (en) * | 2020-06-22 | 2022-01-06 | 株式会社村田製作所 | Surface-mounted passive component |
-
2003
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7551455B2 (en) | 2006-05-04 | 2009-06-23 | Cyntec Co., Ltd. | Package structure |
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| TW200423267A (en) | 2004-11-01 |
| JP2004327554A (en) | 2004-11-18 |
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