JP2001007238A - Method of packaging wafer-level integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of packaging a wafer-level integrated circuit device by which a package-type integrated device can be made smaller and thinner. SOLUTION: A wafer manufactured by a conventional wafer manufacturing process is used. The whole wafer is subjected to a BGA packaging process. A substrate made of one-phase resin material is bonded on each of upper and lower surfaces of a chip. After a package is completed, the wafer is diced to fabricate independent integrated circuits. An integrated circuit device is made smaller in volume and thinner without using an excess wafer manufacturing process for wafer-level packaging. In addition to this, since a CTE(coefficient of thermal expansion) value of the substrate of the resin material is made closer to that of a circuit board, a favorable buffer effect and an effect of reducing thermal stress concentration can be obtained in an SMT process. Furthermore, since a substrate is bonded on each of the upper and lower sides of the chip, a warpage phenomenon due to a difference between a CET value of the substrate and that of the chip can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of packaging an integrated circuit device at a wafer level, and more particularly, to a method of packaging an integrated circuit device using a slightly traditional wafer process and BGA packaging technology. The present invention relates to a wafer level packaging method which does not require a completely extra special wafer process, and relates to a method for reducing the volume and thickness of a BGA package integrated circuit device.

[0002]

2. Description of the Related Art A package of a conventional integrated circuit device includes, for example, a BGA package in which a lead frame is used as an interface for connecting an IC chip and an external signal, and a solder bump is used as a transmission interface.

[0003] Both traditional lead frame packages and BGA packages have the disadvantage that their dimensions are relatively large, and the ratio of the package device width to the chip width (Package / Chip).
Ratioj) is at least 1.6 or more, creating a lot of space waste. Therefore, in the semiconductor industry at present, a so-called “chip-scale package (Chip Scale)” is used.
Le Package (CSP) "technology has been developed, which reduces the ratio of the width of the package device to the width of the chip in integrated circuit devices to 1.2.
More recently, a so-called "wafer level packaging" technology has been provided in which a certain company has integrated a packaging process into a wafer process. Please refer to FIGS. These figures show examples of integrated circuit devices 1 and 2 manufactured using a well-known wafer-level package technology. The size of the integrated circuit devices 1 and 2 is substantially the same as the size of the original chip, and the ratio of the width of the package device to the width of the chip (Package / Chip Ratio) is 1
, Significantly improving the problem of space waste in previous packaging technologies.

However, the wafer level package technology shown in FIGS. 1 and 2 has some disadvantages in practical operation. For example, FIG.
It is a product of IA, which has two metal layers 12 and 13 and two resin layers 14 and 15 formed on the working surface of the chip 11 of the integrated circuit device 1 in order, and the wiring on the chip 11 extends. And used to weld the solder bumps 16. The solder bumps 16 of the BGA package integrated circuit device 1 are welded on one circuit board (so-called SM).
At the time of the T step), the integrated circuit device 1 receives some high stress, high deformation, and high temperature. Traditional BGA packaged devices use the substrate as a buffer between the circuit board and the chip, thereby preventing chip damage. But,
The integrated circuit device 1 of the wafer level package shown in FIG. 1 has two metal layers 12 in order to avoid high stress and high deformation of the chip 11 in the process of welding the solder bumps 16 to the circuit board. 13 and two resin layers 14, 15
And a buffer layer between the chip 11 and the circuit board, but the coefficient of thermal expansion (Coefficent of Therma) of the buffer layer of the integrated circuit device 1 is increased.
l Expansion (CTE) is the CTE of the circuit board
Since the value is considerably different from the value, the phenomenon of damage to the chip 11 in the SMT process was unavoidable, and the yield of the product could not be improved.

FIG. 2 shows a wafer-level package integrated circuit device 2 sold by ShellCas, in which glass layers 22 and 23 are bonded with resin to both a working surface and a non-working surface of a chip 21. , And an aluminum pad 24 for transmitting an operation signal from the chip 21
(Al Pad) is stretched out of the glass layer 22, and the circuit layer 2 is formed of copper on the side surface of the solder bump 25 welded.
6 are formed and used for solder bump 25 welding. In the integrated circuit device 2 shown in FIG. 2, the chip 21 is protected by the glass layers 23 and 22 of which the upper and lower layers have relatively good strength, and can be formed by the difference in CTE value between the chip 21 and the resin layer. The phenomenon of edge warpage is prevented. However, this method does not use the circuit board and the glass layer 22 during the SMT process.
Not only cannot overcome the problem caused by the difference in CTE values of the above, but also this method requires that the aluminum pad 24 be stretched in advance on the dicing route of the chip 21 in the wafer process, and therefore the process is relatively complicated. there were.

In addition, the well-known wafer-level packaging technique shown in FIGS.
In addition, they had common significant drawbacks. That is, all of the well-known wafer-level packaging techniques are implemented during the wafer process, and all of the packages of the integrated circuit devices 1 and 2 are completed by an extra and special wafer process. It is much higher than packaged integrated circuit devices, and the technology of the wafer process is relatively higher.

[0007]

SUMMARY OF THE INVENTION Accordingly, it is a primary object of the present invention to provide a method of packaging a wafer-level integrated circuit device, and to provide a conventional wafer process and BG.
Using the A-package technology alone, the integrated circuit device package can be advanced to complete the wafer-level integrated circuit device package completely without the need for extra and special wafer processes, and The method of the present invention achieves a reduction in package volume and thickness, but is characterized by a relatively low number of required techniques. There is.

Another object of the present invention is to provide a method of packaging an integrated circuit device at a wafer level, in which a packaging process is performed on the whole wafer and an independent package device is formed by dicing. Thus, production efficiency can be increased and production time and costs can be reduced indirectly.

It is a further object of the present invention to provide a method of packaging a wafer-level integrated circuit device, wherein a non-conductive substrate made of a resin material is provided on both upper and lower surfaces of the chip. Not only avoids the problem that occurs during the SMT process when the CTE value and the circuit board come close to each other, but also because the non-conductive substrate is bonded to both the upper and lower sides of the chip, the CTE value of the non-conductive substrate and the chip Can be prevented from occurring due to the difference between the two.

[0010]

According to the first aspect of the present invention, there are provided the following steps a to d: a. Forming a plurality of independently viable circuit layout units on one semiconductor substrate; b. A single non-conductive substrate comprising a plurality of independently-existing metal circuit layers is coupled to the side of the semiconductor substrate having the circuit layout unit, and each metal circuit layer of the non-conductive substrate is connected to a respective one of the semiconductor substrates. Corresponding and associated with a circuit layout unit; c. Providing a plurality of metal balls on a surface of the non-conductive substrate remote from the semiconductor substrate and bonding to the metal circuit layer; d. A step of dicing the semiconductor substrate together with the non-conductive substrate to separate a plurality of circuit layout units into one unit to form an independent integrated circuit device; a wafer level integrated circuit comprising the above steps The device packaging method is used. In the invention according to claim 2, after the non-conductive substrate is coupled to the side of the semiconductor substrate provided with the circuit layout unit in the step b, the circuit layout unit of the semiconductor substrate is not further provided as a step b1. 2. The method as claimed in claim 1, further comprising the step of polishing the surface on the side to reduce the thickness of the semiconductor substrate. In the invention according to claim 3, after the non-conductive substrate is coupled to the side of the semiconductor substrate provided with the circuit layout unit in the step b, the circuit layout unit of the semiconductor substrate is not further provided as a step b2. Bonding another non-conductive substrate on the side surface;
According to a first aspect of the present invention, there is provided a method of packaging a wafer-level integrated circuit device. The invention according to claim 4, wherein a plurality of bonding pads are provided at predetermined positions of each circuit layout unit of the semiconductor base material according to the step a, and the bonding pads serve as electrical contacts for coupling the circuit layout unit to the outside world. An opening is provided in at least a position corresponding to the bonding pad of the non-conductive substrate described in step b, the bonding pad is not shielded by the non-conductive substrate, and further between step b and step c, as step b ′ Filling a position of each opening with an epoxy of a non-conductive resin to cover at least a portion near a portion where the metal circuit layer and the circuit layout unit are connected to each other. The above described method is a packaging method for a wafer-level integrated circuit device. The invention according to claim 5 is a method wherein the metal circuit layer is extended to the periphery of the opening, and the metal circuit layers of the non-conductive substrate in step b are respectively associated with the respective circuit layout units of the semiconductor base material and combined. 5. The method according to claim 4, wherein the metal circuit layer and the circuit layout unit of the semiconductor substrate are interconnected by connecting the metal circuit layer on the periphery of the opening to the corresponding bonding pad by wire bonding. And a packaging method for a wafer-level integrated circuit device. The invention of claim 6 provides the following a,
Steps b, b1, c, d, e, f, ie, a. A step of preparing a wafer, in which the wafer comprises a plurality of chip units, wherein each chip unit is provided with an integrated circuit layout, and a plurality of circuit layouts are provided at predetermined positions as electrical contacts for coupling with the outside world. B. Is provided. B. Bonding a first substrate to a surface on one side of the integrated circuit layout of the wafer, wherein a plurality of metal circuit layers and a plurality of apertures are provided on the first substrate;
The metal circuit layer is coupled to the circuit layout of the corresponding chip unit, and the position of the opening corresponds to the position of the bonding pad, and the bonding pad is not shielded by the non-conductive substrate. B1. Polishing the surface of the wafer not having the circuit layout unit to reduce the thickness of the chip; c. Separately bonding a second substrate to a surface of the wafer having no circuit layout; d. Injecting a non-conductive resin into the opening position of the first substrate; e. Bonding a plurality of metal balls to a surface of the first substrate remote from the chip, and bonding the metal balls to a metal circuit layer; f. Dicing the wafer integrally with the first substrate and the second substrate to separate a plurality of chip units into one to form an independent integrated circuit device; The circuit device is packaged.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of the method for packaging a wafer-level integrated circuit device according to the present invention includes the following steps. a. Forming a plurality of independently viable circuit layout units on a semiconductor substrate (ie, a chip); b. Bonding one first non-conductive substrate comprising a plurality of independently available metal circuit layers to a side of the chip comprising a circuit layout unit; b1. Polishing the surface of the chip not having the circuit layout unit to reduce the thickness of the chip; b2. Bonding a second non-conductive substrate to the surface of the chip on the side not having the circuit layout unit b3. Each metal circuit layer of the first non-conductive substrate is associated with and associated with each circuit layout unit of the semiconductor substrate; c. Providing a plurality of metal bumps on the surface of the non-conductive substrate on a side remote from the chip and bonding the metal bumps to the metal circuit layer; d. Dicing the chip with the non-conductive substrate to separate the plurality of circuit layout units one by one to form an independent integrated circuit device.

In the step of bonding the second non-conductive substrate to the surface of the chip b3 on the side not having the circuit layout unit, a known wire bonding step;
An automatic tape bonding process or a flip chip process of implanting an inner ball between a chip and a substrate can be adopted.

When bonding a chip to a substrate by a wire bonding process and a TAB (tape automatic bonding) process, a plurality of bonding pads are provided in advance at predetermined positions of each circuit layout unit of the chip to connect the circuit layout unit to the outside world. An opening is provided at a position corresponding to the bonding pad on the non-conductive substrate, which is required to form an electrical contact, and the bonding pad is exposed in the opening on the non-conductive substrate, thereby performing a wire bonding or TAB process. Need to be able to progress. In addition, it is possible to insert a molding process step b ′ between the step b and the step c. The non-conductive sealing resin (epoxy) is filled at the position of each opening to open the opening. Cover the holes.

[0014]

2 and 3 show a preferred embodiment of a method for packaging a wafer-level integrated circuit device according to the present invention.
This embodiment is a package method employing a well-known wire bonding process.

The method for packaging a wafer-level integrated circuit device according to the present invention includes the following steps: (1) Device preparation. A semiconductor substrate 31 (hereinafter, referred to as a wafer 31) manufactured by a traditional wafer process;
A non-conductive substrate 32 (hereinafter, referred to as a first substrate 32) is prepared. The working surface of the wafer 31 (Active Si
de) On the semiconductor process, a plurality of independent chip units (Chip) are formed. Each of the chip units includes a circuit layout unit (IC) that operates independently, and a plurality of bonding pads 33 are provided at predetermined positions on each of the independent circuit units to couple the circuit layout unit to the outside world. Electrical contact.
The first substrate 32 is made of a non-conductive resin material, and in this embodiment, the first substrate 32 is a conventional tape substrate. At least one side surface of the first substrate 32 is provided with a single or multiple metal circuit layers (not numbered) that can exist independently. The dimensions of the first substrate 32 correspond to the size of the corresponding chip 3.
The decabromodiphenyl oxide on each independent chip unit on chip 31 is
It substantially corresponds to the independent metal circuit layer of the substrate 32. An opening 34 is provided on the first substrate 32 at a position corresponding to the bonding pad 33, and the metal circuit layer is provided with the opening 3
4 is stretched to near the periphery. (2) Taping. As shown in FIG. 2A, the first substrate 32 is made of a non-conductive adhesive such as a well-known resin (epoxy) or a thermoplastic double-sided tape (Dual-Sid).
Using the ed Adhesive Tape, the chip 31 is adhered to the working surface of the chip 31, that is, the surface on the side of the circuit layout unit, and the bonding pads 33 of the wafer 31 are exposed in the openings 34, and the first substrate 32 is used. Do not block. At this time, if the first substrate 32 is bonded to the wafer 31 with a resin, the resin may be heated to such an extent that the first substrate 32 is fixedly coupled to the wafer 31 without completely heating and curing the resin for a while. (3) polishing. As shown in FIG.
The non-working surface, that is, the surface on the side where the first substrate 32 is not bonded, is polished by polishing equipment or other methods to reduce the thickness of the wafer 31. This step can reduce the overall thickness of the device after the package is completed. (4) Taping. As shown in FIG. 2C, the second substrate 35 is bonded to the non-operation surface of the wafer 31 with a resin. In the present embodiment, the second substrate 35 is basically made of the same material as the first substrate 32, and therefore has substantially the same coefficient of thermal expansion CTE as the first substrate 32. However, the second substrate 3
In No. 5, the production of the aforementioned metal circuit layer is omitted, and
The manufacturing cost of the substrate 35 has been reduced. At this time, if the second substrate 35 is bonded to the wafer with a resin, the first substrate 32 and the second substrate 35 are heated after the completion of this step to completely cure the bonding resin. (5) Wire bonding. As shown in FIG. 3A, the metal circuit layer around the opening 34 of the first substrate 32 is connected to the metal lead wire 36 (preferably a gold wire) on the wafer 3.
By welding to the corresponding bonding pads 33 on 1, each independent metal circuit layer of the first substrate 32 is associated with and connected to each circuit layout unit of the wafer 31. (6) Resin injection (Encapsulating). FIG.
As shown in FIG. 3B, a sealing resin 37 of a resin material is injected into the position of each opening 34. The sealing resin 37 covers at least the bonding pads 33, the metal lead wires 36, and both ends of the metal lead wires 36 and the vicinity of the joint between the wafer 31 and the first substrate 32. In a preferred embodiment, this resin infusion step is performed using the well-known technique of Glob Top. (7) Ball attachment. As shown in FIG. 4A, a plurality of metal balls 38 (preferably solder bumps) are joined to the surface of the first substrate 32 on the side remote from the wafer 31, and the metal balls 38 are connected to the metal circuit. Mutually bond with the layers. (8) Dicing. As shown in FIG. 4B, the wafer 31 is diced together with the first substrate 32 and the second substrate 35 to form a plurality of circuit layout units (chip units).
Are separated one by one to form an integrated circuit device that operates independently.

The metal circuit layer of the first substrate 32 may have a single-layer or multi-layer design. When the metal circuit layer of the first substrate 32 is multilayered, or when the metal circuit layer is not on the same side of the metal ball 38 and the first substrate 32, the metal circuit layer may be a conductive plug penetrating the plurality of first substrates 32. (Not shown) to be coupled to the metal ball 38. Since the technology of the conductive plug is a well-known technology in the industry, a detailed description is omitted.

In the method of packaging a wafer-level integrated circuit device according to the present invention, in addition to the above-described wire bonding process, the metal circuit layer of the substrate and the circuit layout unit of the wafer can be connected by a TAB process. When the TAB process is selected, first, the first substrate 32 in the above-mentioned step (1) is used as a TAB substrate, that is, the metal circuit layer on the TAB substrate is extended and extended to the inner peripheral edge of the opening 34. To form a plurality of inner lead (not shown) structures. In the taping process in step (2), T
Each inner lead of the AB substrate corresponds to the position of each bonding pad 33, and when the TAB substrate is bonded to the semiconductor base material (wafer 31) by pressurizing and heating, a portion of the opening 34 is formed by one pressing die. The inner leads are bonded to the corresponding bonding pads 33, thereby achieving the purpose of mutual connection between the metal circuit layer and the circuit layout unit of the semiconductor substrate, and thereby the aforementioned step (5).
Can be omitted, the process is simplified, and the same effect can be achieved. Since the TAB process is a well-known technique in the industry, a detailed description will be omitted.

According to another preferred embodiment of the method of packaging a wafer-level integrated circuit device of the present invention, an inner ball is provided between the wafer and the first substrate instead of the above-described known wire bonding or TAB process. 1st substrate 3 by a well-known flip chip process
The second metal circuit layer and the circuit layout unit of the wafer 31 are combined. In the flip chip process, a plurality of inner balls (not shown) are provided on a predetermined position of the first substrate 32 or on the bonding pads 33 of the wafer 31, and the above-mentioned inner balls are not necessarily provided on the first substrate 32. It is not necessary to provide the opening 34 described in step (1). The first substrate 32 is heated and pressurized and bonded onto the wafer 31, and at the same time, the inner balls are also welded between the metal circuit layer of the first substrate 32 and the circuit layout unit of the wafer 31. Since the flip chip process is also a well-known technique in the industry, a detailed description is omitted.

[0019]

The present invention has at least the following advantages over the prior art. (1) The integrated circuit device produced according to the present invention has a smaller size and a smaller thickness than a traditional lead frame or BGA device. The ratio (Pa) of the width of the package device to the width of the chip of the integrated circuit device according to the present invention.
Cage / Chip Ratio) is set to almost 1, and an effect similar to the well-known wafer-level packaging technology can be achieved. (2) The present invention adopts the wafer 31 manufactured by the traditional wafer process, and performs the BGA packaging process on the entire chip 31, thereby comparing with the known wafer level packaging technology. The technology is relatively easy and the packaging cost is relatively low. (3) The metal ball 38 of the present invention is the first substrate 3 made of a resin material.
2, which provide a good buffering effect during the SMT process (the buffering effect is the same as in known BGA devices),
Also, the CTE values of the first substrate 32 and the circuit board are relatively close,
Therefore, the phenomenon of concentration of thermal stress hardly occurs in the SMT process, and the reliability of the product can be improved. (4) In the present invention, one substrate 32, 35 is connected to each of two surfaces of the chip unit to form a geometric symmetry. The phenomenon of damage can be prevented. (5) According to the present invention, the package process is performed simultaneously on the entirety of one chip 31, and after the package is completed, the package is further diced to form an independent integrated circuit device. Such a "batch production (Batch Product)"
The method of “ion)” has higher production efficiency and lower production cost as compared with a method of packaging by a method of taping chips one by one in a known package technology. (6) During the process, the relatively large area and relatively hard wafer 31 provides one support function for the tape-type substrates 32 and 35, which is advantageous for the progress of the process and does not require an extra support plate structure. . Of course, the above is a description of a preferred embodiment of the present invention,
It does not limit the scope of the present invention. For example, the above embodiment illustrates a batch (batc) of an entire wafer.
h), the packaging process of the present invention is proceeding.
It can be implemented with half chips, quarter chips, or other relatively large chips composed of at least two chip units. In addition, the first substrate and the second substrate
In addition to the tape-type substrate, the substrate may be a traditional printed circuit board or an alternative thereto, which has good structural strength but is relatively thick. Therefore, any partial modifications made based on the content of the present invention and which do not violate the spirit of the present invention belong to the claims of the present invention. As described above, the present invention has both practicality and inventive step. Also, the present invention is not described in any publication distributed before the filing of the application, and therefore, the present invention
It has "practicality, novelty, and inventive step."

[Brief description of the drawings]

FIG. 1 is a structural schematic diagram of two types of well-known wafer-level integrated circuit devices produced by Sandia and ShellCase.

FIG. 2 is a diagram showing steps of a method for packaging a wafer-level integrated circuit device according to the present invention;

FIG. 3 is a diagram showing steps of a method for packaging a wafer-level integrated circuit device according to the present invention;

FIG. 4 is a diagram showing steps of a method of packaging a wafer-level integrated circuit device according to the present invention.

[Description of Signs] 1 Integrated circuit device 11 Chip 12, 13 Metal layer 14, 15 Resin layer 16 Solder bump 2 Integrated circuit device 21 Chip 22, 23 Glass layer 24 Aluminum pad 25 Solder bump 26 Circuit layer 31 Semiconductor substrate (wafer) ) 32 first substrate 33 bonding pad 34 opening 35 second substrate 36 metal lead 37 sealing resin 38 metal ball

Claims (6)

[Claims] 1. The following steps a to d: a. Forming a plurality of independently viable circuit layout units on one semiconductor substrate; b. A single non-conductive substrate comprising a plurality of independently-existing metal circuit layers is coupled to the side of the semiconductor substrate having the circuit layout unit, and each metal circuit layer of the non-conductive substrate is connected to a respective one of the semiconductor substrates. Corresponding and associated with a circuit layout unit; c. Providing a plurality of metal balls on a surface of the non-conductive substrate remote from the semiconductor substrate and bonding to the metal circuit layer; d. A step of dicing the semiconductor substrate together with the non-conductive substrate to separate a plurality of circuit layout units into one unit to form an independent integrated circuit device; a wafer level integrated circuit comprising the above steps How to package the device. 2. In the step b, after the non-conductive substrate is bonded to the side of the semiconductor substrate provided with the circuit layout unit, as a step b1, further, the side of the semiconductor substrate not having the circuit layout unit is provided. 2. The method according to claim 1, further comprising the step of polishing the surface to reduce the thickness of the semiconductor substrate. 3. In the step b), after the non-conductive substrate is bonded to the side of the semiconductor substrate having the circuit layout unit, the step b2 further includes the step of b2 on the side of the semiconductor substrate not having the circuit layout unit. 2. The method of claim 1, further comprising the step of bonding another non-conductive substrate on the surface. 4. A plurality of bonding pads are respectively provided at predetermined positions of each circuit layout unit of the semiconductor substrate according to the step a) to serve as electrical contacts for coupling the circuit layout unit to the outside world. An opening is provided in at least a position corresponding to the bonding pad of the non-conductive substrate described in b, the bonding pad is not shielded by the non-conductive substrate, and further between step b and step c, as step b ′, 2. The method according to claim 1, further comprising the step of: filling the openings with a non-conductive resin epoxy so as to cover at least a portion where the metal circuit layer and the circuit layout unit are connected to each other. A method of packaging a wafer-level integrated circuit device. 5. The method according to claim 1, wherein the metal circuit layer is extended to a periphery of the opening, and each metal circuit layer of the non-conductive substrate is associated with each circuit layout unit of the semiconductor substrate in step b. 5. The wafer according to claim 4, wherein the metal circuit layer and the circuit layout unit of the semiconductor substrate are interconnected by connecting the metal circuit layer around the opening to the corresponding bonding pad by wire bonding. -Level integrated circuit device packaging method. 6. The following steps a, b, b1, c, d, e, and f: a. A step of preparing a wafer, in which the wafer comprises a plurality of chip units, wherein each chip unit is provided with an integrated circuit layout, and a plurality of circuit layouts are provided at predetermined positions as electrical contacts for coupling with the outside world. B. Is provided. B. Bonding a first substrate to a surface on one side of the integrated circuit layout of the wafer, wherein a plurality of metal circuit layers and a plurality of apertures are provided on the first substrate;
The metal circuit layer is coupled to the circuit layout of the corresponding chip unit, and the position of the opening corresponds to the position of the bonding pad, and the bonding pad is not shielded by the non-conductive substrate. B1. Polishing the surface of the wafer not having the circuit layout unit to reduce the thickness of the chip; c. Separately bonding a second substrate to a surface of the wafer having no circuit layout; d. Injecting a non-conductive resin into the opening position of the first substrate; e. Bonding a plurality of metal balls to a surface of the first substrate remote from the chip, and bonding the metal balls to a metal circuit layer; f. Dicing the wafer integrally with the first substrate and the second substrate to separate a plurality of chip units into one to form an independent integrated circuit device; Circuit device packaging method.