TWI332694B - Chip package structure and process for fabricating the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device exhibiting high reliability, e.g. soldering resistance, and excellent heat dissipation properties. <P>SOLUTION: The semiconductor device is formed by face down mounting a semiconductor element 2 on an interposer 1 and flip-chip bonding the semiconductor element 2. A metal plate 4 having an area larger than that of the surface of the semiconductor element 2 on the side opposite to the flip-chip joint is bonded to that surface. A gap at the flip-chip joint of the semiconductor element 2, the surface of the semiconductor element 2 other than the flip-chip joint and the bonding face with the metal plate 4, and the entire surface of the metal plate 4 other than the bonding face with the semiconductor element 2 are sealed with sealing resin 3 of the same material. The semiconductor element 2 can be sealed with the sealing resin 3 having no interface. Heat generated from the semiconductor element 2 can be transmitted to the metal plate 4 and dissipated from the wide surface of the metal plate 4 through the sealing resin 3. <P>COPYRIGHT: (C)2005,JPO&amp;NCIPI

Description

1332694 V. Description of the Invention (1) Technical Field of the Invention The present invention relates to a chip package structure and a process thereof, and more particularly to a chip package structure having excellent heat dissipation and a process thereof . [Prior Art] In today's highly information society, the market for portable electric devices is rapidly expanding. The chip packaging technology also needs to be developed in line with the trend of digitalization, networking, regional connectivity and user-friendly use of electronic devices. In order to achieve the above requirements, it is necessary to strengthen the requirements for high-speed processing, multi-function, integration, small size, light weight, and low cost of electronic components. Therefore, the chip packaging technology is also becoming miniaturized and high. Density development. Among them, the Flip Chip bonding (F/C bonding) technology is bonded to the carrier by bumps, and the wiring is greatly shortened by the conventional wire bonding method (W ireb οnding). The length, which helps improve the signal transmission speed between the chip and the carrier, has gradually become the mainstream of high-density packaging. However, an important issue with high-density packaging technology is how to solve the heat dissipation problem of a chip package structure with high integration. Fig. 1 is a cross-sectional view showing a conventional wafer-bonded chip package structure. Referring to FIG. 1, the wafer 20 has an active surface 2 2 , and the active surface 22 is further provided with a plurality of pads (not shown). The wafer 20 is placed on the carrier 30 with the active surface 22 facing upward. A plurality of contacts (not shown) are disposed on the surface of the carrier 30. The two ends of the plurality of wires 24 are respectively connected to the pads of the wafer 20 and the contacts of the carrier 30 to be electrically connected to the wafer 20 and the carrier 30.

11843twf.ptd Page 8 1332694 V. Description of the Invention (2) Moreover, the surface of the carrier 30 away from the wafer 20 is further provided with a plurality of arrays of solder balls (So 1 der ba i 1 ) 3 2 , that is, wafers The package structure 10 is a Ball Grid Array Packaging (BGA packaging), so that the chip package structure can be electrically connected to a printed circuit board (PCB) (not shown). In addition, a layer of encapsulating material 34 is disposed on the carrier 30 and covers the wafer 20 and the wires 24 to provide protection. However, this chip package structure 10 has the disadvantage of poor heat dissipation. Figure 2 is a cross-sectional view showing a wafer package structure of a conventional flip chip bonding technique. Referring to Fig. 2, the wafer 50 has an active surface 52, and the main surface 52 is further provided with a plurality of pads (not shown). A plurality of contacts (not shown) are disposed on the surface of the carrier 60. The plurality of bumps 5 4 are disposed on the pads on the active surface 52, and the bumps 54 are electrically connected to the wafers 50 and the pads by the pads of the wafers 50 and the contacts of the carrier 60. Between boards 60. The carrier 60 is further disposed with a plurality of solder balls 6 2 arranged in an array away from the surface of the wafer 50. In order to protect the wafer 50 from moisture damage, the bumps 50 connecting the wafer 50 and the carrier 60 are protected from shear stress (Shear force), thereby forming a The encapsulation material layer 65 is between the wafer 50 and the carrier 60. Conventionally, the method of forming the encapsulating material layer 65 is to use a capillary phenomenon to fill a low-viscosity liquid encapsulating material into the flip-chip bonding gap between the wafer 50 and the carrier 60, and then harden the encapsulating material. As described above, the chip package structure 40 has better electrical performance than the conventional wire-bonded chip package structure 10 shown in Fig. 1, and the thickness also conforms to the trend of thinning of the chip package structure. However, the encapsulating material is filled with flip chip

11843twf.ptd Page 9 1332694 V. INSTRUCTIONS (3) The time required for the joint gap is long and does not meet the industry's requirements for production capacity. Moreover, since the package 'material is filled into the flip-chip bonding gap by natural capillary phenomenon, the number of the bumps 5 4 and the arrangement of the bump bonding gap between the wafer 50 and the carrier 60 will affect the package. The fluidity of the material causes the encapsulation material to be incompletely filled to form voids, which in turn affects the package reliability (R e 1 iabi 1 ity ). In addition, since the wafer 50 is directly exposed to the outside, it is easy to mark the wafer when it is on the surface of the wafer 50, or when the wafer 50 is vacuum-adsorbed to move the wafer package structure 40. This causes damage to the wafer 50. FIG. 3 is a cross-sectional view showing a wafer package structure of a conventional enhanced ball grid array package (TEBGA p a c k a g i n g ). Referring to Figure 3, the wafer 80 has an active surface 82, and the active surface 82 is further provided with a plurality of pads (not shown). A heat sink 8 5 is disposed on the back surface of the wafer 80 and the back surface of the carrier 90, and the heat sink 85 and the wafer 80 are adhered by a thermally conductive adhesive layer 87. A plurality of contacts (not shown) are disposed on the front surface of the carrier 90. The two ends of the plurality of wires 84 are respectively connected between the wafer 80 and the carrier 90, and the wires 84 are electrically connected to the wafer 80 by the pads of the wafer 80 and the contacts of the carrier 90. Between the carrier and the carrier 90. The front surface of the carrier 90 is further provided with a plurality of solder balls 9 2 arranged in an array, and the solder balls 92 are electrically connected to the wafer 80 by wires 84 connecting the contacts. In addition, the chip package structure 70 further includes a package material layer 9.5 covering the contacts of the wafer 80, the wires 84 and the carrier 90 to provide proper protection of these components. As described above, although the chip package structure 70 has better heat dissipation,

11843twf.ptd Page 10 1332694 V. INSTRUCTIONS (4) _ However, it requires a large area and therefore cannot meet the trend of high-density pins (H i gh d e n s i t y I / Ο ). Moreover, the assembly of the chip package structure 70 is also very complicated, and the relative capacity performance is not satisfactory. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a chip package structure and a process thereof for bonding a wafer using a flip chip bonding technique having excellent electrical properties in a chip package structure while providing an excellent chip package structure. Heat dissipation. Based on the above objects, the present invention provides a chip package structure mainly comprising a carrier, a wafer, a heat sink and a layer of packaging material. Wherein, the wafer has an active surface, and the active surface is provided with a plurality of bumps. The wafer is flip-chip bonded to the carrier with the active surface facing the carrier and electrically connected to the carrier. The heat sink is disposed on the wafer, and the area of the heat sink is larger than the area of the wafer. The encapsulating material layer is filled between the wafer and the carrier and on the carrier, and the encapsulating material layer is formed of a single encapsulating material. The surface of the heat sink away from the wafer is at least partially exposed to the outside world. Further, the encapsulating material layer has a thickness at a portion between the wafer and the carrier, and the maximum material particle diameter of the encapsulating material layer is, for example, less than 0.5 times the thickness. The wafer package structure of the present embodiment further includes, for example, a heat conducting adhesive layer. The thermally conductive adhesive layer is disposed between the wafer and the heat sink, for example. Based on the above objects, the present invention further provides a chip package structure, which is mainly composed of a carrier, a wafer set, a heat sink and a layer of packaging material. The chip set is disposed on the carrier and electrically connected to the carrier. crystal

11843twf.ptd Page 11 1332694 V. INSTRUCTIONS (5) _ The chip group is mainly composed of a plurality of wafers, and at least one of the wafers is flip-chip bonded to the carrier or the other wafer, and a flip chip bonding is maintained. gap. The heat sink is disposed on the wafer set, and the area of the heat sink is larger than the area of the chip set. The encapsulating material layer is filled in the flip-chip bonding gap and on the carrier, and the encapsulating material layer is formed by a single encapsulating material. The surface of the heat sink away from the chip set is at least partially exposed to the outside. Further, the portion of the encapsulating material layer located in the flip-chip bonding gap has a thickness, and the maximum material particle diameter of the encapsulating material layer is, for example, less than 0.5 times the thickness. The chip package structure of this embodiment further includes, for example, a thermally conductive adhesive layer. The thermally conductive adhesive layer is disposed, for example, between the wafer at the top of the wafer set and the heat sink. Further, the wafer set of this embodiment is mainly composed of, for example, a first wafer and a second wafer. The first wafer has a first active surface, and the first wafer is disposed on the carrier with the first active surface facing away from the carrier. The second wafer has a second active surface with a plurality of bumps disposed on the second active surface. The second wafer is flip-chip bonded to the first wafer with the second active surface facing the first wafer and electrically connected to the first wafer. The bumps maintain the flip-chip bonding gap. Further, the wafer set includes, for example, a plurality of wires. The two ends of each of the wires are electrically connected to the first wafer and the carrier, respectively. In addition, the chip set of this embodiment may also be mainly composed of a first wafer, a second wafer and a third wafer. The first wafer has a first active surface, and the first active surface is provided with a plurality of first bumps. The first wafer is flip-chip bonded to the carrier with the first active surface facing the carrier, and

11843twf.ptd Page 12 1332694 V. INSTRUCTIONS (6) Electrically connected to the carrier. The second wafer has a second active surface, and the second wafer is disposed on the first wafer with the second active surface facing away from the first wafer. The third wafer has a third active surface, and the third active surface is provided with a plurality of second bumps. The third wafer is flip-chip bonded to the second wafer with the third active surface facing the second wafer and electrically connected to the second wafer. The first bump and the second bump maintain a flip-chip bonding gap. Further, the wafer set includes, for example, a plurality of wires. The two ends of each of the wires are electrically connected to the second wafer and the carrier, respectively. In both embodiments of the above wafer package structure, the material of the encapsulating material layer is, for example, a resin. The material of the heat sink is, for example, a metal. The chip package structure further includes, for example, a plurality of arrays of solder balls and at least one passive component. Among them, the solder balls are disposed, for example, on the surface of the carrier on which the wafer is not disposed. The passive component is, for example, disposed on the carrier and electrically connected to the carrier. The carrier is, for example, a substrate or a lead frame. Based on the above object, the present invention further provides a chip packaging process, which mainly includes the following steps: (a) providing a carrier and a plurality of wafers, each of the wafers having an active surface, and at least one active surface is provided with a plurality of bumps . (b) electrically connecting the wafer to the carrier. (c) A heat sink is adhered to the back side of the wafer by a thermally conductive adhesive layer. (d) covering at least one of the buffered heat-resistant film on a part of the surface of the heat sink. (e) forming a layer of encapsulating material on the carrier and filling a layer of encapsulating material between the wafer and the carrier. Among them, the method of forming the encapsulating material layer is, for example, a reduced pressure transfer injection molding method. Forming the encapsulation material layer, for example, further includes cutting the carrier to form a plurality of wafer package structures. Moreover, the pressure reduction transfer injection molding

11843twf.ptd Page 13 1332694 V. INSTRUCTIONS (7) The pressure of the method is, for example, kept below 20 mm-Hg (m in - H g 〇r T 〇rr ), and the temperature is, for example, less than that of the bump The melting point is 10 degrees Celsius. The portion of the encapsulating material layer between the wafer and the carrier has a thickness, and the maximum particle size of the encapsulating material is, for example, less than one-half of the thickness. In summary, according to the chip package structure of the present invention, since a heat sink having a larger area than the wafer is disposed on the wafer, an excellent heat dissipation path of the chip package structure of the high-density pin can be provided, thereby improving the wafer. The operation speed and reliability of the package structure. Moreover, the chip packaging process proposed in accordance with the present invention also has the advantage of high throughput. The above and other objects, features, and advantages of the present invention will be apparent from [Embodiment] Figs. 4A to 4I are cross-sectional views showing various wafer package structures according to a first preferred embodiment of the present invention. Referring to Figures 4A to 4I, the wafer package structure 100 is mainly composed of a carrier 180, a wafer 150, a heat sink 140 and a package material layer 170. The carrier board 180 is, for example, a package substrate such as an organic substrate, a ceramic substrate, or a flexible substrate, or is, for example, a Flip Chip Quad Flat Non-leaded packaging (F/C QFN packaging). ) Lead frames used in packaging processes. The upper surface of the carrier plate 180 has, for example, a plurality of contacts (not shown). The wafer 150 has an active surface 152, and the wafer 150 is flip-chip bonded to the upper surface of the carrier 180 with the active surface 152 facing the carrier 180. crystal

11843twf.ptd Page 14 1332694 V. Description of the Invention (8) For example, a plurality of pads (not shown) are disposed on the active surface of the film 150, and a plurality of bumps 160 are disposed on the wafer 1 500. Active surface 1 5 2 on the pad. The wafer .1 0 is electrically connected to the carrier 110 by a bump 160 on the pad. That is, the wafer package structure 100 of the present embodiment includes at least one wafer 150, and the wafer 150 is bonded to the upper surface of the carrier 110 by a flip chip bonding technique. However, in addition to the wafer 150, the present embodiment can also be provided with other wafers or other components such as resistors, capacitors, and the like on the carrier 110 in the package structure 100. The heat sink 140 is disposed on the wafer 150, and the area of the heat sink 140 is larger than the area of the wafer 150, so that the heat dissipation efficiency is better. Moreover, the heat sink 140 is not limited to being integrally formed, and may be composed of a plurality of independent heat sinks. This design facilitates the flexible use of a large-area chip package structure. In addition, the encapsulating material layer 170 is filled between the wafer 150 and the carrier 180, and covers the carrier 180. Moreover, the encapsulating material layer 170 is formed of a single piece of material. The material of the encapsulating material layer 170 is, for example, a resin. The material of the heat sink 140 is, for example, a metal. In the present invention, the heat sink 160 of a metal material having a larger area than the wafer 150 is mainly used for diffusing the heat generated by the wafer 150, so that the thermal conductivity is preferably the best. Generally, for example, a copper plate, a name plate, an iron plate, a nickel plate or a surface mineralizer thereof is used. In addition, the fins 140 must be able to withstand the pressure at which the package process is formed, and therefore it is preferable to have a strength that is not easily bent. The thickness of the fins is preferably between 0.1 and 0. 6 mm. In addition, in order to increase the interface of the encapsulation material layer 170 and the heat sink

11843twf.ptd Page 15 1332694 V. The tightness of the invention (9), in addition to gold plating on the surface of the heat sink 140, for example, surface chemical treatment or surface on the surface of the heat sink 140 Physical processing such as roughening. In addition, in order to have a proper connection between the heat sink 1404 and the wafer 150, for example, a thermal adhesive layer 145 is disposed between the heat sink 1404 and the wafer 150 (eg, FIG. 4A). Shown in the enlarged section). Thermally Conductive Adhesive Layer 1 4 5 Generally, a material with good thermal conductivity such as silicone, silver paste or solder paste is used. In addition, the chip package structure 100 includes, for example, a plurality of solder balls 1 0 0 arranged in an array. The solder ball 190 is disposed, for example, on a contact of the lower surface of the carrier 110. Solder balls 190 provide the use of, for example, a printed circuit board after the chip package structure 100. In the chip package structure 100 shown in FIGS. 4A to 41, the chip package structure of FIGS. 4A to 4E, 4A to 4I is a single wafer 150 as an example, and 4F to 4 The chip package structure of FIG. 1 is taken as an example of two wafers 150. Of course, the number of wafers 150 is not limited thereto, and the number thereof may be more. The chip package structure of the 4th C, 4D, 4G and 4I diagrams has a package material layer 1 70 covering the periphery of the upper surface of the heat sink 1 40, and the remaining chip package structure 100 heat sink The upper surface of 140 is completely exposed to the outside world. The wafer package structure of the 4D and 4D drawings has a peripheral edge of the heat sink 1 4 0 which is processed and deformed. The chip package structure of FIG. 4 and FIG. 4 further includes at least one passive component 195. The passive component 195 is disposed, for example, on the upper surface of the carrier 110, and is electrically connected to the carrier 110. Sexual connection. The above various types of chip package structures 1 are all variations of the first preferred embodiment of the present invention, but still do not depart from the scope of the present invention. Figures 5 and 6 illustrate a second preferred embodiment in accordance with the present invention.

11843twf.ptd Page 16 1332694 V. DESCRIPTION OF THE INVENTION (ίο) A cross-sectional view of a wafer package structure of the embodiment. In the chip package structure according to the second preferred embodiment of the present invention, a plurality of wafers are mainly added, and the rest of the same as the first preferred embodiment will not be described herein. Referring to FIG. 5 and FIG. 6 together, the chip package structure 2000 is mainly composed of a carrier board 280, a chip set 250, a heat sink 240 and a package material layer 270. . The wafer set 250 is mainly composed of a plurality of wafers, and at least one of the wafers is bonded to the carrier 206 or other wafer by flip chip bonding. Therefore, at least one flip-chip bonding gap 2 5 6 exists in the wafer set 250, and the flip-chip bonding gap 256 is formed by bumps on the wafer which are flip-chip bonded. The heat sink 240 is disposed on the wafer set 250. The encapsulating material layer 270 is filled in the flip-chip bonding gap 256 and covers the carrier 280. The encapsulating material layer 270 is formed from a single encapsulating material. The surface of the heat sink 240 away from the chip set 250 is at least partially exposed to the outside. In addition, the portion of the encapsulating material layer 270 located in the flip-chip bonding gap 256 has a thickness, and the maximum material particle diameter of the encapsulating material layer 270 is, for example, less than 0.5 times the thickness. The wafer package structure 200 of the present embodiment further includes a thermally conductive adhesive layer 245. The thermally conductive adhesive layer 245 is disposed, for example, between the wafer at the top of the wafer group 250 and the heat sink 240. Thermally Conductive Adhesive Layer 2 4 5 Generally, a material with good thermal conductivity such as silicone rubber, silver paste or solder paste is used. Referring to FIG. 5, the wafer set 250 of the preferred embodiment is mainly composed of a first wafer 250a and a second wafer 250b, for example. The configuration relationship of each component is as follows. The first wafer 250a has a first active surface 252a, and the first wafer 250a is disposed on the carrier 280 with the first active surface 252b facing up. The second wafer 250b has a second active surface

11843twf.ptd Page 17 1332694 V. INSTRUCTION DESCRIPTION (11) 252b, a plurality of bumps 260 are disposed on the second active surface 252b. The second wafer 250b is flip-chip bonded to the first wafer 250a with the second active surface 252b facing the first wafer 250a, and is electrically connected to the first wafer 250a. The bumps 260 maintain the flip-chip bonding gap 256. In addition, the chip set 250 further includes, for example, a plurality of wires 2 5 4b. For example, a plurality of contacts (not shown) are disposed on the surface of the carrier 2 80, and a plurality of first active surfaces 252a of the first wafer 250a and the second active surface 252b of the second wafer 250b are disposed, for example. Solder pad (not shown). The bump 260 of the second wafer 2 0 0 b maintains the flip-chip bonding gap 256 between the first wafer 2 5 σ a and the second wafer 2 50 b. In other words, the second wafer 250b is bonded to the first active surface 2 5 2a of the first wafer 250 by a flip chip bonding technique. The two ends of each of the wires 2 5 4b are electrically connected to the pads of the first wafer 250 a and the contacts of the carrier 2 80, respectively. Referring to FIG. 6, the wafer set 250 of the preferred embodiment is formed, for example, by a first wafer 250a, a second wafer 250b, and a third wafer 250c. The wafer set 250 further includes, for example, a plurality of wires 2 5 4 b. Here, the arrangement relationship of each element is as follows. The first wafer 250 is disposed on the carrier 280, and the first wafer 250a has a first active surface 252a. The first active surface 252a is provided with a plurality of first bumps 260a. The first wafer 250a is flip-chip bonded to the carrier 280 with the first active surface 252a facing the carrier 280 and electrically connected to the carrier 280. The second wafer 250b has a second active surface 252b that faces away from the first wafer 250a. Moreover, the plurality of wires 2 5 4b are connected to the pads on the second active surface 25 2b of the second wafer 250b, and between the contacts of the carrier 202, to electrically connect the second crystal

11843twf.ptd Page 18 1332694 V. INSTRUCTIONS (12) Sheet 250b and carrier plate 280. The third wafer 250c has a third active surface 252c, and the third active 'surface 252c is provided with a plurality of second bumps 260b. The third wafer 250c is flip-chip bonded to the second wafer 250b with the third active surface 252c toward the second wafer 250b, and is electrically connected to the second wafer 250b. The first bump 2 60 a and the second bump 2 6 0 b maintain the flip-chip bonding gap 2 5 6 . In other words, the third wafer 250c is bonded to the second active surface 2 5 2 b of the second wafer 250b by flip chip bonding, and the first wafer 250 is bonded by the flip chip bonding technique. The surface of the plate 2 5 0 b. In the second preferred embodiment of the present invention, the number of wafers is increased as compared with the first preferred embodiment, and all wafers are not limited to being bonded to the carrier by flip chip bonding. The most important feature of the present invention is that at least one wafer is included in the wafer package structure, and the wafer is bonded to the carrier or other wafer by flip chip bonding. Moreover, a heat sink is further disposed above the wafer. The package material layer is provided on the carrier board and in the flip chip bonding gap, and the package material layer is formed at one time with the same package material. The heat sink is at least partially exposed to the outside of the surface of the wafer. Any implementation that conforms to the above-described main features should fall within the scope of the invention as claimed. The wafer packaging process of the preferred embodiment of the present invention will now be described, and an embodiment thereof will be described in detail. The chip packaging process mainly includes the following steps: (a) providing a carrier and a plurality of wafers, each having an active surface, and at least one active surface is provided with a plurality of bumps. (b) electrically connecting the wafer to the carrier. (d) A heat sink is adhered to the back side of the wafer by a thermally conductive adhesive layer. (e) covering at least one of the buffered heat-resistant film on a part of the surface of the heat sink. (f) forming a layer of encapsulating material on the carrier board

11843twf.ptd Page 19 1332694 V. INSTRUCTIONS (13) The layer of encapsulating material is filled between the wafer and the carrier. The wafer package structure obtained by completing this wafer 'packaging process has the following features. Figure 7A is a cross-sectional view of the finished product after completing the wafer packaging process in accordance with the wafer package structure of the preferred embodiment of the present invention. Figure 7B is a cross-sectional view of the finished wafer package structure after the wafer package process is completed, according to a preferred embodiment of the present invention. Referring to FIG. 7A and FIG. 7B together, in order to meet the requirements for mass production, the packaging process of the preferred embodiment is formed after the formation of the encapsulation material layer 170, for example, along the cutting line L (D ici ng ) to form a plurality of wafer package structures 100. Each of the chip package structures 100 includes at least one wafer 150. In addition, although the encapsulating material layer 170 shown in FIG. 7A is integrally connected, the process mold can be adjusted to form a plurality of mutually independent encapsulating material layers 170, that is, in the cutting line portion. The encapsulation material layer is not formed to shorten the time required for subsequent cutting. It is to be noted that in the process of the chip package structure according to the preferred embodiment of the present invention, the method of forming the encapsulation material layer is, for example, a reduced pressure transfer injection molding process. The reduced pressure transfer injection molding method refers to a treatment method in which a wafer structure to be packaged is placed in a mold, and after the mold is brought into a reduced pressure state, a hot melt material is introduced into the mold, and heat and pressure treatment is performed to harden the resin. In general, the injection molding method is not suitable for decompression, which may cause insufficient filling of the flip-chip bonding gap or between the wafer and the heat dissipation plate. If the decompression state in the mold is kept below 20 mm-Hg. A better encapsulation effect is obtained, and the optimum value of the reduced pressure state is below 10 mm-Hg.

11843twi.ptd Page 20 1332694 V. INSTRUCTION DESCRIPTION (14) FIG. 8 is a view showing a wafer package structure according to a preferred embodiment of the present invention formed in a decompression > multi-turn injection molding die. Sectional view. Referring to Fig. 8, the transfer molding apparatus (not shown) can place a suitable mold 300 according to the required package type, and the mold 300 is mainly composed of the upper mold 3 1 0 and the lower mold 3 2 0 Composition. When the upper mold 310 is clamped with the lower mold 3 20 , in order to achieve a more efficient vacuum effect, the mold clamping step firstly vacuums the upper mold 3 10 , the lower mold 3 2 0 and the mold 300 . The rubber seal ring 3 3 0 is in light contact. Next, a vacuum pump (not shown) is subjected to a vacuum reduction process in the mold cavity 340 via the evacuation line 307. Then, a tablet (not shown) is placed in the glue injection line 350 and maintained for 1 to 5 seconds to increase the degree of vacuum in the space, while raising the temperature in the mold to make the cake into a hot melt state. material. Finally, the upper mold 310 and the lower mold 3 2 0 are completely adhered together, and the plunger 360 is pulled up to introduce the encapsulating material in a hot melt state, so as to fill the mold cavity 340, and complete Transfer molding under reduced pressure. Wherein, during the pressure-reduction transfer molding, the forming temperature is controlled to be lower than the melting point of the bump 160 to at least 10 degrees Celsius, and the forming temperature is higher than the sealing material in the molten state at the time of molding. For the pressure generated by the wafer 150, the bump 160 is insufficient for the wafer bonding strength of the wafer 150 and the carrier 180, and it is easy to cause the wafer to fall off during the injection molding process under reduced pressure. phenomenon. In addition, in the wafer packaging process according to the preferred embodiment of the present invention, the heat sink 1 to be exposed to the outside after the wafer packaging process is completed must be covered by a buffer heat-resistant film 380. Package.

11843twf.ptd Page 21 1332694 V. Description of the invention (15) If the package is not covered with the buffered heat-resistant film 380, the heat sink 1 4 0 is exposed to the outside part and is prone to overflow (F 1 u sh ) . However, if the upper mold 3 10 is adjusted to prevent the occurrence of overflow, and the pressure is directly applied to the heat sink 1 400, the molding pressure at the time of packaging is also applied to the wafer 150 through the heat sink 1404. Damage to the wafer 1 500. Therefore, it is better to use the buffered heat-resistant film 380 as a buffer system on the heat sink 140. Buffering and 热 胜 片 380 380 material is commonly used in polyamide (Polyamide) or fluororesin materials, there is no special regulations. The buffer heat-resistant film 380 is generally used in a thickness of 2 5 to 7 5 μm, and the thickness can be obtained by the buffering effect of the present invention. In addition, the material of the buffer and the heat film 380 can also be made of rubber such as fluorinated rubber. Moreover, in the wafer package process according to the preferred embodiment of the present invention, the maximum particle size of the package material used is less than 5 times the flip chip bonding gap. If the maximum particle size of the encapsulating material used is greater than 0.5 times of the flip-chip bonding gap, it is difficult to fill the flip-chip bonding gap or the encapsulation material between the wafer and the heat dissipating plate, and even cause incomplete filling. Moreover, the surface of the wafer is damaged by the friction with the surface of the wafer when the package material is filled, and the reliability of the wafer is lowered. The implementation conditions of the practical application examples and the comparative examples of the present invention, and the obtained implementation results will be described below. [Example 1] A wafer having a size of 8 mm x 8 mm, having 800 eutectic tin-lead bumps (melting point of 183 ° C, pitch of 0.25 mm), thickness of 0.3 mm, Bonded in a matrix arrangement to an area of 3 5 mm × 3 5 mm, thickness

11843twf.ptd Page 22 1332694 V. INSTRUCTIONS (16) 0·4 mm carrier plate (F R - 5 ). In order to allow the current to pass uniformly, aluminum wiring is applied to the surface of the wafer. The flip-chip bonding gap is 5 0 to 7 5 μm. A 2 mm 2 x 2 2 mm thick copper plate having a thickness of 0.2 mm was adhered to the wafer using a commercially available thermal conductive adhesive. After nickel plating on the copper plate, a 20 mm 0PFA film (thickness 50 μm) sold on the market side was placed in the middle. Similarly, in order to improve the adhesion strength, the surface roughening treatment is applied below, and the pressure-reducing function of the tool is transferred to an injection molding apparatus for pressure-reduction transfer molding. The degree of decompression in space is approximately 1 mm-Hg. The package material used was Panasonic Electrician Co., Ltd. C V 8 7 0 0 F 2 (the maximum particle size of the filler was 21 μm, the average particle size was 5 μm, and the added materials were all 矽). The thickness of the upper mold space is 0.6 mm, and the encapsulation portion is formed by an area of 7 mm x 27 mm. Forming at 170 ° C, 70 kg / square centimeter pressure for 2 minutes, and then a 175 ° C, 4 hours post-hardening procedure can be obtained to form a wafer package structure as shown in Figure 4C. [Comparative Example 1] Using the wafer of the example 1 and the carrier sheet, the filling material (C V 5 1 8 3 F, manufactured by Matsushita Electric Works Co., Ltd.) was filled with a bottom portion which was generally sold, and the filling of the flip-chip bonding gap was carried out by a dispensing apparatus. After the encapsulating material is hardened under certain conditions, the resulting wafer package structure is shown in Fig. 2. [Comparative Example 2] The same wafer and carrier plate as in Example 1 were used except that the vacuum pump was not subjected to pressure reduction treatment, and the obtained wafer package structure was shown in Fig. 4C. [Example 2] The same procedure was repeated except that the degree of vacuum of Example 1 was changed to that shown in Fig. 9, and the obtained wafer package structure was shown in Fig. 4C. [Example 3] The wafer package structure obtained by changing the degree of vacuum of Example 1 to the one shown in Fig. 9 was the same.

11843twf.ptd Page 23 1332694 V 'Invention Description (17) [Example 4] Except that the molding temperature of Example 1 was changed to that shown in Fig. 9, the other wafer fabrication structures were the same. [Example 5] Except that the molding temperature of Example 1 was changed to that shown in Fig. 9, the others were all the same, and the obtained wafer package structure was the same. [Comparative Example 3] The same procedure was repeated except that the maximum particle diameter of the material used in Example 1 was changed as shown in Fig. 9, and the obtained wafer package structure was shown in Fig. 4C. [Comparative Example 4] The same procedure was repeated except that the maximum particle diameter of the material used in Example 1 was changed as shown in Fig. 9, and the obtained wafer package structure was shown in Fig. 4C. [Example 6] The same procedure was repeated except that the PF A film of Example 1 was changed to a polyimide film having a thickness of 50 μm, and the obtained wafer package structure was 4 C. [Example 7] Except that the heat sink material of Example 1 was changed to an aluminum plate, the others were all the same, and the obtained chip package structure was shown in Fig. 4C. [Example 8] In addition to changing the thickness of the PFA film of Example 1 to 30 μm and performing overall packaging (all of the surface of the wafer package structure and the entire mold is covered), the wafer package having the upper surface flat as shown in FIG. 4B can be obtained. structure. [Comparative Example 5] In Example 8, except that no film was used, the other was the same, and the obtained wafer package structure was shown in Fig. 4B. [Comparative Example 6] In Example 8, except that no film was used, and the package thickness was changed to 0.5 mm, the others were all the same, and the obtained chip package structure was 4B. The test conditions and test results of the wafer package structures of the above examples and comparative examples are shown in Fig. 9 and Fig. 10, respectively. The wafer packaging process of the preferred embodiment of the present invention is based on the technique disclosed in Japanese Patent JP 3 9 2 269. However, the present invention optimizes the package size and sets the heat sink to encapsulate the wafer.

11843twf.ptd Page 24 1332694 V. INSTRUCTIONS (18) The structure has the best package reliability and heat dissipation. In summary, the chip package structure according to the preferred embodiment of the present invention has a heat-dissipating chip package structure and the wafers are all coated with the same material at one time. Compared with the conventional chip package structure, the chip has a high reliability and has a high reliability. High heat dissipation. If a package material with a high thermal conductivity is used, the heat dissipation effect is better. Moreover, the chip package structure also has a simple structure and is suitable for mass production advantages. While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

11843twf.ptd Page 25 1332694 Brief Description of the Drawings Fig. 1 is a cross-sectional view showing a conventional wafer-bonded chip package structure. Figure 2 is a cross-sectional view showing a wafer package structure of a conventional flip chip bonding technique. Figure 3 is a cross-sectional view showing a wafer package structure of a conventional heat-enhanced ball grid array package. 4A to 4I are cross-sectional views showing various wafer package structures in accordance with a first preferred embodiment of the present invention. 5 and 6 are cross-sectional views showing a wafer package structure in accordance with a second preferred embodiment of the present invention. Figure 7A is a cross-sectional view of the finished product after completing the wafer packaging process in accordance with the wafer package structure of the preferred embodiment of the present invention. Figure 7B is a cross-sectional view of the finished wafer package structure after the wafer package process is completed, according to a preferred embodiment of the present invention. Figure 8 is a cross-sectional view showing the formation of a layer of encapsulating material in a reduced pressure transfer injection molding die in accordance with a preferred embodiment of the present invention. Fig. 9 is a view showing the conditions used in the transfer molding. Figure 10 shows the results obtained after transfer molding (including device performance and reliability). [Illustration Description] 1 0, 4 0, 7 0 : Chip package structure 20 ' 50 , 8 0 : Wafer

11843twf.ptd Page 26 1332694 Schematic description 22 &gt; 52 '82 Active surface 24, 84: Wire 30 &gt; 60 &gt; 90 Carrier 32 '62 ' 92 Solder ball 34 ' 65 ' 95 Package material layer 5 4 : bump 8 5 : heat sink 100 ' 200 chip package structure 140 ' 240 scatter sheet 145, 245 rail adhesive layer 150 : wafer 152 : main 1 surface 160 260 bump 170 ' 270 package material layer 180 , 280 Plate 190' 290 solder ball 195' 295 passive component 2 5 0 a first - wafer 2 5 0 b first - wafer 2 5 0 c first - wafer 2 5 2 a first active surface 2 52 b first - active surface 2 5 2 c No. - Active surface 2 54b wire

11843twf.ptd Page 27 1332694 Schematic description 2 5 6 : flip-chip bonding gap 2 6 0 a : first bump 2 6 0 b : second bump 300 : mold 3 1 0 : upper mold 3 2 0 : Lower mold 3 3 0 : Vacuum rubber seal ring 3 4 0 : mold cavity 3 5 0 : glue injection line 3 6 0 : plunger 3 7 0 : vacuum line 3 8 0 : buffer heat-resistant film L: cutting line

11843twf.ptd Page 28

Claims (1)

1332694 6. Patent application scope 1. A chip package structure comprising at least: a carrier plate; a wafer having an active surface, the active surface having a plurality of bumps disposed thereon, the wafer having the active surface facing the carrier plate The flip chip is bonded to the carrier and electrically connected to the carrier; a heat sink is disposed on the wafer, the area of the heat sink is larger than the area of the wafer, and a layer of packaging material is filled in the The encapsulation material layer is formed by a single encapsulation material between the wafer and the carrier, and the surface of the heat sink away from the wafer is at least partially exposed to the outside. 2. The chip package structure of claim 1, wherein the portion of the encapsulation material layer between the wafer and the carrier plate has a thickness, and the maximum material particle size of the encapsulation material layer is less than the thickness. 0.5 times. 3. The chip package structure of claim 1, further comprising a thermally conductive adhesive layer disposed between the wafer and the heat sink. 4. The wafer package structure of claim 1, wherein the material of the encapsulating material layer comprises a resin. 5. The chip package structure of claim 1, wherein the material of the heat sink comprises a metal. 6. The wafer package structure of claim 1, further comprising a plurality of arrays of solder balls arranged on the surface of the carrier away from the wafer. The wafer of claim 1 is as claimed in claim 1. Package structure, more package 11843twf.ptd Page 29 1332694 VI. The patent application scope includes at least one passive component disposed on the carrier board and electrically connected to the carrier board. 8. The chip package structure of claim 1, wherein the carrier board comprises one of a package substrate and a lead frame. A chip package structure comprising: at least one carrier; a chip set disposed on the carrier and electrically connected to the carrier, the chip set including a plurality of wafers, at least one of the wafers The crystal is bonded to one of the carrier and the one of the wafers, and maintains a flip-chip bonding gap; a heat sink is disposed on the wafer set, the area of the heat sink is larger than the area of the S-shaped chip group, and A layer of encapsulating material is filled in the flip-chip bonding gap and on the carrier, and the encapsulating material layer is formed of a single encapsulating material, wherein the surface of the heat sink away from the chip group is at least partially exposed to the outside. The wafer package structure of claim 9, wherein the portion of the encapsulating material layer located in the flip-chip bonding gap has a thickness, and the maximum material particle diameter of the encapsulating material layer is less than the thickness 〇· 5 times. 1. The wafer package structure of claim 9, further comprising a thermally conductive adhesive layer disposed between the top surface of the wafer set and the heat sink. 1. The wafer package structure of claim 9, wherein the wafer set comprises at least: a first wafer having a first active surface, and the first wafer system 11843twf.ptd page 30 1332694. The patent application scope is that the first active surface is disposed on the carrier plate facing away from the carrier board; and a second wafer has a second active surface on the second active surface. a plurality of bumps are disposed, the second wafer is flip-chip bonded to the first wafer with the second active surface facing the first wafer, and electrically connected to the first wafer, wherein the bumps are The flip chip bonding gap is maintained. The chip package structure of claim 12, wherein the chip set further comprises a plurality of wires, and the two ends of the wires are electrically connected to the first wafer and the carrier. The wafer package structure of claim 9, wherein the wafer set comprises at least: a first wafer having a first active surface, wherein the first active surface is provided with a plurality of first bumps The first wafer is flip-chip bonded to the carrier with the first active surface facing the carrier and electrically connected to the carrier; a second wafer has a second active surface, the second The wafer is disposed on the first wafer with the second active surface facing away from the first wafer; and a third wafer having a third active surface, wherein the third active surface is provided with a plurality of second bumps The third wafer is flip-chip bonded to the second wafer toward the second wafer, and is electrically connected to the second wafer, wherein the first bumps and the second wafers are electrically connected to the second wafer. The bump maintains the flip chip bonding gap. The chip package structure of claim 14, wherein the chip group further comprises a plurality of wires, and the two ends of the wires are respectively electrically 11843twf.ptd Page 31 1332694 VI. Patent Application Range Connected to the second wafer and the carrier. The chip package structure of claim 9, wherein the material of the encapsulating material layer comprises a resin. The wafer package structure of claim 9, wherein the material of the heat sink comprises a metal. The chip package structure of claim 9, further comprising a plurality of array-arranged solder balls disposed on the surface of the carrier away from the chip set. The chip package structure of claim 9, further comprising at least one passive component disposed on the carrier and electrically connected to the carrier. The wafer package structure of claim 9, wherein the carrier board comprises one of a package substrate and a lead frame. 2 1. The chip packaging process comprises at least the following steps: providing a carrier and a plurality of wafers, each of the wafers having an active surface, and at least one of the active surfaces is provided with a plurality of bumps; The wafers are electrically connected to the carrier, wherein the wafers face the carrier with the active surface; a heat sink is adhered to the back surface of the wafers by a thermally conductive adhesive layer; covering at least one buffer heat Film is on a portion of the surface of the heat sink; and a layer of encapsulating material is formed on the carrier, and the layer of encapsulating material is filled between the wafers and the carrier. 1 1843tvvf .ptd Page 32 1332694 VI. Scope of Application 2 2. The wafer packaging process described in claim 21, wherein the method of forming the encapsulating material layer comprises a reduced pressure transfer injection molding process. 2. The wafer packaging process of claim 2, wherein after forming the encapsulation material layer, further comprising cutting the carrier to form a plurality of wafer package structures. 2. The wafer packaging process of claim 2, wherein the pressure of the reduced pressure transfer injection molding method is maintained at 20 mm-Hg. 2. The wafer packaging process of claim 2, wherein the temperature of the reduced pressure injection molding process is at least 10 degrees Celsius lower than the melting point of the bump. 2. The wafer packaging process of claim 2, wherein the portion of the encapsulating material layer between the wafer and the carrier has a thickness, and the maximum material particle size of the encapsulating material layer is Less than 5 times the thickness. 11843twf.ptd Page 33