JP2004260138A - Semiconductor device and manufacturing method therefor - Google Patents

Semiconductor device and manufacturing method therefor Download PDF

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Publication number
JP2004260138A
JP2004260138A JP2003411921A JP2003411921A JP2004260138A JP 2004260138 A JP2004260138 A JP 2004260138A JP 2003411921 A JP2003411921 A JP 2003411921A JP 2003411921 A JP2003411921 A JP 2003411921A JP 2004260138 A JP2004260138 A JP 2004260138A
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Prior art keywords
resin
mounting substrate
semiconductor device
adhesive
semiconductor chip
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JP4390541B2 (en
JP2004260138A5 (en
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Koichi Honda
広一 本多
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NEC Electronics Corp
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NEC Electronics Corp
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Priority to JP2003411921A priority Critical patent/JP4390541B2/en
Priority to US10/763,554 priority patent/US7728440B2/en
Priority to TW093102258A priority patent/TWI243457B/en
Priority to KR1020040006563A priority patent/KR100549313B1/en
Publication of JP2004260138A publication Critical patent/JP2004260138A/en
Publication of JP2004260138A5 publication Critical patent/JP2004260138A5/ja
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Publication of JP4390541B2 publication Critical patent/JP4390541B2/en
Priority to US12/785,292 priority patent/US8324718B2/en
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device, in which a semiconductor chip is flip-chip connected to a mounting substrate, the amount of warpage of the mounting substrate is reduced, and there is no break of a solder bump, etc. connecting the semiconductor chip with the mounting substrate or cracks, etc. of the mounting substrate at a temperature cycle test. <P>SOLUTION: This device comprises a semiconductor chip 20, a mounting substrate 10 to which the chip is flip-chip-connected, a first filling part 40, containing an under fill part 40a and a fillet part 40b formed of a first resin, a reinforcement material 30, a first binding material 42, a lid part 31, and a second filling part 41 formed of a second resin whose coefficient of thermal expansion is smaller than that of the first resin. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

この発明は、有機系プリント配線基板と同様の製造方法で作られた搭載用基板に半導体チップをフリップチップ接続した例えばＢＧＡ（Ball Grid Array ）型のような半導体装置及びその製造方法に関する。   The present invention relates to a semiconductor device such as a BGA (Ball Grid Array) type in which a semiconductor chip is flip-chip connected to a mounting substrate manufactured by the same manufacturing method as an organic printed wiring board, and a method of manufacturing the same.

一般的に半導体チップをフリップチップ接続する搭載用基板は、有機系プリント配線基板と同様の製造方法で製作されたものである。搭載用基板は、配線層数が目的応じて二層から十数層で形成されている。しかし、十数層の配線層があるにも係わらず搭載用基板の厚さは０．５〜２．０ｍｍ程度であり、外力や異種材料間の熱膨張率の差による生じる応力に非常に弱く変形しやすい。搭載用基板の外形寸法は、この搭載用基板に搭載する半導体チップの大きさ、外部端子数、前記外部端子の配列、例えばフルグリッドか周辺グリッドかによって大きく異なる。一例をあげれば軽量薄型化の要求で半導体チップが約１７〜２０ｍｍ□、このチップのパッド電極数２０００〜３０００個、搭載用基板に設けなければならない外部端子数（バンプ）１８００〜２０００個の配列をフルグリッドにした場合、搭載用基板の外形は４５乃至５０ｍｍ□、厚さは１．０〜２．５ｍｍ程度である。   Generally, a mounting substrate for flip-chip connection of a semiconductor chip is manufactured by the same manufacturing method as an organic printed wiring board. The mounting substrate is formed with two to more than ten wiring layers depending on the purpose. However, despite the presence of more than a dozen wiring layers, the thickness of the mounting substrate is about 0.5 to 2.0 mm, and is extremely weak to stresses caused by external forces and differences in the coefficient of thermal expansion between different materials. Easy to deform. The external dimensions of the mounting board differ greatly depending on the size of the semiconductor chip mounted on the mounting board, the number of external terminals, and the arrangement of the external terminals, for example, a full grid or a peripheral grid. As an example, an array of semiconductor chips of about 17 to 20 mm square in order to reduce weight and thickness, the number of pad electrodes of this chip is 2000 to 3000, and the number of external terminals (bumps) 1800 to 2000 must be provided on a mounting substrate. Is a full grid, the outer shape of the mounting substrate is 45 to 50 mm square, and the thickness is about 1.0 to 2.5 mm.

最初に、従来の半導体装置について特許文献１と図１９を参照して説明する。図１９（ａ）は、例えば特許文献１に記載された従来の半導体装置２００で蓋部（「リッド」とも称される）２３１を取り外した状態の平面図であり、図１９（ｂ）は図１９（ａ）のＥ−Ｅ’線に沿った位置で蓋部２３１を取り付けた状態の断面図である。この半導体装置２００は、１ｍｍ程度の厚さの搭載用基板２１０に半導体チップ２２０がフリップチップ接続され、その隙間にアンダーフィル樹脂２４０を充填して硬化させてある。又、半導体チップ２２０の周辺を囲むように補強材（「スティフナ」とも称される）２３０が搭載用基板２１０に接着され、半導体チップ２２０の裏面と補強材２３０の端面に導電性接着材２４３によって蓋部２３１が固着されている。また、補強材２３０と半導体チップ２２０の側面の間は、空間２４７が形成されている。   First, a conventional semiconductor device will be described with reference to Patent Document 1 and FIG. FIG. 19A is a plan view of a conventional semiconductor device 200 described in Patent Literature 1, for example, with a lid (also referred to as a “lid”) 231 removed. FIG. It is sectional drawing of the state which attached the cover part 231 in the position along the EE 'line of 19 (a). In this semiconductor device 200, a semiconductor chip 220 is flip-chip connected to a mounting substrate 210 having a thickness of about 1 mm, and an underfill resin 240 is filled in the gap and cured. A reinforcing material (also referred to as a “stiffener”) 230 is adhered to the mounting substrate 210 so as to surround the periphery of the semiconductor chip 220, and a conductive adhesive 243 is attached to the back surface of the semiconductor chip 220 and the end surface of the reinforcing material 230. The lid 231 is fixed. A space 247 is formed between the reinforcing member 230 and the side surface of the semiconductor chip 220.

次に図２０（ａ）〜（ｄ）及び図２１（ａ）〜（ｃ）を参照して、従来の半導体装置２００の製造方法の概要を説明する。まず、上述した搭載用基板２１０と半導体チップ２２０と補強材２３０とアンダーフィル樹脂２４０とエポキシ樹脂接着材２４２と導電性接着材２４３と蓋部２３１を準備し、図２０（ａ）の配線基板図をスクリーン印刷機またはディスペンサのステージ（図示せず）にセットする。次いで搭載用基板２１０の周囲に熱膨張率が１６〜２２ｐｐｍのエポキシ樹脂接着材２４２をスクリーン印刷機又はディスペンサで塗布する。その後、補強材２３０を載置して所定の温度（１００℃〜１６０℃程度）でキュアする（図２０（ｂ））。次に、半導体チップ２２０のパッド２２１上に形成されたバンプ電極２２２と搭載用基板２１０のランド２１１をフリップチップマウンター（図示せず）により位置合わせした後、低融点合金、例えばＰｂフリー半田の場合は２５０℃前後の温度で溶融接続する（図２０（ｃ））。   Next, with reference to FIGS. 20A to 20D and FIGS. 21A to 21C, an outline of a conventional method of manufacturing the semiconductor device 200 will be described. First, the mounting substrate 210, the semiconductor chip 220, the reinforcing material 230, the underfill resin 240, the epoxy resin adhesive 242, the conductive adhesive 243, and the lid 231 described above are prepared, and the wiring board diagram of FIG. Is set on the stage (not shown) of the screen printer or dispenser. Next, an epoxy resin adhesive 242 having a coefficient of thermal expansion of 16 to 22 ppm is applied around the mounting substrate 210 using a screen printer or a dispenser. Thereafter, the reinforcing member 230 is placed and cured at a predetermined temperature (about 100 ° C. to 160 ° C.) (FIG. 20B). Next, after the bump electrodes 222 formed on the pads 221 of the semiconductor chip 220 and the lands 211 of the mounting substrate 210 are aligned by a flip chip mounter (not shown), a low melting point alloy, for example, a Pb-free solder is used. Is melt-connected at a temperature of about 250 ° C. (FIG. 20C).

また、別の方法では、半導体チップ２２０のパッド２２１と搭載用基板２１０のランド２１１の接続方法として接合面の材料がＡｕとＡｌ、ＡｕとＡｕから構成され加熱しながら超音波をかけて接続する方法がある。この場合は、 補強材２３０と搭載用基板２１０を接着するエポキシ樹脂接着材２４２の本キュアは別工程で本キュアする。次に、搭載用基板２１０と半導体チップ２２０の接着強度を確保するために熱膨張率が３２ｐｐｍ程度で流動性のあるアンダーフィル樹脂２４０をディスペンサ等で両者間の数１００μｍ程度の隙間に毛細管現象を利用して充填する。次にアンダーフィル樹脂２４０を１００℃程度の温度でキュアする（図２０（ｄ））。   In another method, as a method of connecting the pad 221 of the semiconductor chip 220 and the land 211 of the mounting substrate 210, the material of the bonding surface is made of Au and Al, or Au and Au, and the connection is made by applying ultrasonic waves while heating. There is a way. In this case, the main cure of the epoxy resin adhesive 242 for bonding the reinforcing member 230 and the mounting substrate 210 is performed in another step. Next, in order to secure the bonding strength between the mounting substrate 210 and the semiconductor chip 220, the underfill resin 240 which has a thermal expansion coefficient of about 32 ppm and has fluidity is drawn by a dispenser or the like into a gap of about several hundreds μm between them. Use and fill. Next, the underfill resin 240 is cured at a temperature of about 100 ° C. (FIG. 20D).

次いで、熱膨張率が１６〜２２ｐｐｍの導電性接着材２４３を補強材２３０の端面と半導体チップ２２０の裏面上に塗布または印刷方法で付着させる（図２１（ａ））。次に、蓋部２３１を補強材２３０に位置合わせして蓋部２３１を載置して荷重を掛け、更にこの状態で１５０〜１７０℃程度の温度でキュアして導電性接着材２４３を硬化させる（図２１（ｂ））。キュア方法は、オーブンでバッチ処理する方法、ベルト炉内に連続的に投入してキュアする一般的な方法がある。   Next, a conductive adhesive 243 having a coefficient of thermal expansion of 16 to 22 ppm is applied to the end surface of the reinforcing member 230 and the back surface of the semiconductor chip 220 by coating or printing (FIG. 21A). Next, the lid 231 is positioned with respect to the reinforcing material 230, the lid 231 is placed thereon, and a load is applied. In this state, the conductive adhesive 243 is cured by curing at a temperature of about 150 to 170 ° C. (FIG. 21 (b)). The curing method includes a batch method in an oven and a general method in which the mixture is continuously charged into a belt furnace and cured.

最後に、搭載用基板２１０のランド２１２に外部端子である半田バンプ２１３を一般的な方法で接着する（図２１（ｃ））。従来の半導体装置２００では、搭載用基板２１０のランド２１２に半田バンプ２１３が接着された直後の室温状態で既に、例えば図２２（ａ）に示すように、搭載用基板２１０の半導体チップ２２０との対向部が１００μｍ程度半導体チップ２２０側に引っ張られ、チップ搭載面側に凸の形状になっている。   Finally, solder bumps 213 as external terminals are bonded to the lands 212 of the mounting substrate 210 by a general method (FIG. 21C). In the conventional semiconductor device 200, at a room temperature immediately after the solder bumps 213 are bonded to the lands 212 of the mounting substrate 210, for example, as shown in FIG. The facing portion is pulled toward the semiconductor chip 220 by about 100 μm, and has a convex shape on the chip mounting surface side.

図２２（ａ）はこの半導体装置２００が２０℃の常温のときの搭載用基板２１０の基板反りの状態を模式的に示した図であり、図２２（ｂ）及び図２２（ｃ）はそれぞれ半導体装置２００が−４５℃の低温度のとき及び１５０℃の高温度のときの搭載用基板２１０の基板反りの状態を模式的に示した図である。従来の半導体装置２００では、図２２（ａ）のように、２０℃の常温状態で１００μｍ程度チップ側に凸の状態である。この状態から−４５℃に冷却すると、図２２（ｂ）のように反り量は１８０μｍまで増大する。常温に戻して次に１５０℃に加熱すると、図２２（ｃ）のように反り量は約５０μｍ迄減少する。従って、従来の半導体装置２００に対して、−４５℃の低温度状態と１５０℃の高温度状態との間の温度サイクルが数百回から千回程度繰り返されると、半導体チップ２２０のパッド２２１と搭載用基板２１０のランド２１１を接合するバンプ電極２２２にクラックが生じたり、各接合界面で剥離が生じる。   FIG. 22A is a diagram schematically showing the state of warpage of the mounting substrate 210 when the semiconductor device 200 is at a normal temperature of 20 ° C. FIGS. 22B and 22C respectively. FIG. 5 is a diagram schematically illustrating a state of the substrate warpage of the mounting substrate 210 when the semiconductor device 200 is at a low temperature of −45 ° C. and at a high temperature of 150 ° C. In the conventional semiconductor device 200, as shown in FIG. 22A, the semiconductor device 200 is in a state of projecting toward the chip side by about 100 μm at a normal temperature of 20 ° C. When cooling to −45 ° C. from this state, the warpage increases to 180 μm as shown in FIG. When the temperature is returned to normal temperature and then heated to 150 ° C., the warpage decreases to about 50 μm as shown in FIG. Therefore, when the temperature cycle between the low temperature state of −45 ° C. and the high temperature state of 150 ° C. is repeated about several hundreds to 1,000 times with respect to the conventional semiconductor device 200, the pad 221 of the semiconductor chip 220 becomes Cracks occur in the bump electrodes 222 that join the lands 211 of the mounting substrate 210, and peeling occurs at each joining interface.

温度サイクルで半田バンプにクラックが生じたり、パッドやランドとの接合界面で剥離が生じる理由は次のように推定される。図２３は、この理由を説明するためのバンプ電極２２２近傍の模式的な拡大図である。以下、図２２，２３を参照しながら説明する。アンダーフィル樹脂２４０を充填することで平面方向の応力を吸収しているが、アンダーフィル樹脂２４０の収縮によりバンプ電極２２２が半導体チップ２２０側に引っ張られると共に垂直方向の力が掛かる状態となる。この状態で温度サイクルを繰り返すと半導体チップ２２０を含めて搭載用基板２１０が、図２２（ａ）乃至図２２（ｃ）に示されるような凸形状と平坦形状を繰り返すことによってバンプ電極２２２のパッド２２１との接続部又は搭載用基板２１０のランド２１１との接続部に引っ張りと圧縮の応力が繰り返され、バンプ電極２２２にクラック２１７が生じたり、各接合界面で剥離２１８が生じ、破壊に至るものと推定される。   The reason why cracks occur in the solder bumps or peeling occurs at the bonding interface with the pads or lands in the temperature cycle is presumed as follows. FIG. 23 is a schematic enlarged view near the bump electrode 222 for explaining the reason. This will be described below with reference to FIGS. The filling of the underfill resin 240 absorbs the stress in the planar direction, but the shrinkage of the underfill resin 240 pulls the bump electrode 222 toward the semiconductor chip 220 and applies a vertical force. When the temperature cycle is repeated in this state, the mounting substrate 210 including the semiconductor chip 220 repeats a convex shape and a flat shape as shown in FIGS. In the connection portion with the 221 or the connection portion with the land 211 of the mounting substrate 210, the tensile and compressive stresses are repeated, cracks 217 occur on the bump electrodes 222, and peeling 218 occurs on each joint interface, leading to destruction. It is estimated to be.

上述した製造方法で製造された半導体装置２００は、０．５〜２．０ｍｍ厚の樹脂搭載用基板２１０の配線電極２１１に０．７ｍｍ厚の半導体チップ２２０のパッド２２１がバンプ電極２２２により接続され、接続部を補強するアンダーフィル樹脂２４０で固着されている。また、半導体チップ２２０を囲むように０．５〜１．０ｍｍ程度厚の補強材２３０を接着して樹脂搭載用基板２１０の平坦性と強度を確保した上で半導体チップ２２０を保護する０．５〜１．０ｍｍ厚の蓋部２４３が接着されて半導体装置２００が構成されている。   In the semiconductor device 200 manufactured by the above-described manufacturing method, a pad 221 of a 0.7 mm thick semiconductor chip 220 is connected to a wiring electrode 211 of a resin mounting substrate 210 having a thickness of 0.5 to 2.0 mm by a bump electrode 222. Are fixed with an underfill resin 240 that reinforces the connection portion. Further, a reinforcing material 230 having a thickness of about 0.5 to 1.0 mm is adhered so as to surround the semiconductor chip 220 to secure the flatness and strength of the resin mounting substrate 210 and to protect the semiconductor chip 220. A semiconductor device 200 is formed by bonding a lid portion 243 having a thickness of about 1.0 mm.

上記構成材料で製造された常温での半導体装置２００の搭載用基板２１０には図２２（ａ）のような基板の反りが生じている。この断面図は、図１９（ａ）のＤ−Ｄ‘線に沿った断面図である。半導体チップ２２０直下はアンダーフィル樹脂２４０の収縮により半導体チップ２２０側に引っ張られてチップ搭載面側に凸になった状態である。また補強材２３０の直下も、チップ搭載面側に少し凸の形状に変形している。すなわち２段形状に変形している。   The mounting substrate 210 of the semiconductor device 200 at room temperature manufactured from the above-described constituent materials is warped as shown in FIG. This cross-sectional view is a cross-sectional view along the line DD ′ in FIG. Immediately below the semiconductor chip 220 is a state where the underfill resin 240 is pulled toward the semiconductor chip 220 due to contraction of the underfill resin 240 and becomes convex toward the chip mounting surface. The portion directly below the reinforcing member 230 is also deformed into a slightly convex shape on the chip mounting surface side. That is, it is deformed into a two-stage shape.

アンダーフィル樹脂２４０の熱膨張率を１６〜２２ｐｐｍ程度に低くすれば、半導体チップ２２０直下の凸形状に引っ張られる現象はある程度抑制されるが、搭載用基板の反り量を大幅に低減させるのは難しい。また、アンダーフィル樹脂２４０の熱膨張率を低くするためには、通常シリカフィラー等を多量に配合するが、そうすると樹脂の粘度が上昇してしまう。この結果、搭載用基板２１０と半導体チップ２２０との対向領域のアンダーフィル樹脂２４０内にボイドを取り込み、剥離現象を発生させ易くなるため、熱膨張率を３２ｐｐｍ以下に下げることが困難であった。すなわち、アンダーフィル樹脂２４０の熱膨張率と粘度の関係は、熱膨張率を下げるためにはシリカ、アルミナのようなフィラーを多く混入すればよいが、これらのフィラーの混入量が多くなると粘度が上昇するというトレードオフの関係にある。   If the coefficient of thermal expansion of the underfill resin 240 is reduced to about 16 to 22 ppm, the phenomenon that the underfill resin 240 is pulled into a convex shape directly below the semiconductor chip 220 is suppressed to some extent, but it is difficult to greatly reduce the amount of warpage of the mounting substrate. . Further, in order to lower the coefficient of thermal expansion of the underfill resin 240, a large amount of a silica filler or the like is usually added, but this increases the viscosity of the resin. As a result, voids are taken into the underfill resin 240 in a region where the mounting substrate 210 and the semiconductor chip 220 are opposed to each other, and a peeling phenomenon is easily caused. Therefore, it has been difficult to reduce the coefficient of thermal expansion to 32 ppm or less. That is, the relationship between the coefficient of thermal expansion and the viscosity of the underfill resin 240 may be reduced by mixing a large amount of filler such as silica or alumina in order to reduce the coefficient of thermal expansion. There is a trade-off relationship of rising.

次に、特許文献２には、配線パターン面に半導体チップを接続しその隙間に第１の封止材（アンダーフィル樹脂）を６０〜１２０℃で進入させて、更に１４０〜１７０℃で硬化させた後に半導体チップの側面を第２の封止材（公知のフィレット材）により封止した構成の半導体装置が開示されている。この半導体装置では、半導体チップの直下に第１の封止材が存在し、半導体チップの側面に第２の封止材がフィレット状に形成されている。   Next, in Patent Document 2, a semiconductor chip is connected to a wiring pattern surface, a first sealing material (underfill resin) is introduced into the gap at 60 to 120 ° C., and further cured at 140 to 170 ° C. After that, a semiconductor device having a configuration in which the side surface of a semiconductor chip is sealed with a second sealing material (known fillet material) is disclosed. In this semiconductor device, a first encapsulant exists directly below a semiconductor chip, and a second encapsulant is formed in a fillet shape on a side surface of the semiconductor chip.

更に、特許文献３には、インターポーザ基板に半導体チップをフリップチップ接続し、インターポーザ基板と半導体チップ間と補強材に相当する部分をトランスファーモールドで一体的に充填してからヒートスプレッダ（蓋部に相当）を接着した構造の半導体装置が開示されている。   Further, in Patent Document 3, a semiconductor chip is flip-chip connected to an interposer substrate, a portion between the interposer substrate and the semiconductor chip and a portion corresponding to a reinforcing material are integrally filled by transfer molding, and then a heat spreader (corresponding to a lid portion). Has been disclosed.

特開２０００−３２３６２４号公報JP 2000-323624 A

特開２０００−２６０８２０号公報JP-A-2000-260820 特開２０００−３４９２０３号公報JP 2000-349203 A

上述した従来の半導体装置は、半導体チップを構成する例えばシリコンと有機系の樹脂基板からなる搭載用基板のように熱膨張率の異なる材料間を半田接続しているバンプが破壊されるのを防止するために、高熱膨張率，高弾性率のアンダーフィル樹脂を半導体チップと搭載用基板との間に充填することによって、両者の熱膨張率差による応力を緩和させていた。しかし、各材料の熱膨張率と弾性率が大きく異なることから製造工程が終了した時点で、半導体チップとアンダーフィル樹脂を介して対向している搭載用基板の対向領域は半導体チップ側に引っ張られる応力が発生して反った状態になっている。このため、反り量が大きくなると、当該半導体装置が実装される回路基板等に半田付け実装する際に反った部分の半田接続不良が発生し易くなるという問題が生じる。また、半導体装置自体に関しても、５℃〜３５℃程度の範囲の温度変動の小さい常温状態であれば問題がないが、温度サイクルのように低温、高温が繰り返されると搭載用基板の反りにより、半導体チップのパッドと搭載用基板のランドを接合する半田バンプにクラックが生じたり、各接合界面で剥離が生じたりするという問題があった。   The above-described conventional semiconductor device prevents the bumps connecting the materials having different coefficients of thermal expansion from being soldered, such as a mounting board made of silicon and an organic resin substrate, which constitutes a semiconductor chip, from being broken. In order to achieve this, an underfill resin having a high coefficient of thermal expansion and a high modulus of elasticity is filled between the semiconductor chip and the mounting substrate so as to reduce the stress caused by the difference in the coefficient of thermal expansion between the two. However, since the thermal expansion coefficient and the elastic modulus of each material are significantly different, when the manufacturing process is completed, the facing region of the mounting substrate facing the semiconductor chip via the underfill resin is pulled toward the semiconductor chip. It is in a warped state due to the occurrence of stress. For this reason, when the amount of warpage is large, there arises a problem that when soldering and mounting on a circuit board or the like on which the semiconductor device is mounted, defective solder connection at the warped portion is likely to occur. In addition, the semiconductor device itself has no problem if it is in a normal temperature state with a small temperature fluctuation in a range of about 5 ° C. to 35 ° C. However, when the low temperature and the high temperature are repeated as in a temperature cycle, the mounting substrate warps. There has been a problem that cracks occur in solder bumps joining the pads of the semiconductor chip and the lands of the mounting substrate, and peeling occurs at each joint interface.

また、例えば、半導体チップの直下に第１の封止材が存在し、側面に第２の封止材がフィレット状に形成された構造でも、半導体チップ直下の配線パターンの収縮を完全に防止することはできない。更に、トランスファーモールドでフィラー含有量の多い封止用樹脂をアンダーフィル樹脂としてインターポーザ基板と半導体チップ間に注入充填した構造の場合、樹脂の粘度が高いのでインターポーザ基板と半導体チップとの隙間にボイドを取り込み易くなり、剥がれやクラックの発生等の信頼性を損なう問題点を生じる。   Further, for example, even in a structure in which the first sealing material is present directly below the semiconductor chip and the second sealing material is formed in a side surface in a fillet shape, contraction of the wiring pattern immediately below the semiconductor chip is completely prevented. It is not possible. Furthermore, in the case of a structure in which a sealing resin having a high filler content is injected and filled between the interposer substrate and the semiconductor chip as an underfill resin by transfer molding, voids are formed in the gap between the interposer substrate and the semiconductor chip because the viscosity of the resin is high. It becomes easy to take in and there is a problem that reliability is impaired, such as peeling and cracking.

本発明の目的は、半導体チップと、この半導体チップが第１の面にフリップチップ接続された搭載用基板を備えた半導体装置であって、封止した後の状態で、搭載用基板の反り量が当該半導体装置を実装する回路基板等の実装用基板への半田付け実装において支障のない範囲内であり、且つ温度サイクル試験において半導体チップと搭載用基板との接続部である半田バンプ等におけるクラックや剥離等の発生による破壊がなく、搭載用基板にもクラック等の発生がない半導体装置を提供することにある。   An object of the present invention is a semiconductor device including a semiconductor chip and a mounting substrate in which the semiconductor chip is flip-chip connected to a first surface, and the amount of warpage of the mounting substrate in a state after sealing. Is within a range that does not hinder soldering to a mounting board such as a circuit board on which the semiconductor device is mounted, and cracks in solder bumps and the like that are connection portions between the semiconductor chip and the mounting board in a temperature cycle test. It is an object of the present invention to provide a semiconductor device which is free from destruction due to occurrence of peeling or peeling, and free from cracks or the like on a mounting substrate.

上記目的を達成するために、本発明の半導体装置は、半導体チップと、この半導体チップが第１の面にフリップチップ接続された搭載用基板と、前記半導体チップと前記搭載用基板との間に第１の樹脂が充填されたアンダーフィル部とこのアンダーフィル部から前記第１の樹脂が延在したフィレット部とを有する第１充填部と、前記半導体チップを囲む枠状の補強材と、この補強材の第１の端面を前記搭載用基板に接着する第１の接着材と、前記補強材で囲まれた領域を覆う蓋部と、この蓋部を前記半導体チップの裏面及び前記補強材の第１の端面と反対側の第２の端面に接着する第２の接着材と、前記半導体チップの側面，前記搭載用基板及び前記フィレット部で囲まれる空間に前記第１の樹脂と異なる第２の樹脂を充填して形成された第２充填部を備える。より具体的には、上記半導体装置は、一主面に複数の外部接続用電極（以下、チップ電極とする）を備えた半導体チップと、各チップ電極と対応する電極（以下、内部ランド電極とする）を第１の面に備えた搭載用基板を有し、互いに対応するチップ電極と内ランド電極を半田バンプ等の導電性電極（以下、接続部材とする）を介して対向させながら接続することで半導体チップが搭載用基板に搭載されている。また、半導体チップと搭載用基板との間に第１の樹脂が充填されたアンダーフィル部と半導体チップ領域からこの第１の樹脂が延在したフィレット部とを有する第１充填部と、半導体チップを囲む枠状の補強材と、この補強材の第１の端面を搭載用基板に接着する第１の接着材と、補強材で囲まれた領域を覆う蓋部と、この蓋部を半導体チップの裏面及び補強材の第１の端面と反対側の第２の端面に接着する第２の接着材と、半導体チップの側面，搭載用基板及びフィレット部で囲まれる空間に第２の樹脂を充填して形成された第２充填部も備えている。   In order to achieve the above object, a semiconductor device according to the present invention includes a semiconductor chip, a mounting substrate in which the semiconductor chip is flip-chip connected to a first surface, and a semiconductor chip mounted between the semiconductor chip and the mounting substrate. A first filling portion having an underfill portion filled with a first resin, a fillet portion extending from the underfill portion with the first resin, a frame-shaped reinforcing material surrounding the semiconductor chip, A first adhesive for bonding a first end surface of the reinforcing material to the mounting substrate; a lid covering an area surrounded by the reinforcing material; and a lid for covering the back surface of the semiconductor chip and the reinforcing material. A second adhesive that adheres to a second end surface opposite to the first end surface, and a second material different from the first resin in a space surrounded by the side surface of the semiconductor chip, the mounting substrate, and the fillet portion. No. formed by filling the resin Comprising a filling unit. More specifically, the semiconductor device includes a semiconductor chip having a plurality of external connection electrodes (hereinafter, referred to as chip electrodes) on one main surface, and an electrode corresponding to each chip electrode (hereinafter, an internal land electrode). Is mounted on the first surface, and the chip electrodes and the inner land electrodes corresponding to each other are connected while facing each other via conductive electrodes such as solder bumps (hereinafter referred to as connection members). Thus, the semiconductor chip is mounted on the mounting substrate. A first filling portion having an underfill portion filled with a first resin between the semiconductor chip and the mounting substrate, and a fillet portion extending from the semiconductor chip region with the first resin; , A first adhesive for bonding the first end surface of the reinforcing material to the mounting substrate, a lid covering an area surrounded by the reinforcing material, and a semiconductor chip A second adhesive is bonded to the back surface of the semiconductor chip and a second end face of the reinforcing member opposite to the first end face, and a space surrounded by the side surface of the semiconductor chip, the mounting substrate, and the fillet portion is filled with a second resin. Also provided is a second filling portion formed as described above.

また、本発明の半導体装置の製造方法は、搭載用基板に補強材を接着する工程と、搭載用基板に半導体チップを接続する工程と、第１の樹脂を充填・硬化する工程と、第２の樹脂を充填・硬化する工程と、蓋部を取り付ける工程と、半田バンプを接続する工程とを備え、少なくとも前記搭載用基板に補強材を接着する工程を第１番目の工程とし、前記搭載用基板に半導体チップを接続する工程を２番目の工程としたことを特徴とする。このとき、前記搭載用基板に補強材を接着する工程と、前記搭載用基板に半導体チップを接続する工程と、前記第１の樹脂を充填・硬化する工程と、前記第２の樹脂を充填・硬化する工程の各工程における樹脂の硬化は各樹脂を半硬化する処理であり、蓋部を取り付ける工程の硬化処理において全ての樹脂を本硬化するのが好ましい。   The method of manufacturing a semiconductor device according to the present invention includes a step of bonding a reinforcing material to the mounting substrate, a step of connecting a semiconductor chip to the mounting substrate, a step of filling and curing the first resin, and a step of: A step of filling and curing the resin, a step of attaching a lid part, and a step of connecting solder bumps, wherein at least a step of bonding a reinforcing material to the mounting substrate is a first step, The step of connecting the semiconductor chip to the substrate is a second step. At this time, a step of bonding a reinforcing material to the mounting substrate, a step of connecting a semiconductor chip to the mounting substrate, a step of filling and curing the first resin, and a step of filling and curing the second resin The curing of the resin in each step of the curing step is a process of semi-curing each resin, and it is preferable that all the resins are fully cured in the curing process of the step of attaching the lid.

また、本発明の半導体装置の他の製造方法は、搭載用基板に補強材を接着する工程と、搭載用基板に半導体チップを接続する工程と、第１の樹脂を充填・硬化する工程と、第２の樹脂を充填・硬化する工程と、蓋部を取り付ける工程と、半田バンプを接続する工程とを備え、前記第２の樹脂の充填・硬化する工程は蓋部を取り付ける工程の後に実施することを特徴とする。   Another method for manufacturing a semiconductor device of the present invention includes a step of bonding a reinforcing material to a mounting substrate, a step of connecting a semiconductor chip to the mounting substrate, and a step of filling and curing a first resin. The method includes a step of filling and curing the second resin, a step of attaching a lid, and a step of connecting a solder bump. The step of filling and curing the second resin is performed after the step of attaching the lid. It is characterized by the following.

上記構成の半導体装置において、第１の樹脂及び第２の樹脂は、第２の樹脂の熱膨張率が、第１の樹脂の熱膨張率よりも小さくなるように選択することで、熱硬化時や熱硬化後の温度変化による第１の樹脂の収縮・膨張応力を緩和することができる。従って、第１充填部のアンダーフィル部におけるボイドの発生を防止し接続部材の剥離，破壊を抑制するために、第１の樹脂として粘度は低いが熱膨張率がやや高い材料を用いても、搭載用基板の反りを抑制することができる。また、低温と高温を繰り返す温度サイクル試験においても第１の樹脂の収縮・膨張による応力が最小限に抑えられ、半田バンプ等の接続部材のクラック発生や剥離，破壊及びチップ電極や内部ランド電極の剥離を防止することができる。尚、第２の樹脂の熱膨張率は、搭載用基板の熱膨張率よりも小さくなっていればより好ましい。   In the semiconductor device having the above configuration, the first resin and the second resin are selected so that the coefficient of thermal expansion of the second resin is smaller than the coefficient of thermal expansion of the first resin. Or the shrinkage / expansion stress of the first resin due to a temperature change after heat curing. Therefore, in order to prevent the occurrence of voids in the underfill portion of the first filling portion and to prevent peeling and destruction of the connection member, even if a material having a low viscosity but a relatively high coefficient of thermal expansion is used as the first resin, Warpage of the mounting substrate can be suppressed. Also, in a temperature cycle test in which low and high temperatures are repeated, stress due to contraction and expansion of the first resin is minimized, and cracking, peeling, and destruction of connection members such as solder bumps and chip electrodes and internal land electrodes are prevented. Peeling can be prevented. It is more preferable that the coefficient of thermal expansion of the second resin is smaller than the coefficient of thermal expansion of the mounting substrate.

また、本発明の半導体装置の製造方法によれば、搭載用基板の強度を補強できるために製造工程中のハンドリング性を改善すると共に反りを抑えることができる。また、各接着材及び樹脂を各工程で仮キュアして半硬化状態にしておき最後に本キュアして完全硬化するために製造後の反りを最小に抑えることができる。   Further, according to the method of manufacturing a semiconductor device of the present invention, since the strength of the mounting substrate can be reinforced, the handling property during the manufacturing process can be improved and the warpage can be suppressed. In addition, since each adhesive and resin are temporarily cured in each step to be in a semi-cured state, and finally cured and completely cured, warpage after production can be minimized.

また、本発明の半導体装置の他の製造方法によれば、蓋部を取り付けてから第２の樹脂を注入・硬化させているので、第２の樹脂を完全に充填でき、蓋部近傍に空隙ができず搭載用基板の変形を抑制することができる。   According to another manufacturing method of the semiconductor device of the present invention, since the second resin is injected and cured after the lid is attached, the second resin can be completely filled, and the gap is formed near the lid. And deformation of the mounting substrate can be suppressed.

次に、本発明の実施形態について図面を参照して説明する。
図１は本発明の半導体装置の第１の実施形態を示す図で、（ａ）及び（ｂ）は、それぞれ蓋部を外した状態の平面図、及び（ａ）のＡ１−Ａ１’線に沿った位置で蓋部が取り付けられた状態の断面図である。図１（ａ），（ｂ）を参照すると、本実施形態の半導体装置１は、半導体チップ２０と、半導体チップ２０が第１の面にフリップチップ接続された搭載用基板１０と、半導体チップ２０と搭載用基板１０との対向領域の隙間に第１の樹脂が充填されたアンダーフィル部４０ａと半導体チップ２０と搭載用基板１０との対向領域から第１の樹脂が延在したフィレット部４０ｂとを有する第１充填部４０と、半導体チップ２０を囲む枠状の補強材３０と、この補強材３０の第１の端面を搭載用基板１０に接着する第１の接着材４２と、補強材３０及び補強材３０で囲まれた領域を覆う蓋部３１と、蓋部３１を半導体チップ２０の裏面及び補強材３１の第１の端面と反対側の第２の端面に接着する第２の接着材４３と、補強材３０，半導体チップ２０の側面，搭載用基板１０及び第１の樹脂からなるフィレット部４０ｂで囲まれる空間に第２の樹脂を充填して形成された第２充填部４１を備える。以下、具体的に説明する。 Next, an embodiment of the present invention will be described with reference to the drawings.
FIGS. 1A and 1B are views showing a first embodiment of a semiconductor device according to the present invention. FIGS. 1A and 1B are plan views of the semiconductor device with a lid removed, and FIG. It is sectional drawing of the state where the cover part was attached in the position along. Referring to FIGS. 1A and 1B, a semiconductor device 1 of the present embodiment includes a semiconductor chip 20, a mounting substrate 10 having the semiconductor chip 20 flip-chip connected to a first surface, and a semiconductor chip 20. An underfill portion 40a in which a gap between an opposing region of the semiconductor chip 20 and the mounting substrate 10 is filled with a first resin, and a fillet portion 40b in which the first resin extends from an opposing region of the semiconductor chip 20 and the mounting substrate 10. A first filling portion 40 having the following structure; a frame-shaped reinforcing member 30 surrounding the semiconductor chip 20; a first adhesive 42 for bonding the first end surface of the reinforcing member 30 to the mounting substrate 10; And a second adhesive that adheres the lid to the back surface of the semiconductor chip and to a second end surface of the reinforcement member opposite to the first end surface. 43, the reinforcing member 30, and the semiconductor chip 2 Comprising side, a second filling portion 41 formed by filling the second resin into a space surrounded by a fillet portion 40b made of the packaging board 10 and the first resin. This will be specifically described below.

半導体チップ２０は、主表面に外部接続用の複数のチップ電極２１を備えている。搭載用基板１０は、第１の面上にチップ電極２１と対応する位置に形成された内部ランド電極１１と、第１の面と反対側の第２の面上に形成された外部ランド電極１２と、互いに対応する内部ランド電極１１と外部ランド電極１２とを接続する基板内配線１５と、外部ランド電極１２に接着された例えば半田バンプ１３を備え、この半田バンプ１３は半導体装置１の外部端子となっている。   The semiconductor chip 20 has a plurality of chip electrodes 21 for external connection on the main surface. The mounting substrate 10 includes an internal land electrode 11 formed on the first surface at a position corresponding to the chip electrode 21 and an external land electrode 12 formed on the second surface opposite to the first surface. A wiring 15 for connecting the corresponding internal land electrode 11 and external land electrode 12 to each other; and, for example, a solder bump 13 bonded to the external land electrode 12. The solder bump 13 is connected to an external terminal of the semiconductor device 1. It has become.

搭載用基板１０と半導体チップ２０とは、互いに対応する内部ランド電極１１とチップ電極２１とが導電性材料で形成されたバンプ電極２２を介して接続されている。第１充填部４０を形成する第１の樹脂は、この接続部の応力を緩和させている。   The mounting substrate 10 and the semiconductor chip 20 are connected to each other via bump electrodes 22 made of a conductive material, and the corresponding internal land electrodes 11 and chip electrodes 21 are connected to each other. The first resin forming the first filling portion 40 relieves the stress at the connecting portion.

半導体チップ２０は、搭載用基板１０の中央部に搭載されており、補強材３０が半導体チップ２０の周囲を囲んで搭載用基板１０の第１の面の周縁部に第１の接着材４２により接着されている。この半導体装置１は、補強材３０により、製造工程中の熱的、機械的応力による搭載用基板１０の反りを低減させると共に強度を補強している。   The semiconductor chip 20 is mounted at the center of the mounting substrate 10, and the reinforcing member 30 surrounds the periphery of the semiconductor chip 20 and is attached to the periphery of the first surface of the mounting substrate 10 by the first adhesive 42. Glued. In the semiconductor device 1, the reinforcing member 30 reduces the warpage of the mounting substrate 10 due to thermal and mechanical stress during the manufacturing process and reinforces the strength.

また、搭載用基板１０，補強材３０の内壁，半導体チップ２０の側壁，蓋部３１及びフィレット部４０ｂで囲まれる空間に第２の樹脂を充填し、硬化させて第２充填部４１が形成され、ほぼ空間をなくすようにしている。この第２充填部４１を形成する第２の樹脂の熱膨張率、より具体的には線膨張率は、少なくとも第１の樹脂の熱膨張率よりも低くなっている。このように半導体装置１は、半導体チップ２０と補強材３０との間の空間に少なくとも第１の樹脂よりも低熱膨張率の第２の樹脂を充填・硬化した第２充填部４１が形成されているので、高温・低温時の第１の樹脂４０の膨張・収縮による搭載用基板１０の反りを抑制できる。尚、第２の樹脂の熱膨張率を、第１の接着材４２、第２の接着材４３、搭載用基板１０等の熱膨張率よりも低くすることにより、搭載用基板１０の反りを一層低減できる。   Further, the space surrounded by the mounting substrate 10, the inner wall of the reinforcing member 30, the side wall of the semiconductor chip 20, the lid 31, and the fillet 40b is filled with a second resin and cured to form a second filling portion 41. , Almost eliminating space. The coefficient of thermal expansion of the second resin forming the second filling portion 41, more specifically, the coefficient of linear expansion is lower than at least the coefficient of thermal expansion of the first resin. As described above, in the semiconductor device 1, the space between the semiconductor chip 20 and the reinforcing member 30 is formed with the second filling portion 41 in which at least the second resin having a lower coefficient of thermal expansion than the first resin is filled and cured. Therefore, warpage of the mounting substrate 10 due to expansion and contraction of the first resin 40 at high and low temperatures can be suppressed. The warp of the mounting substrate 10 is further reduced by making the thermal expansion coefficient of the second resin lower than that of the first adhesive 42, the second adhesive 43, the mounting substrate 10, and the like. Can be reduced.

ここで、第１充填部４０に用いた第１の樹脂、第２充填部４１に用いた第２の樹脂等の樹脂の特性の例を表−１に示す。

表−１ 各樹脂の特性
熱膨張率 （ppm） 弾性率 （GPa）
第１の接着材 １６〜２２ １１〜１２
第１の樹脂 ３０〜３２ ９〜１０
第２の樹脂 ８〜１６ １１〜２８
第２の接着材 ５０〜１００ ３〜９
Here, Table 1 shows examples of the characteristics of the resin such as the first resin used for the first filling unit 40 and the second resin used for the second filling unit 41.

Table 1 Properties of each resin
Coefficient of thermal expansion (ppm) Modulus of elasticity (GPa)
First adhesive 16-22 11-12
First resin 30-329 9-10
Second resin 8-16 11-28
Second adhesive 50-100 3-9

次に、図８（ａ）〜（ｅ）及び図９（ａ）〜（ｃ）を参照して、本実施形態の半導体装置１０の製造方法を工程順に沿って説明する。先ず、搭載用基板１０を準備する。搭載用基板１０の第１の面上には、搭載される半導体チップ２０のチップ電極２１と対応する位置に形成された内部ランド電極１１と、第１の面と反対側の第２の面上に形成された外部ランド電極１２とを備え、互いに対応する内部ランド電極１１と外部ランド電極１２が基板内配線１５により接続されている（図８（ａ））。   Next, with reference to FIGS. 8A to 8E and FIGS. 9A to 9C, a method of manufacturing the semiconductor device 10 of the present embodiment will be described in the order of steps. First, the mounting substrate 10 is prepared. On the first surface of the mounting substrate 10, an internal land electrode 11 formed at a position corresponding to the chip electrode 21 of the semiconductor chip 20 to be mounted, and on a second surface opposite to the first surface. The external land electrode 12 is formed on the internal land electrode 11 and the external land electrode 12 corresponding to each other are connected by the wiring 15 in the substrate (FIG. 8A).

次に、搭載用基板１０の周縁部に熱膨張率が１６〜２２ｐｐｍ程度、弾性率が１１〜１２ＧＰａの第１の接着材４２を、やはり予め準備してある枠状の補強材３０の形状と一致するように口字状に塗布した後、補強材３０を第１の接着材４２が塗布された部分に位置合わせして第１の端面が第１の接着材４２と接するように載置し、１２５℃程度で約１５分間仮キュアする（図８（ｂ））。この状態では、補強材３０は搭載用基板１０に接着されているが、第１の接着材４２は熱硬化反応して、ゲル化が進行し一部固体化しているが未だ完全には固化していない。尚、第１の接着材４２は、例えばエポキシ系樹脂、ポリオレフィン系樹脂、シリコン系樹脂、シアネートエステル系樹脂、ポリイミド系樹脂、ポリノルボルネン系樹脂を含む樹脂群の中から選択された樹脂材料を主成分として、熱膨張率と弾性率が所望の値になるように無機質フィラーを適量混入させて調整してある。また、補強材３０の材料は、Ｃｕ、ＳＵＳ（フェライト系ステンレス鋼）、アルミナ、シリコン、窒化アルミニウム、エポキシ樹脂等を含むグループの中から選択できる。   Next, a first adhesive 42 having a coefficient of thermal expansion of about 16 to 22 ppm and an elasticity of 11 to 12 GPa is provided on the peripheral portion of the mounting substrate 10 with the shape of the frame-shaped reinforcing material 30 which is also prepared in advance. After being applied in a bracket shape so as to coincide with each other, the reinforcing member 30 is aligned with the portion where the first adhesive 42 is applied, and placed so that the first end surface is in contact with the first adhesive 42. Temporarily cure at about 125 ° C. for about 15 minutes (FIG. 8B). In this state, the reinforcing material 30 is adhered to the mounting substrate 10, but the first adhesive material 42 undergoes a thermosetting reaction, and gelation proceeds to partially solidify, but is still completely solidified. Not. The first adhesive 42 mainly includes a resin material selected from a resin group including, for example, an epoxy resin, a polyolefin resin, a silicon resin, a cyanate ester resin, a polyimide resin, and a polynorbornene resin. As a component, an appropriate amount of an inorganic filler is mixed and adjusted so that the coefficient of thermal expansion and the modulus of elasticity become desired values. The material of the reinforcing member 30 can be selected from a group including Cu, SUS (ferritic stainless steel), alumina, silicon, aluminum nitride, epoxy resin, and the like.

次に、チップ電極２１上にバンプ電極２２が接着された半導体チップ２０を、各バンプ電極２２が対応する内部ランド電極１１と接するように位置決め載置して、例えば窒素雰囲気中で２５０℃に加熱して搭載用基板１０の内部ランド電極１１にフリップチップ接続する（図８（ｃ））。   Next, the semiconductor chip 20 having the bump electrodes 22 bonded to the chip electrodes 21 is positioned and mounted such that each bump electrode 22 is in contact with the corresponding internal land electrode 11, and heated to 250 ° C. in a nitrogen atmosphere, for example. Then, the chip is flip-chip connected to the internal land electrode 11 of the mounting substrate 10 (FIG. 8C).

次に、半導体チップ２０と搭載用基板１０との隙間にディイスペンサ等で第１の樹脂を滴下方法で注入・充填した後、１００℃程度で約１０分仮キュアし第１充填部４０を形成する（図８（ｄ））。この状態では第１の樹脂も熱硬化反応して、ゲル化が進行し一部固体化しているが未だ完全には固化していない。尚、第１の樹脂は、例えばエポキシ系樹脂を熱膨張率が３２ｐｐｍ程度、弾性率が９ＧＰａ程度になるように調整したものである。第１の樹脂がこの特性であれば、流動性が１０００〜４００００ＣＰＳ（centipoises ）でありアンダーフィル部４０ａにボイドを発生させることなく注入・充填できる。このとき、第１の樹脂により、半導体チップ２０と搭載用基板１０との隙間のアンダーフィル部４０ａと共にこのアンダーフィル部４０ａから半導体チップ２０の周囲に延びるフィレット部４０ｂも形成される。但し、フィレット部４０ｂは補強材３０まで達することはなく、この時点ではフィレット部４０ｂと補強材３０との間に搭載用基板１０の第１の面が露出している。   Next, the first resin is injected and filled into the gap between the semiconductor chip 20 and the mounting substrate 10 by a dispenser or the like by a dropping method, and then temporarily cured at about 100 ° C. for about 10 minutes to form the first filling section 40. (FIG. 8 (d)). In this state, the first resin also undergoes a thermosetting reaction, progresses gelation, and is partially solidified, but has not been completely solidified yet. The first resin is prepared, for example, by adjusting an epoxy resin to have a thermal expansion coefficient of about 32 ppm and an elastic modulus of about 9 GPa. If the first resin has this characteristic, the fluidity is 1000 to 40000 CPS (centipoises), and the resin can be injected and filled without generating voids in the underfill portion 40a. At this time, the first resin also forms an underfill portion 40a in a gap between the semiconductor chip 20 and the mounting substrate 10, and a fillet portion 40b extending from the underfill portion 40a to the periphery of the semiconductor chip 20. However, the fillet portion 40b does not reach the reinforcing material 30, and at this time, the first surface of the mounting substrate 10 is exposed between the fillet portion 40b and the reinforcing material 30.

次に、補強材３０の内壁，半導体チップ２０の側壁，搭載用基板１０の第１の面及びフィレット部４０ｂで囲まれた空間に第２の樹脂を充填後、約１５０℃で３０分程度仮キュアして第２充填部４１を形成する（図８（ｅ））。第２の樹脂についても、やはりこの状態では、熱硬化反応して、ゲル化が進行し一部固体化しているが未だ完全には固化していない。第２充填部４１を形成する第２の樹脂としては、第１の樹脂よりも熱膨張率が小さい、例えば熱膨張率が８〜１６ｐｐｍ程度で弾性率が１１〜２８ＧＰａのエポキシ系樹脂を用いることができる。尚、第２の樹脂の熱膨張率を搭載用基板１０の熱膨張率よりも小さくできればより好ましい。また、その充填方法としては、インジェクション注入、トランスファー封止、液状樹脂の滴下等の方法を用いることができる。   Next, after filling the second resin into the space surrounded by the inner wall of the reinforcing member 30, the side wall of the semiconductor chip 20, the first surface of the mounting substrate 10, and the fillet portion 40b, the space is temporarily set at about 150 ° C. for about 30 minutes. The second filling portion 41 is formed by curing (FIG. 8E). Also in this state, the second resin also undergoes a thermosetting reaction, and gelation proceeds to partially solidify, but has not yet completely solidified. As the second resin forming the second filling portion 41, an epoxy resin having a smaller coefficient of thermal expansion than the first resin, for example, having a coefficient of thermal expansion of about 8 to 16 ppm and an elastic modulus of 11 to 28 GPa is used. Can be. It is more preferable that the coefficient of thermal expansion of the second resin can be made smaller than the coefficient of thermal expansion of the mounting substrate 10. In addition, as a filling method, a method such as injection injection, transfer sealing, dropping of liquid resin, or the like can be used.

次に、半導体チップ２０の裏面及び補強材３０の第２の端面に第２の接着材４３を塗布した後（図９（ａ））、蓋部３１を補強材３０で囲まれた領域全体を覆うように載置し、更に蓋部３１の上に適切な荷重を載せて約１７５℃まで緩やかに昇温させた後、更に約１７５℃の状態を６０分程度維持して本キュアする（図９（ｂ））。これにより、第１充填部４０の第１の樹脂，第２充填部４１の第２の樹脂，第１の接着材４２及び第２の接着材４３が全て完全に硬化され、蓋部３１も完全に接着される。尚、第２の接着材４３としては、熱膨張率が５０〜１００ｐｐｍ程度の例えばエポキシ系樹脂を用いることができる。また、第２の接着材４３の場合は、無機質フィラーとしてＡｇ、Ｃｕ粉末等を適量混入しておけば第２の接着材４３の熱伝導性が向上し、より好ましい。   Next, after the second adhesive 43 is applied to the back surface of the semiconductor chip 20 and the second end surface of the reinforcing member 30 (FIG. 9A), the entire area surrounded by the reinforcing member 30 is covered with the lid 31. After placing it so as to cover it and further gently raising the temperature to about 175 ° C. by placing an appropriate load on the lid portion 31, the state is further maintained at about 175 ° C. for about 60 minutes to perform the main cure (FIG. 9 (b)). Thereby, the first resin of the first filling unit 40, the second resin of the second filling unit 41, the first adhesive 42 and the second adhesive 43 are all completely cured, and the lid 31 is also completely cured. Adhered to. As the second adhesive 43, for example, an epoxy resin having a coefficient of thermal expansion of about 50 to 100 ppm can be used. Further, in the case of the second adhesive 43, it is more preferable to mix an appropriate amount of Ag, Cu powder, or the like as an inorganic filler, because the thermal conductivity of the second adhesive 43 is improved.

次に、搭載用基板１０の外部ランド電極１２に外部端子である半田パンプ１３を一般的な方法で接着し、半導体装置１が完成する（図９（ｃ））。   Next, a solder pump 13 as an external terminal is bonded to the external land electrode 12 of the mounting substrate 10 by a general method, and the semiconductor device 1 is completed (FIG. 9C).

尚、上述した第１の樹脂，第２の樹脂，第１の接着材４２及び第２の接着材４３の主成分樹脂材料は、全て同じ例えばエポキシ系樹脂を用いることができ、それぞれに求められる熱膨張率等の特性に応じて、無機質フィラーの含有量を変えて最適な特性に調整して使用すればよい。   As the main resin materials of the first resin, the second resin, the first adhesive 42 and the second adhesive 43 described above, the same resin material, for example, epoxy resin can be used, and each is required. The content of the inorganic filler may be changed according to the properties such as the coefficient of thermal expansion to adjust the properties so as to be optimal.

また、蓋部３１の内壁と第２充填部４１との間にできる空隙４７は出来るだけ小さい方が望ましいが、第２充填部４１が半導体チップ２０の裏面の高さまで充填されていれば、その大きさは特に問題とならない。逆に、第２充填部４１の一部が蓋部３１の内壁と接していたり、空隙４７が消滅していても良い。   Further, it is desirable that the gap 47 formed between the inner wall of the lid portion 31 and the second filling portion 41 is as small as possible. However, if the second filling portion 41 is filled up to the height of the back surface of the semiconductor chip 20, the gap 47 is The size does not matter in particular. Conversely, a part of the second filling part 41 may be in contact with the inner wall of the lid part 31, or the void 47 may be eliminated.

次に、本発明の半導体装置の第２の実施形態について説明する。
図２は、本発明の半導体装置の第２の実施形態の断面図で、図１（ｂ）に相当する図である。図２を参照すると、本実施形態の半導体装置１ａの構成は半導体装置１の構成とほとんど同じであるが、唯一異なる点は搭載用基板１０へ補強材３０を接着する第１の接着材４２ａとして第２の樹脂を用いたことである。この半導体装置１ａにおいては、補強材３０を接着する第１の接着材４２ａに熱膨張率が８〜１６ｐｐｍ程度で弾性率が１１〜２８ＧＰａの第２の樹脂を用いることによって、半導体チップ２０直下の搭載用基板１０の収縮の程度をより緩和することができ、搭載用基板１０の反りを抑制できる。尚、本実施形態の半導体装置１ａの製造方法は、第１の接着材４０の代わりに第２の樹脂からなる第１の接着材４０ａを用いるだけで、他の工程は第１の実施形態の半導体装置１の製造方法と同じである。 Next, a second embodiment of the semiconductor device of the present invention will be described.
FIG. 2 is a sectional view of a second embodiment of the semiconductor device of the present invention, and is a view corresponding to FIG. Referring to FIG. 2, the configuration of the semiconductor device 1 a of the present embodiment is almost the same as the configuration of the semiconductor device 1, except that the configuration is different from that of the semiconductor device 1 a in that the reinforcing member 30 is bonded to the mounting substrate 10. That is, the second resin is used. In this semiconductor device 1a, the first resin 42a having a thermal expansion coefficient of about 8 to 16 ppm and an elastic modulus of 11 to 28 GPa is used for the first adhesive 42a for bonding the reinforcing member 30, so that the first resin 42a directly under the semiconductor chip 20 is used. The degree of shrinkage of the mounting substrate 10 can be further reduced, and the warpage of the mounting substrate 10 can be suppressed. The method of manufacturing the semiconductor device 1a according to the present embodiment uses only the first adhesive 40a made of a second resin instead of the first adhesive 40, and other steps are the same as those of the first embodiment. This is the same as the method of manufacturing the semiconductor device 1.

次に、本発明の半導体装置の第３の実施形態について説明する。
図３は、本発明の半導体装置の第３の実施形態を示す図で、（ａ）乃至（ｃ）はそれぞれ蓋部を外した状態の平面図、（ａ）のＡ２−Ａ２’線に沿った位置で蓋部が取り付けられた状態の断面図及び（ｂ）の補強材と搭載用基板との接着部の部分拡大断面図である。図３（ａ）乃至（ｃ）を参照すると、本実施形態の半導体装置１ｂは、半導体チップ２０と、半導体チップ２０が第１の面にフリップチップ接続された搭載用基板１０と、半導体チップ２０と搭載用基板１０との対向領域の隙間に第１の樹脂が充填されたアンダーフィル部４０ａと半導体チップ２０と搭載用基板１０との対向領域から第１の樹脂が延在したフィレット部４０ｂとを有する第１充填部４０と、半導体チップ２０を囲む枠状の補強材３２と、この補強材３２の第１の端面を搭載用基板１０に接着する第１の接着材４２と、補強材３２及び補強材３２で囲まれた領域を覆う蓋部３１と、蓋部３１を半導体チップ２０の裏面及び補強材３１の第１の端面と反対側の第２の端面に接着する第２の接着材４３と、補強材３２，半導体チップ２０の側面，搭載用基板１０及び第１充填部４０のフィレット部４０ｂで囲まれる空間に第２の樹脂を充填して形成した第２充填部４１を備える。第３の実施形態の半導体装置１ｂの構成は半導体装置１の構成とほとんど同じであるが、唯一異なる点は、補強材３２の第１の端面と搭載用基板１０との間の隙間が凹凸形状となっている点である。半導体装置１の補強材３０の第１の端面は、全面が平面となっているが、半導体装置１ｂの補強材３２の第１の端面の形状は、例えば渦巻状あるいは格子状の溝等により凸部５０と凹部が交互に形成された形状となっている。このとき、その溝または凹部の深さは、適宜設定できるが半導体チップ２０と搭載用基板１０との隙間であるが５０〜２００μｍ程度が好ましい。補強材３２の材料は、Ｃｕ、ＳＵＳ（フェライト系ステンレス鋼）、アルミナ、シリコン、窒化アルミニウム、エポキシ樹脂等を含むグループの中から選択できる。この補強材３２と搭載用基板１０の接着は第１の端面の凹部に第１の接着材４２を充填して接着している。尚、この場合も第１の接着材４２の代わりに第２の樹脂を第１の端面の凹部に充填して接着してもよい。 Next, a third embodiment of the semiconductor device of the present invention will be described.
FIGS. 3A to 3C are views showing a third embodiment of the semiconductor device of the present invention. FIGS. 3A to 3C are plan views of the semiconductor device with a lid removed, and are taken along line A2-A2 'in FIG. FIG. 4 is a cross-sectional view showing a state where a lid is attached at a position where the lid is attached, and a partially enlarged cross-sectional view of a bonding portion between a reinforcing material and a mounting substrate in FIG. Referring to FIGS. 3A to 3C, a semiconductor device 1b according to the present embodiment includes a semiconductor chip 20, a mounting substrate 10 in which the semiconductor chip 20 is flip-chip connected to a first surface, and a semiconductor chip 20. An underfill portion 40a in which a gap between an opposing region of the semiconductor chip 20 and the mounting substrate 10 is filled with a first resin, and a fillet portion 40b in which the first resin extends from an opposing region of the semiconductor chip 20 and the mounting substrate 10. , A frame-shaped reinforcing member 32 surrounding the semiconductor chip 20, a first adhesive 42 for bonding the first end face of the reinforcing member 32 to the mounting substrate 10, and a reinforcing member 32. And a second adhesive that adheres the lid to the back surface of the semiconductor chip and to a second end surface of the reinforcement member opposite to the first end surface. 43, reinforcing material 32, semiconductor chip 20 aspect, a second filling portion 41 formed by filling the second resin into a space surrounded by a fillet portion 40b of the mounting board 10 and the first filling portion 40. The configuration of the semiconductor device 1b according to the third embodiment is almost the same as the configuration of the semiconductor device 1, except that the gap between the first end surface of the reinforcing member 32 and the mounting substrate 10 has an uneven shape. It is a point that has become. The first end surface of the reinforcing member 30 of the semiconductor device 1 is entirely flat, but the shape of the first end surface of the reinforcing member 32 of the semiconductor device 1b is convex, for example, by a spiral or lattice-like groove. The shape is such that the portions 50 and the concave portions are alternately formed. At this time, the depth of the groove or the concave portion can be set as appropriate, and is a gap between the semiconductor chip 20 and the mounting substrate 10, but is preferably about 50 to 200 μm. The material of the reinforcing member 32 can be selected from a group including Cu, SUS (ferritic stainless steel), alumina, silicon, aluminum nitride, epoxy resin, and the like. The bonding between the reinforcing member 32 and the mounting substrate 10 is performed by filling a concave portion of the first end surface with a first adhesive 42. Note that, in this case as well, instead of the first adhesive 42, a second resin may be filled in the concave portion on the first end surface and bonded.

この半導体装置１ｂの構造による常温及び温度サイクルによる作用的特徴は、搭載用基板１０と補強材３２の接着状態を半導体チップ２０と搭載用基板１０との状態に近づけることによってまず補強材３２による搭載用基板１０の反りを抑制する。更に、半導体チップ２０が接続されている搭載用基板１０との間に第１の樹脂を充填して第１充填部４０が形成されると共に、半導体チップ２０の周囲の空間に第２の樹脂を空間全体が埋まるように充填し、硬化させて第２充填部４１が形成されている。この第２の樹脂を半導体チップ２０の側壁と補強材３２の内壁との間の空間に充填して第２充填部４１を形成することにより上下方向の動きを抑制する。また、補強材３２がシリコン、や銅などの材料からなるときは、第１の端面の凸部５０が接触する搭載用基板１０の領域に接続用電極を設けておくと共に第１の端面の凸部５０をメタライズしてからフラックスで活性化させ前述の接続用電極と半田付け接続する。この場合には、搭載用基板１０と補強材３２の接着状況が半導体チップ２０と搭載用基板１０の接着状況と同じ状態にすることができるので収縮による反りを抑えることができる。また、上記説明では補強材３２の第１の端面の形状を凹凸形状にした例を示したが、搭載用基板１０の補強材３２と接する領域に凸部５０としてギャップ部材となる例えば半田バンプ等の低融点金属部材を配置して凹凸形状を形成してもよい。   The functional characteristic of the structure of the semiconductor device 1b at room temperature and the temperature cycle is that the mounting state of the mounting substrate 10 and the reinforcing member 32 is made closer to the state of the semiconductor chip 20 and the mounting substrate 10 by mounting the reinforcing member 32 first. Warp of the substrate 10 is suppressed. Further, the first resin is filled between the mounting substrate 10 to which the semiconductor chip 20 is connected to form the first filling portion 40, and the second resin is filled in a space around the semiconductor chip 20. The second space 41 is formed by filling and curing the entire space. The second resin is filled in the space between the side wall of the semiconductor chip 20 and the inner wall of the reinforcing member 32 to form the second filling portion 41, thereby suppressing the vertical movement. When the reinforcing member 32 is made of a material such as silicon or copper, a connection electrode is provided in a region of the mounting substrate 10 in contact with the projection 50 of the first end face, and the projection of the first end face is provided. After the portion 50 is metallized, it is activated with a flux and soldered to the connection electrode. In this case, the state of adhesion between the mounting substrate 10 and the reinforcing material 32 can be made the same as the state of adhesion between the semiconductor chip 20 and the mounting substrate 10, so that warpage due to shrinkage can be suppressed. In the above description, an example in which the shape of the first end face of the reinforcing member 32 is made uneven is shown. However, a convex member 50 is formed as a gap member in a region of the mounting substrate 10 in contact with the reinforcing member 32, such as a solder bump or the like. The low-melting point metal member may be arranged to form an uneven shape.

次に、本発明の第４の実施形態について説明する。
図４は、本発明の半導体装置の第４の実施形態を示す断面図であり、第１の実施形態の図１（ｂ）に相当する図である。図４を参照すると、本実施形態の半導体装置１ｃは、補強材３３の開口部の形状が逆テーパ状に形成されている点が、第１の実施形態乃至第３の実施形態の各半導体装置１，１ａ，１ｂと異なるだけで、他の構成は半導体装置１，１ａ，１ｂと同じ構成であってよい。半導体装置１ｃでは、補強材３３の庇部分が第２の樹脂の上に覆い被さっているので、フィレット部４０ｂと第２充填部４１が蓋部３１側に変形するのを防止する効果がある。尚、第４の実施形態の半導体装置１ｃの製造方法は、第１の実施形態乃至第３の実施形態の各半導体装置の製造方法と同じであり、説明は省略する。 Next, a fourth embodiment of the present invention will be described.
FIG. 4 is a sectional view showing a fourth embodiment of the semiconductor device of the present invention, and is a view corresponding to FIG. 1B of the first embodiment. Referring to FIG. 4, the semiconductor device 1c of the present embodiment is different from the semiconductor devices of the first to third embodiments in that the opening of the reinforcing member 33 is formed in a reverse tapered shape. Other configurations may be the same as those of the semiconductor devices 1, 1a, and 1b, only different from the semiconductor devices 1, 1a, and 1b. In the semiconductor device 1c, since the eaves portion of the reinforcing member 33 covers the second resin, there is an effect of preventing the fillet portion 40b and the second filling portion 41 from being deformed toward the lid portion 31 side. The method for manufacturing the semiconductor device 1c according to the fourth embodiment is the same as the method for manufacturing each semiconductor device according to the first to third embodiments, and a description thereof will not be repeated.

次に、本発明の第５の実施形態について説明する。   Next, a fifth embodiment of the present invention will be described.

図５は、本発明の半導体装置の第５の実施形態を示す図で、（ａ）は蓋部を外した状態の平面図であり、（ｂ）及び（ｃ）はいずれも蓋部が取り付けられた状態でそれぞれ（ａ）のＢ−Ｂ’線に沿った位置での部分断面図及び（ａ）のＣ−Ｃ’線に沿った位置での断面図である。図５（ａ）乃至（ｃ）を参照すると、本実施形態の半導体装置１ｄは、半導体チップ２０と、半導体チップ２０が第１の面にフリップチップ接続された搭載用基板１０と、半導体チップ２０と搭載用基板１０との対向領域の隙間に第１の樹脂が充填されたアンダーフィル部４０ａと半導体チップ２０と搭載用基板１０との対向領域から第１の樹脂が延在したフィレット部４０ｂとを有する第１充填部４０と、半導体チップ２０を囲む枠状の補強材３４と、この補強材３４の第１の端面を搭載用基板１０に接着する第１の接着材４２と、補強材３４及び補強材３４で囲まれた領域を覆う蓋部３１と、蓋部３１を半導体チップ２０の裏面及び補強材３１の第１の端面と反対側の第２の端面に接着する第２の接着材４３と、補強材３４，半導体チップ２０の側面，搭載用基板１０及び第１充填部４０のフィレット部４０ｂで囲まれる空間に第２の樹脂を充填して形成された第２充填部４１を備える。第５の実施形態の半導体装置１ｄの構成は半導体装置１の構成とほとんど同じであるが、唯一異なる点は、補強材３４の４つのコーナー部の第１の端面側に溝部３４ａが形成されており、この溝部３４ａにも第２の樹脂が充填されている点である。矩形状の半導体装置においては、対角線の長さが最も大きいので膨張・収縮による影響が出やすい。半導体装置１ｄでは、上記構造により膨張・収縮による影響を抑制する効果が得られている。   FIGS. 5A and 5B are diagrams showing a fifth embodiment of the semiconductor device of the present invention, wherein FIG. 5A is a plan view showing a state in which a lid is removed, and FIGS. FIG. 4A is a partial cross-sectional view taken along a line BB ′ in FIG. 4A and a cross-sectional view taken along a line CC ′ in FIG. Referring to FIGS. 5A to 5C, a semiconductor device 1d according to the present embodiment includes a semiconductor chip 20, a mounting substrate 10 in which the semiconductor chip 20 is flip-chip connected to a first surface, and a semiconductor chip 20. An underfill portion 40a in which a gap between an opposing region of the semiconductor chip 20 and the mounting substrate 10 is filled with a first resin, and a fillet portion 40b in which the first resin extends from an opposing region of the semiconductor chip 20 and the mounting substrate 10. , A frame-shaped reinforcing material 34 surrounding the semiconductor chip 20, a first adhesive 42 for bonding the first end face of the reinforcing material 34 to the mounting substrate 10, and a reinforcing material 34. And a second adhesive for bonding the lid to the back surface of the semiconductor chip and to a second end surface of the reinforcement member opposite to the first end surface. 43, the reinforcing member 34, and the semiconductor chip. 20 aspect, a second filling portion 41 formed by filling the second resin into a space surrounded by a fillet portion 40b of the mounting board 10 and the first filling portion 40. The configuration of the semiconductor device 1d of the fifth embodiment is almost the same as the configuration of the semiconductor device 1, except that the groove 34a is formed on the first end face side of the four corners of the reinforcing member 34. That is, the groove 34a is also filled with the second resin. In a rectangular semiconductor device, since the length of the diagonal line is the longest, it is likely to be affected by expansion and contraction. In the semiconductor device 1d, the effect of suppressing the influence of expansion and contraction is obtained by the above structure.

本実施形態の半導体装置１ｄでは、補強材３４の材料として、熱膨張率がＡｌ、Ｃｕ、ＳＵＳのように搭載用基板１０に近い材料を用いるのが好ましい。搭載用基板１０と補強材３４の溝部３４ａ以外の部分、すなわち辺央部分との接着には、第１の接着材４２を用いてもよいが第２の樹脂４１を使用するのがより好ましい。また、コーナー部に設けられた溝部３４ａには、第２の樹脂が充填される。この第５の実施形態の構造による作用的特徴は、搭載用基板１０及び補強材３４の熱膨張特性をほぼ一致させると共に溝部３４ａに第２の樹脂を充填することによって搭載用基板１０の反りを抑えつつ半導体チップ２０直下の搭載用基板１０の反りを上述した第１充填部４０と第２充填部４１で抑制している。   In the semiconductor device 1d of the present embodiment, as the material of the reinforcing member 34, it is preferable to use a material having a coefficient of thermal expansion close to that of the mounting substrate 10, such as Al, Cu, or SUS. The first adhesive 42 may be used for bonding the mounting substrate 10 to a portion other than the groove 34 a of the reinforcing member 34, that is, the center portion of the periphery, but it is more preferable to use the second resin 41. The groove 34a provided at the corner is filled with a second resin. The functional feature of the structure of the fifth embodiment is that the thermal expansion characteristics of the mounting substrate 10 and the reinforcing member 34 are substantially matched, and the groove 34a is filled with the second resin to reduce the warpage of the mounting substrate 10. The warpage of the mounting substrate 10 immediately below the semiconductor chip 20 is suppressed by the first filling portion 40 and the second filling portion 41 while suppressing the above.

次に、本実施形態の半導体装置１ｄの製造方法について説明する。半導体装置１ｄの第１の製造方法は、第１の実施形態の半導体装置１の製造方法とほぼ同様であるので、異なる点のみについて説明する。第１の異なる点は、第１の端面が平坦な補強材３０の代わりに第１の端面の各コーナー部に溝部３４ａが形成された補強材３４を用いる点である。第２の異なる点は、補強材３４を用いることに伴うものであって、第１の接着材４２または第２の樹脂を枠状の補強材３４の形状と一致するように口字状に塗布し、更に溝部３４ａに対応する位置に第２の樹脂を重ねて塗布した後、補強材３４を第１の接着材４２または第２の樹脂が口字状に塗布された部分に位置合わせして第１の端面が第１の接着材４２または第２の樹脂４１と接するように載置する点である。他は、半導体装置１の製造方法と同様にして製造できる。   Next, a method for manufacturing the semiconductor device 1d of the present embodiment will be described. Since the first method for manufacturing the semiconductor device 1d is substantially the same as the method for manufacturing the semiconductor device 1 of the first embodiment, only different points will be described. A first different point is that a reinforcing member 34 having a groove 34a at each corner of the first end surface is used instead of the reinforcing member 30 having a flat first end surface. A second different point is that the reinforcing material 34 is used, and the first adhesive 42 or the second resin is applied in a square shape so as to match the shape of the frame-shaped reinforcing material 34. Then, after the second resin is further applied to the position corresponding to the groove 34a, the reinforcing material 34 is aligned with the first adhesive 42 or the portion where the second resin is applied in a bracket shape. The point is that the first end face is placed so as to be in contact with the first adhesive material 42 or the second resin 41. Others can be manufactured in the same manner as the manufacturing method of the semiconductor device 1.

次に、半導体装置１ｄの第２の製造方法について図１０（ａ）乃至（ｅ）、図１１（ａ）及び（ｂ）並びに図１２（ａ）及び（ｂ）を参照して説明する。先ず、搭載用基板１０及び補強材３４（但し、図１０（ａ）では図示せず）を準備する。搭載用基板１０の第１の面上には、搭載される半導体チップ２０のチップ電極２１と対応する位置に形成された内部ランド電極１１と、第１の面と反対側の第２の面上に形成された外部ランド電極１２とを備え、互いに対応する内部ランド電極１１と外部ランド電極１２が基板内配線１５により接続されている（図１０（ａ））。   Next, a second method for manufacturing the semiconductor device 1d will be described with reference to FIGS. 10 (a) to 10 (e), FIGS. 11 (a) and 11 (b), and FIGS. 12 (a) and 12 (b). First, the mounting substrate 10 and the reinforcing material 34 (however, not shown in FIG. 10A) are prepared. On the first surface of the mounting substrate 10, an internal land electrode 11 formed at a position corresponding to the chip electrode 21 of the semiconductor chip 20 to be mounted, and on a second surface opposite to the first surface. And the corresponding external land electrodes 12 are connected to each other by the in-substrate wiring 15 (FIG. 10A).

次に、搭載用基板１０の周縁部に熱膨張率が１６〜２２ｐｐｍ程度、弾性率が１１〜１２ＧＰａの第１の接着材４２を、予め準備してある枠状の補強材３４の形状と一致するように口字状に塗布した後、補強材３４を第１の接着材４２が塗布された部分に位置合わせして第１の端面が第１の接着材４２と接するように載置し、１２５℃程度で約１５分間仮キュアする（図１０（ｂ））。この状態では、補強材３０は搭載用基板１０に接着されているが、第１の接着材４２は熱硬化反応して、ゲル化が進行し一部固体化しているが未だ完全には固化していない。尚、第１の接着材４２は、例えばエポキシ系、ポリオレフィン系、シリコン系、シアネートエステル系、ポリイミド系、ポリノルボルネン系を含む樹脂群の中から選択された樹脂材料を主成分として、熱膨張率と弾性率が所望の値になるように無機質フィラーを適量混入させて調整してある。また、補強材３４の材料は、熱膨張率が搭載用基板１０の熱膨張率に近いＣｕ、ＳＵＳ（フェライト系ステンレス鋼）、Ａｌ等を含むグループの中から選択するのが好ましい。   Next, a first adhesive 42 having a coefficient of thermal expansion of about 16 to 22 ppm and an elasticity of 11 to 12 GPa is provided on the periphery of the mounting substrate 10 so as to conform to the shape of the frame-shaped reinforcing material 34 prepared in advance. After the application, the reinforcing member 34 is aligned with the portion where the first adhesive 42 is applied, and is placed so that the first end surface is in contact with the first adhesive 42. Temporarily cure at about 125 ° C. for about 15 minutes (FIG. 10B). In this state, the reinforcing material 30 is adhered to the mounting substrate 10, but the first adhesive material 42 undergoes a thermosetting reaction, and gelation proceeds to partially solidify, but is still completely solidified. Not. The first adhesive 42 has, as a main component, a resin material selected from a resin group including, for example, an epoxy-based, polyolefin-based, silicon-based, cyanate ester-based, polyimide-based, and polynorbornene-based resin, and has a coefficient of thermal expansion. And an appropriate amount of an inorganic filler is adjusted so that the elastic modulus becomes a desired value. The material of the reinforcing member 34 is preferably selected from a group containing Cu, SUS (ferritic stainless steel), Al, or the like, whose coefficient of thermal expansion is close to the coefficient of thermal expansion of the mounting substrate 10.

次に、チップ電極２１上にバンプ電極２２が接着された半導体チップ２０を、各バンプ電極２２が対応する内部ランド電極１１と接するように位置決め載置して、例えば窒素雰囲気中で２５０℃に加熱して搭載用基板１０の内部ランド電極１１にフリップチップ接続する（図１０（ｃ））。   Next, the semiconductor chip 20 having the bump electrodes 22 bonded to the chip electrodes 21 is positioned and mounted such that each bump electrode 22 is in contact with the corresponding internal land electrode 11, and heated to 250 ° C. in a nitrogen atmosphere, for example. Then, it is flip-chip connected to the internal land electrode 11 of the mounting substrate 10 (FIG. 10C).

次に、半導体チップ２０と搭載用基板１０との隙間にディイスペンサ等で第１の樹脂を滴下方法で注入・充填した後、１００℃程度で約１０分仮キュアして第１充填部４０を形成する（図１０（ｄ））。この状態では第１の樹脂も熱硬化反応して、ゲル化が進行し一部固体化しているが未だ完全には固化していない。尚、第１の樹脂は、例えばエポキシ系樹脂を熱膨張率が３２ｐｐｍ程度、弾性率が９ＧＰａ程度になるように調整したものである。第１の樹脂がこの特性であれば、流動性が１０００〜４００００ＣＰＳ（centipoises ）でありアンダーフィル部４０ａにボイドを発生させることなく注入・充填できる。このとき、第１の樹脂により、半導体チップ２０と搭載用基板１０との隙間のアンダーフィル部４０ａと共にこのアンダーフィル部４０ａから半導体チップ２０の周囲に延びるフィレット部４０ｂも形成される。但し、フィレット部４０ｂは補強材３４まで達することはなく、この時点ではフィレット部４０ｂと補強材３０との間に搭載用基板１０の第１の面が露出している。   Next, the first resin is injected and filled into the gap between the semiconductor chip 20 and the mounting substrate 10 by a dispenser or the like by a dropping method, and then temporarily cured at about 100 ° C. for about 10 minutes to form the first filling section 40. (FIG. 10D). In this state, the first resin also undergoes a thermosetting reaction, progresses gelation, and is partially solidified, but has not been completely solidified yet. The first resin is prepared, for example, by adjusting an epoxy resin to have a thermal expansion coefficient of about 32 ppm and an elastic modulus of about 9 GPa. If the first resin has this characteristic, the fluidity is 1000 to 40000 CPS (centipoises), and the resin can be injected and filled without generating voids in the underfill portion 40a. At this time, the first resin also forms an underfill portion 40a in a gap between the semiconductor chip 20 and the mounting substrate 10, and a fillet portion 40b extending from the underfill portion 40a to the periphery of the semiconductor chip 20. However, the fillet portion 40b does not reach the reinforcing member 34, and at this time, the first surface of the mounting substrate 10 is exposed between the fillet portion 40b and the reinforcing member 30.

次に、半導体チップ２０の裏面及び補強材３４の第２の端面に第２の接着材４３を塗布した後（図１０（ｅ））、蓋部３１を補強材３４で囲まれた領域全体を覆うように載置し、１５０℃程度で、３０分間程度加熱して第２の接着材４３を仮キュアして蓋部３１を接着させる（図１１（ａ）及び（ｂ））。尚、第２の接着材４３としては、熱膨張率が５０〜１００ｐｐｍ程度の例えばエポキシ系樹脂を用いることができる。また、第２の接着材４３の場合は、無機質フィラーとしてＡｇ、Ｃｕ粉末等を適量混入しておけば第２の接着材４３の熱伝導性が向上し、より好ましい。   Next, after the second adhesive 43 is applied to the back surface of the semiconductor chip 20 and the second end face of the reinforcing member 34 (FIG. 10E), the entire region surrounded by the reinforcing member 34 is covered with the lid 31. It is placed so as to cover it, and is heated at about 150 ° C. for about 30 minutes to temporarily cure the second adhesive 43 and adhere the lid 31 (FIGS. 11A and 11B). As the second adhesive 43, for example, an epoxy resin having a coefficient of thermal expansion of about 50 to 100 ppm can be used. Further, in the case of the second adhesive 43, it is more preferable to mix an appropriate amount of Ag, Cu powder, or the like as an inorganic filler, because the thermal conductivity of the second adhesive 43 is improved.

次に、補強材３４のコーナー部に形成された溝部３４ａの２ヶ所に加温圧入ノズル６０を接触させて、半導体チップ２０の側面，補強材３４の内壁，蓋部３１，搭載用基板１０及びフィレット部４０ｂで囲まれた空間に第２の樹脂を注入・充填して第２充填部４１を形成する（図１２（ａ）及び（ｂ））。尚、前述の空間に第２の樹脂を注入・充填する方法としては、トランスファーモールドで圧入する方法を用いることもできる。   Next, the heating and press-fitting nozzles 60 are brought into contact with two portions of the groove portions 34a formed at the corners of the reinforcing member 34, and the side surfaces of the semiconductor chip 20, the inner wall of the reinforcing member 34, the lid 31, the mounting substrate 10 and A second resin is injected and filled into a space surrounded by the fillet portion 40b to form a second filling portion 41 (FIGS. 12A and 12B). In addition, as a method of injecting and filling the second resin into the space described above, a method of press-fitting with a transfer mold can also be used.

次に、全体を約１７５℃まで緩やかに昇温させた後、更に約１７５℃の状態を６０分程度維持して本キュアすることで、第１充填部４０の第１の樹脂，第２充填部４１の第２の樹脂，第１の接着材４２及び第２の接着材４３を全て完全に硬化させる。その後、搭載用基板１０の外部ランド電極１２に外部端子となる例えば半田パンプ１３を一般的な方法で接着して、図５に示すような半導体装置１ｄが完成する。   Next, after the whole is gradually heated to about 175 ° C., the state is further maintained at about 175 ° C. for about 60 minutes, and the main curing is performed. The second resin, the first adhesive 42 and the second adhesive 43 of the portion 41 are all completely cured. Thereafter, for example, a solder pump 13 serving as an external terminal is bonded to the external land electrode 12 of the mounting substrate 10 by a general method, thereby completing a semiconductor device 1d as shown in FIG.

次に、本発明の半導体装置の第６の実施形態について説明する。
図６は、本発明の半導体装置の第６の実施形態の断面図で、図１（ｂ）に相当する図である。本実施形態の半導体装置１ｅは、第１の実施形態の半導体装置１の補強材３０を、有機材料の樹脂で形成された補強材３５に替えただけで、他の構成は全て半導体装置１と同じである。本実施形態の半導体装置１ｅの製造方法は、樹脂製の補強材３５を例えばトランスファー封止により予め製作して準備しておけば、その他の製造手順は図１３（ａ）乃至（ｅ）並びに図１４（ａ）及び（ｂ）に示すように第１の実施形態の半導体装置１の製造方法と同じであり、詳細な説明は省略する。概略を説明すれば、先ず搭載用基板１０に第１の接着材４２を塗布し、樹脂製補強材３５を載置して仮キュアする。次に半導体チップ２０を内部ランド電極１１にフリップチップ接続して、第１の樹脂を充填し仮キュアして第１充填部４０を形成する。次に、半導体チップ２０の側面，補強材３５の内壁，搭載用基板１０及びフィレット部４０ｂで囲まれた空間に第２の樹脂を注入・充填して第２充填部４１を形成した後、半導体チップ２０の裏面と補強材３５の第２の端面に第２の接着材４３を塗布して蓋部３１を載置し、本キュアして第１の接着材４２、第１充填部４０の第１の樹脂、第２充填部４１の第２の樹脂及び第２の接着材４３を完全に硬化させて半導体装置１ｅが完成する。 Next, a sixth embodiment of the semiconductor device of the present invention will be described.
FIG. 6 is a sectional view of a semiconductor device according to a sixth embodiment of the present invention, and is a view corresponding to FIG. The semiconductor device 1e of the present embodiment differs from the semiconductor device 1 of the first embodiment only in that the reinforcing member 30 of the semiconductor device 1 of the first embodiment is replaced with a reinforcing member 35 formed of an organic resin. Is the same. In the method of manufacturing the semiconductor device 1e according to the present embodiment, if a resin reinforcing material 35 is prepared and prepared in advance by, for example, transfer sealing, the other manufacturing procedures are the same as those shown in FIGS. As shown in FIGS. 14A and 14B, the method is the same as the method of manufacturing the semiconductor device 1 of the first embodiment, and a detailed description is omitted. In brief, first, the first adhesive 42 is applied to the mounting substrate 10, and the resin reinforcing material 35 is placed and temporarily cured. Next, the semiconductor chip 20 is flip-chip connected to the internal land electrode 11, filled with a first resin, and temporarily cured to form a first filling portion 40. Next, a second resin is injected and filled into a space surrounded by the side surface of the semiconductor chip 20, the inner wall of the reinforcing member 35, the mounting substrate 10, and the fillet portion 40b to form a second filling portion 41. A second adhesive 43 is applied to the back surface of the chip 20 and the second end surface of the reinforcing member 35, the lid 31 is placed, and the main adhesive is cured, and the first adhesive 42 and the first filler 40 are filled. The semiconductor device 1e is completed by completely curing the first resin, the second resin of the second filling portion 41, and the second adhesive 43.

尚、本実施形態の半導体装置１ｅの他の製造方法としては、搭載用基板１０をトランスファー封止用金型に載置して搭載用基板１０に一体的に樹脂製補強材３５を形成する方法も適用できる。この方法により図１３（ｂ）の形状が実現でき、その後は第１の実施形態の製造方法と同じ方法で処理できる。この方法によれば、製造工程の省力化ができる。   As another manufacturing method of the semiconductor device 1e of the present embodiment, a method of mounting the mounting substrate 10 on a transfer sealing mold and integrally forming the resin reinforcing material 35 on the mounting substrate 10 is described. Is also applicable. With this method, the shape shown in FIG. 13B can be realized, and thereafter, the processing can be performed by the same method as the manufacturing method of the first embodiment. According to this method, the labor of the manufacturing process can be saved.

次に、本発明の半導体装置の第７の実施形態について説明する。
図７は、本発明の半導体装置の第７の実施形態の断面図で、図１（ｂ）に相当する図である。本実施形態の半導体装置１ｆは、第１の実施形態の半導体装置１の補強材３０を、有機材料の樹脂で形成され且つ開口部が逆テーパ状の補強材３６に替えただけで、他の構成は全て半導体装置１と同じである。本実施形態の半導体装置１ｆでは第２充填部４１の上に補強材３６が庇状に覆い被さっている。この構造によってフィレット部４０ｂと第２充填部４１が蓋部３１側に変形するのを抑制できる効果がある。本実施形態の半導体装置１ｆの製造方法は、第６の実施形態の半導体装置１ｅの製造方法と同じである。 Next, a seventh embodiment of the semiconductor device of the present invention will be described.
FIG. 7 is a cross-sectional view of a semiconductor device according to a seventh embodiment of the present invention, and is a view corresponding to FIG. The semiconductor device 1f according to the present embodiment is different from the semiconductor device 1 according to the first embodiment only in that the reinforcing member 30 of the semiconductor device 1 according to the first embodiment is replaced with a reinforcing member 36 formed of a resin of an organic material and having an opening having an inverted tapered shape. The configuration is all the same as that of the semiconductor device 1. In the semiconductor device 1f of the present embodiment, the reinforcing material 36 covers the second filling portion 41 like an eave. This structure has an effect of suppressing the deformation of the fillet portion 40b and the second filling portion 41 toward the lid portion 31. The method of manufacturing the semiconductor device 1f of the present embodiment is the same as the method of manufacturing the semiconductor device 1e of the sixth embodiment.

以上説明したように、本発明によれば搭載用基板上に半導体チップをフリップチップ接続し、その搭載用基板と半導体チップの隙間に第１の樹脂を充填して第１充填部を形成し、半導体チップの周囲を囲むように補強材を取り付けて蓋部の支持体とした場合に、搭載用基板，半導体チップの側面，補強材及び蓋部で囲まれる空間に第１の樹脂よりも低熱膨張率の第２の樹脂を充填・硬化して第２充填部が形成してあるために、第１充填部の膨張・収縮による搭載用基板の上下方向の動きを第２充填部が抑制し、温度サイクルによるチップ電極や内部ランド電極の剥離や半田バンプのクラックの発生を防止できる。また、製造の初期に搭載用基板の強度を補強できるために製造工程中のハンドリング性を改善すると共に反りを抑えることができる。更に、各接着材及び各樹脂を各工程で仮キュアしておき、最後に本キュアして完全に硬化することで製造後の反りを最小に抑えることができる。   As described above, according to the present invention, a semiconductor chip is flip-chip connected on a mounting substrate, a gap between the mounting substrate and the semiconductor chip is filled with a first resin to form a first filling portion, When a reinforcing material is attached so as to surround the periphery of the semiconductor chip to serve as a support for the lid, the space surrounded by the mounting substrate, the side of the semiconductor chip, the reinforcing material and the lid has a lower thermal expansion than the first resin. The second filling portion is formed by filling and hardening the second resin at a predetermined rate, so that the second filling portion suppresses vertical movement of the mounting substrate due to expansion and contraction of the first filling portion, It is possible to prevent chip electrodes and internal land electrodes from peeling off due to a temperature cycle and to prevent cracks in solder bumps. Further, since the strength of the mounting substrate can be reinforced in the early stage of the manufacturing, the handleability during the manufacturing process can be improved and the warpage can be suppressed. Further, each adhesive and each resin are temporarily cured in each step, and finally, this is finally cured and completely cured, so that warpage after production can be minimized.

具体的には、例えば図１７（ａ）乃至（ｅ）は、それぞれ本発明の第１の実施形態乃至第５の実施形態の各半導体装置における搭載用基板の反りの状態を模式的に示す図である。尚、比較のために従来の半導体装置の搭載用基板の反りの状態を図１７（ｆ）に模式的に示している。図１７（ａ）乃至（ｆ）において、破線が搭載用基板の反りの状態を示している。図１７（ａ）乃至（ｅ）から分かるとおり、本発明の各実施形態の半導体装置の搭載用基板の反り量の最大値Wa, Wb, Wc, Wd及びWeは、いずれも従来の半導体装置の搭載用基板の反り量の最大値Wfよりも十分小さくなっていることが分かる。   Specifically, for example, FIGS. 17A to 17E are diagrams schematically showing warping states of the mounting substrate in each of the semiconductor devices according to the first to fifth embodiments of the present invention. It is. For comparison, FIG. 17F schematically shows a state of warpage of the mounting substrate of the conventional semiconductor device. 17A to 17F, broken lines indicate the warped state of the mounting substrate. As can be seen from FIGS. 17A to 17E, the maximum values Wa, Wb, Wc, Wd, and We of the amounts of warpage of the mounting substrate of the semiconductor device of each embodiment of the present invention are all smaller than those of the conventional semiconductor device. It can be seen that it is sufficiently smaller than the maximum value Wf of the amount of warpage of the mounting substrate.

また、図１８は、本発明の第１の実施形態の構造を備えた半導体装置のサンプル（半導体チップのサイズ：17.3mm×17.3mm、搭載用基板の厚さ：約１．０ｍｍ、搭載用基板のサイズ：50mm×50mm）について、当該サンプルの温度を変化させたときの半導体装置の反り量、具体的には搭載用基板の反り量、の実測結果を示すグラフである。尚、図１８には比較例として、従来構造の半導体装置（但し、半導体チップのサイズ、搭載用基板の厚さ及び搭載用基板のサイズは上記本発明のサンプルと同じ）の反り量も共に示してある。図１８から分かるとおり、温度サイクル試験における搭載用基板の反りの程度も、本発明の構造を備えた半導体装置の方が従来構造の半導体装置の場合よりも大幅に抑制されていることが分かる。   FIG. 18 is a sample of a semiconductor device having the structure of the first embodiment of the present invention (semiconductor chip size: 17.3 mm × 17.3 mm, mounting substrate thickness: about 1.0 mm, mounting substrate (Size: 50 mm × 50 mm) is a graph showing actual measurement results of the amount of warpage of the semiconductor device when the temperature of the sample is changed, specifically, the amount of warpage of the mounting substrate. FIG. 18 also shows, as a comparative example, the warpage of a semiconductor device having a conventional structure (however, the size of the semiconductor chip, the thickness of the mounting substrate, and the size of the mounting substrate are the same as those of the sample of the present invention). It is. As can be seen from FIG. 18, the degree of warpage of the mounting substrate in the temperature cycle test is significantly suppressed in the semiconductor device having the structure of the present invention as compared with the semiconductor device having the conventional structure.

また、第２の実施形態のように搭載用基板に補強材を固着する第１の接着材として、第２の樹脂を用いることにより、第１充填部の膨張・収縮による搭載用基板の上下方向の動きを一層抑制することができ、温度サイクルによるチップ電極や内部ランド電極の剥離や半田バンプのクラックの発生をより効果的に防止できる。   Further, by using the second resin as the first adhesive material for fixing the reinforcing material to the mounting substrate as in the second embodiment, the vertical direction of the mounting substrate due to expansion and contraction of the first filling portion. Can be further suppressed, and peeling of chip electrodes and internal land electrodes due to temperature cycles and generation of cracks in solder bumps can be more effectively prevented.

また、第５の実施形態のように補強材の第１の端面の４隅に溝部を形成し、この溝部に低熱膨張率の第２の樹脂を充填して補強材と搭載用基板の接着材の一部として用いることで、矩形形状の半導体装置で最も寸法が大きい対角線方向の膨張収縮の影響を一層抑制することができ、やはり温度サイクルによるチップ電極や内部ランド電極の剥離や半田バンプのクラックの発生をより効果的に防止できる。また、第５の実施形態の第２の製造方法によれば、蓋部３１を先に取り付けてから第２の樹脂を注入・硬化させて第２充填部４１を形成しているので第２の樹脂が完全に充填でき蓋部３１と第２充填部４１との間に空隙４７ができず搭載用基板１０の変形を抑制することができる。   Also, as in the fifth embodiment, grooves are formed at the four corners of the first end face of the reinforcing member, and the grooves are filled with a second resin having a low coefficient of thermal expansion to form an adhesive between the reinforcing member and the mounting substrate. By using it as a part of the semiconductor device, the influence of diagonal expansion and contraction, which is the largest dimension of a rectangular semiconductor device, can be further suppressed, and chip electrodes and internal land electrodes are peeled off due to temperature cycling, and cracks in solder bumps are also caused. Can be more effectively prevented. Further, according to the second manufacturing method of the fifth embodiment, the second filling portion 41 is formed by injecting and curing the second resin after attaching the lid portion 31 first, so that the second filling portion 41 is formed. The resin can be completely filled, and no gap 47 is formed between the lid portion 31 and the second filling portion 41, so that the deformation of the mounting substrate 10 can be suppressed.

本発明の半導体装置の第１の実施形態を示す図で、（ａ）及び（ｂ）はそれぞれ蓋部を外した状態の平面図及び（ａ）のＡ１−Ａ１’線に沿った位置で蓋部が取り付けられた状態の断面図である。1A and 1B are views showing a semiconductor device according to a first embodiment of the present invention, in which FIGS. 1A and 1B are plan views showing a state in which a lid portion is removed, and FIGS. It is sectional drawing of the state in which the part was attached. 本発明の半導体装置の第２の実施形態を示す図で、第１の実施形態の図１（ｂ）に相当する断面図である。FIG. 2 is a view showing a second embodiment of the semiconductor device of the present invention, and is a cross-sectional view corresponding to FIG. 1B of the first embodiment. 本発明の半導体装置の第３の実施形態を示す図で、（ａ）蓋部を外した状態の平面図であり、（ｂ）及び（ｃ）は（ａ）のＡ２−Ａ２’線に沿った位置で蓋部が取り付けられた状態の断面図及び（ｂ）の補強材と搭載用基板との接着部の部分拡大断面図である。It is a figure which shows 3rd Embodiment of the semiconductor device of this invention, Comprising: (a) It is a top view in the state which removed the cover part, (b) and (c) are along A2-A2 'line of (a). FIG. 4 is a cross-sectional view showing a state where a lid is attached at a position where the lid is attached, and a partially enlarged cross-sectional view of a bonding portion between a reinforcing material and a mounting substrate in FIG. 本発明の半導体装置の第４の実施形態を示す図で、第１の実施形態の図１（ｂ）に相当する断面図である。FIG. 6 is a view showing a fourth embodiment of the semiconductor device of the present invention, and is a cross-sectional view corresponding to FIG. 1B of the first embodiment. 本発明の半導体装置の第５の実施形態を示す図で、（ａ）は蓋部を外した状態の平面図であり、（ｂ）及び（ｃ）はいずれも蓋部が取り付けられた状態でそれぞれ（ａ）のＢ−Ｂ’線に沿った位置の部分断面図及び（ａ）のＣ−Ｃ’線に沿った位置の断面図である。5A and 5B are diagrams showing a fifth embodiment of the semiconductor device of the present invention, in which FIG. 5A is a plan view showing a state in which a lid is removed, and FIGS. FIG. 3A is a partial cross-sectional view taken along a line BB ′ in FIG. 3A and a cross-sectional view taken along a line CC ′ in FIG. 本発明の半導体装置の第６の実施形態を示す図で、第１の実施形態の図１（ｂ）に相当する断面図である。FIG. 9 is a view showing a sixth embodiment of the semiconductor device of the present invention, and is a cross-sectional view corresponding to FIG. 1B of the first embodiment. 本発明の半導体装置の第７の実施形態を示す図で、第１の実施形態の図１（ｂ）に相当する断面図である。FIG. 14 is a view showing a seventh embodiment of the semiconductor device of the present invention, and is a cross-sectional view corresponding to FIG. 1B of the first embodiment. （ａ）乃至（ｅ）は、第１の実施形態の半導体装置の製造方法を説明するための図で、図１（ａ）のＡ１−Ａ１’線に沿った位置での工程毎断面図である。FIGS. 3A to 3E are views for explaining a method of manufacturing the semiconductor device according to the first embodiment, and are cross-sectional views for respective steps at positions along the line A1-A1 ′ in FIG. is there. （ａ）乃至（ｃ）は、第１の実施形態の半導体装置の製造方法を説明するための図で、図１（ａ）のＡ１−Ａ１’線に沿った位置での図８に続く工程毎断面図である。8A to 8C are views for explaining the method of manufacturing the semiconductor device according to the first embodiment, and are steps subsequent to FIG. 8 at a position along the line A1-A1 'in FIG. It is each sectional view. （ａ）乃至（ｅ）は、第５の実施形態の半導体装置の製造方法を説明するための図で、図５（ａ）のＡ２−Ａ２’線に沿った位置の工程毎断面図である。5A to 5E are views for explaining a method for manufacturing a semiconductor device according to a fifth embodiment, and are sectional views for respective steps at positions along line A2-A2 'in FIG. . （ａ）及び（ｂ）は、第５の実施形態の半導体装置の製造方法を説明するための図で、いずれも図１０に続く同一工程の図で、それぞれ図５（ａ）のＡ２−Ａ２’線に沿った位置の断面図及びＣ−Ｃ’線に沿った位置の断面図である。(A) and (b) are views for explaining the method of manufacturing the semiconductor device according to the fifth embodiment, which are views of the same step following FIG. 10, and are each A2-A2 in FIG. It is sectional drawing of the position along the 'line, and sectional drawing of the position along the CC' line. （ａ）及び（ｂ）は、第５の実施形態の半導体装置の製造方法を説明するための図で、いずれも図１１に続く第２の樹脂を充填する工程の図であり、（ａ）は加温圧入ノズルが接続された状態の平面図、（ｂ）は（ａ）のＤ−Ｄ’線に沿った位置の断面図である。11A and 11B are views for explaining a method of manufacturing the semiconductor device according to the fifth embodiment, and are views illustrating steps of filling the second resin subsequent to FIG. FIG. 3 is a plan view showing a state where a heating press-fitting nozzle is connected, and FIG. 3B is a cross-sectional view taken along a line DD ′ in FIG. 第６の実施形態の半導体装置の製造方法を説明するための図で、図１（ａ）のＡ１−Ａ１’線に沿った位置での工程毎断面図である。FIG. 13 is a diagram for explaining the method for manufacturing the semiconductor device of the sixth embodiment, and is a sectional view for each step at a position along line A <b> 1-A <b> 1 ′ in FIG. 第６の実施形態の半導体装置の製造方法を説明するための図１３に続く図で、図１（ａ）のＡ１−Ａ１’線に沿った位置での工程毎断面図である。FIG. 14 is a view for explaining the manufacturing method of the semiconductor device according to the sixth embodiment, which is a cross-sectional view for each step at a position along line A <b> 1-A <b> 1 ′ in FIG. 第７の実施形態の半導体装置の製造方法を説明するための図で、図１（ａ）のＡ１−Ａ１’線に沿った位置での工程毎断面図であるFIG. 18 is a diagram for explaining the method for manufacturing the semiconductor device of the seventh embodiment, and is a cross-sectional view for each step at a position along line A1-A1 ′ in FIG. 第７の実施形態の半導体装置の製造方法を説明するための図１５に続く図で、図１（ａ）のＡ１−Ａ１’線に沿った位置での工程毎断面図であるFIG. 16 is a view illustrating the method for manufacturing the semiconductor device of the seventh embodiment, following FIG. 15, and is a cross-sectional view for each step at a position along line A1-A1 ′ in FIG. （ａ）乃至（ｅ）はそれぞれ本発明の各実施形態の構造の半導体装置における搭載用基板の反りの状態を模式的に示す図であり、（ｆ）は比較のために従来構造の半導体装置の搭載用基板の反りの状態を模式的に示す図である。(A) to (e) are diagrams schematically showing a warped state of a mounting substrate in a semiconductor device having a structure of each embodiment of the present invention, and (f) is a semiconductor device having a conventional structure for comparison. FIG. 3 is a view schematically showing a warped state of the mounting substrate. 本発明による構造を備えた半導体装置の温度を変化させたときの半導体装置の反り量の実測結果を示すグラフである。6 is a graph showing actual measurement results of the amount of warpage of the semiconductor device when the temperature of the semiconductor device having the structure according to the present invention is changed. （ａ）は従来構造の半導体装置で、蓋部を外した状態の平面図であり、（ｂ）は、（ａ）のＥ−Ｅ’線に沿った位置で蓋部が取り付けられた状態の断面図である。(A) is a plan view of a semiconductor device having a conventional structure in which a lid is removed, and (b) is a state in which the lid is attached at a position along the line EE 'of (a). It is sectional drawing. 従来の半導体装置の製造方法を説明するための図で、図１９のＥ−Ｅ’線に沿った位置での工程毎断面図である。FIG. 20 is a diagram for explaining the conventional method of manufacturing the semiconductor device, and is a sectional view for each step at a position along line E-E ′ in FIG. 19. 従来の半導体装置の製造方法を説明するための図２０に続く図で、図１９のＥ−Ｅ’線に沿った位置での工程毎断面図である。FIG. 21 is a view illustrating the method for manufacturing the conventional semiconductor device, following FIG. 20, and is a sectional view illustrating each step at a position along line E-E ′ in FIG. 19; 温度サイクル試験による従来構造の半導体装置の反りの状態を模式的に示す図である。FIG. 4 is a diagram schematically illustrating a warped state of a semiconductor device having a conventional structure by a temperature cycle test. 従来構造の半導体装置のバンプ電極周辺の拡大断面図である。FIG. 4 is an enlarged cross-sectional view around a bump electrode of a semiconductor device having a conventional structure.

符号の説明Explanation of reference numerals

１，１ａ，１ｂ，１ｃ，１ｄ，１ｅ，１ｆ 半導体装置
１０ 搭載用基板
１１ 内部ランド電極
１２ 外部ランド電極
１３ 半田バンプ
１５ 基板内配線
２０ 半導体チップ
２１ チップ電極
２２ バンプ電極
３０ 補強材
３１，３２，３３，３４，３５，３６ 蓋部
３４ａ 溝部
４０ 第１充填部
４０ａ アンダーフィル部
４０ｂ フィレット部
４１ 第２充填部
４２，４２ａ 第１の接着材
４３ 第２の接着材
４７ 空隙
５０ 凸部
６０ 加温圧入ノズル
1, 1a, 1b, 1c, 1d, 1e, 1f Semiconductor device 10 Mounting substrate 11 Internal land electrode 12 External land electrode 13 Solder bump 15 In-board wiring 20 Semiconductor chip 21 Chip electrode 22 Bump electrode 30 Reinforcement 31, 32, 33, 34, 35, 36 Lid 34a Groove 40 First filling 40a Underfill 40b Fillet 41 Second filling 42, 42a First adhesive 43 Second adhesive 47 Void 50 Convex 60 Heating Press-fit nozzle

Claims (22)

半導体チップと、
この半導体チップが第１の面にフリップチップ接続された搭載用基板と、
前記半導体チップと前記搭載用基板との間に第１の樹脂が充填されたアンダーフィル部とこのアンダーフィル部から前記第１の樹脂が延在したフィレット部とを有する第１充填部と、
前記半導体チップを囲む枠状の補強材と、
この補強材の第１の端面を前記搭載用基板に接着する第１の接着材と、
前記補強材で囲まれた領域を覆う蓋部と、
この蓋部を前記半導体チップの裏面及び前記補強材の第１の端面と反対側の第２の端面に接着する第２の接着材と、
前記半導体チップの側面，前記搭載用基板及び前記フィレット部で囲まれる空間に前記第１の樹脂と異なる第２の樹脂を充填した第２充填部と、を備えることを特徴とする半導体装置。 A semiconductor chip,
A mounting substrate in which the semiconductor chip is flip-chip connected to the first surface;
A first filling portion having an underfill portion filled with a first resin between the semiconductor chip and the mounting substrate, and a fillet portion extending the first resin from the underfill portion;
A frame-shaped reinforcing material surrounding the semiconductor chip,
A first adhesive for bonding a first end surface of the reinforcing material to the mounting substrate;
A lid that covers an area surrounded by the reinforcing material,
A second adhesive for bonding the lid to the back surface of the semiconductor chip and to a second end surface of the reinforcing member opposite to the first end surface;
A semiconductor device comprising: a second filling portion in which a space surrounded by the side surface of the semiconductor chip, the mounting substrate, and the fillet portion is filled with a second resin different from the first resin. 前記半導体チップの平面形状が矩形であり、前記第１の端面と前記搭載用基板との間であって前記半導体チップの平面形状の仮想的な対角線の延長部との交差領域を含む所定の対角領域に前記第２の樹脂が充填されている請求項１記載の半導体装置。   The semiconductor chip has a rectangular planar shape, and a predetermined pair including a crossing area between the first end surface and the mounting substrate and extending with a virtual diagonal extension of the planar shape of the semiconductor chip. 2. The semiconductor device according to claim 1, wherein a corner region is filled with the second resin. 前記補強材は、前記第１の端面の前記対角領域が凹部となっている請求項２記載の半導体装置。   The semiconductor device according to claim 2, wherein the diagonal region of the first end surface of the reinforcing member is a recess. 前記第１の接着材の厚さは、厚い部分と薄い部分が混在している請求項１乃至３いずれか１項に記載の半導体装置。   4. The semiconductor device according to claim 1, wherein a thickness of the first adhesive is a mixture of a thick portion and a thin portion. 5. 前記第１の端面は、前記搭載用基板に対向して凹部と凸部とが混在している請求項１乃至４いずれか１項に記載の半導体装置。   5. The semiconductor device according to claim 1, wherein the first end face includes a mixture of concave portions and convex portions facing the mounting substrate. 6. 前記搭載用基板と前記凹部との間に前記第１の接着材が充填されている請求項５記載の半導体装置。   6. The semiconductor device according to claim 5, wherein the first adhesive is filled between the mounting substrate and the recess. 前記搭載用基板と前記凹部との間に前記第２の樹脂が充填されている請求項５記載の半導体装置。   6. The semiconductor device according to claim 5, wherein the second resin is filled between the mounting substrate and the recess. 前記搭載用基板が前記補強材と対向する領域に第１の金属層を備えると共に、前記補強材が前記凸部の表面に第２の金属層を備え、前記搭載用基板と前記凸部とが低融点合金で接続されている請求項５乃至７いずれか１項に記載の半導体装置。   The mounting substrate includes a first metal layer in a region facing the reinforcing member, the reinforcing member includes a second metal layer on a surface of the convex portion, and the mounting substrate and the convex portion The semiconductor device according to claim 5, wherein the semiconductor device is connected by a low melting point alloy. 前記第２充填部は、前記補強材の内壁と、前記フィレット部と、前記搭載用基板と前記半導体チップの側壁に接触している請求項１乃至８いずれか１項に記載の半導体装置。   9. The semiconductor device according to claim 1, wherein the second filling portion is in contact with an inner wall of the reinforcing member, the fillet portion, the mounting substrate, and a side wall of the semiconductor chip. 10. 前記第２充填部が、蓋部の内壁とも接触している請求項９記載の半導体装置。   The semiconductor device according to claim 9, wherein the second filling portion is also in contact with an inner wall of the lid. 前記第２の樹脂の弾性率は、前記第１の樹脂の弾性率よりも大きい請求項１乃至１０いずれか１項に記載の半導体装置。   The semiconductor device according to claim 1, wherein an elastic modulus of the second resin is larger than an elastic modulus of the first resin. 前記第２の樹脂の熱膨張率が前記第１の樹脂の熱膨張率よりも小さい請求項１乃至１１いずれか１項に記載の半導体装置。   The semiconductor device according to claim 1, wherein a coefficient of thermal expansion of the second resin is smaller than a coefficient of thermal expansion of the first resin. 前記第１の接着材が前記第２の樹脂からなる請求項１乃至１２いずれか１項に記載の半導体装置。   The semiconductor device according to claim 1, wherein the first adhesive is made of the second resin. 前記第２の樹脂の熱膨張率が前記第１の接着材の熱膨張率よりも小さい請求項１乃至１２いずれか１項に記載の半導体装置。   The semiconductor device according to claim 1, wherein a thermal expansion coefficient of the second resin is smaller than a thermal expansion coefficient of the first adhesive. 前記補強材は、Ｃｕ、ＳＵＳ、Ａｌ、アルミナ、シリコン、窒化アルミニウム及び樹脂を含むグループの中から選択された材料で形成されている請求項１乃至１４いずれか１項に記載の半導体装置。   The semiconductor device according to claim 1, wherein the reinforcing material is formed of a material selected from a group including Cu, SUS, Al, alumina, silicon, aluminum nitride, and a resin. 前記第１の樹脂と前記第２の樹脂はいずれも、エポキシ系、ポリオレフィン系、シリコン系、シアネートエステル系、ポリイミド系、ポリノルボルネン系を含む樹脂群の中から選択された樹脂を主成分とする請求項１乃至１５いずれか１項に記載の半導体装置。   Each of the first resin and the second resin contains, as a main component, a resin selected from a resin group including epoxy, polyolefin, silicon, cyanate ester, polyimide, and polynorbornene. The semiconductor device according to claim 1. 前記搭載用基板と前記第１の端面の間に、前記第１の接着材と異なるギャップ部材が部分的に配置されている請求項１乃至４いずれか１項に記載の半導体装置。   The semiconductor device according to claim 1, wherein a gap member different from the first adhesive is partially disposed between the mounting substrate and the first end surface. 前記ギャップ部材は、低融点合金からなる請求項１７記載の半導体装置。   18. The semiconductor device according to claim 17, wherein the gap member is made of a low melting point alloy. 搭載用基板に補強材を接着する工程と、搭載用基板に半導体チップを接続する工程と、第１の樹脂を充填・硬化する工程と、第２の樹脂を充填・硬化する工程と、蓋部を取り付ける工程と、半田バンプを接続する工程とを備え、少なくとも前記搭載用基板に補強材を接着する工程を第１番目の工程とし、前記搭載用基板に半導体チップを接続する工程を２番目の工程としたことを特徴とする半導体装置の製造方法。   A step of bonding a reinforcing material to the mounting board, a step of connecting a semiconductor chip to the mounting board, a step of filling and curing a first resin, a step of filling and curing a second resin, And a step of attaching a reinforcing material to at least the mounting substrate as a first step, and a step of connecting a semiconductor chip to the mounting substrate as a second step. A method for manufacturing a semiconductor device, comprising the steps of: 前記搭載用基板に補強材を接着する工程は第１の接着材を前記搭載用基板に塗布するステップと、前記補強材を前記第１の接着材の上に載置した後前記第１の接着材を半硬化させるステップを含み、
前記第１の樹脂を充填・硬化する工程は前記第１の樹脂を前記半導体チップと前記搭載用基板との隙間に充填するステップと、前記第１の樹脂を半硬化させるステップを含み、
前記第２の樹脂を充填・硬化する工程は前記第２の樹脂を充填するステップと、前記第２の樹脂を半硬化させるステップを含み、
前記蓋部を取り付ける工程は第２の接着材を塗布するステップと、前記蓋部を前記第２の接着材の上に載置するステップと、前記第２の接着材を硬化させるステップを含み、
前記第２の接着材を硬化させるステップにおいて、前記第１の接着材，前記第２の接着材，前記第１の樹脂及び前記第２の樹脂の全てが本硬化される請求項１９記載の半導体装置の製造方法。 The step of bonding a reinforcing material to the mounting substrate includes applying a first adhesive to the mounting substrate, and placing the reinforcing material on the first bonding material and then performing the first bonding. Semi-curing the material,
The step of filling and curing the first resin includes a step of filling the gap between the semiconductor chip and the mounting substrate with the first resin, and a step of semi-curing the first resin.
The step of filling and curing the second resin includes a step of filling the second resin and a step of semi-curing the second resin,
The step of attaching the lid includes applying a second adhesive, placing the lid on the second adhesive, and curing the second adhesive.
20. The semiconductor according to claim 19, wherein in the step of curing the second adhesive, all of the first adhesive, the second adhesive, the first resin, and the second resin are fully cured. Device manufacturing method. 搭載用基板に補強材を接着する工程と、搭載用基板に半導体チップを接続する工程と、第１の樹脂を充填・硬化する工程と、第２の樹脂を充填・硬化する工程と、蓋部を取り付ける工程と、半田バンプを接続する工程とを備え、前記第２の樹脂の充填・硬化する工程は蓋部を取り付ける工程の後に実施することを特徴とする半導体装置の製造方法。   A step of bonding a reinforcing material to the mounting board, a step of connecting a semiconductor chip to the mounting board, a step of filling and curing a first resin, a step of filling and curing a second resin, And a step of connecting solder bumps, and the step of filling and curing the second resin is performed after the step of attaching a lid. 前記搭載用基板に補強材を接着する工程は第１の接着材を前記搭載用基板に塗布するステップと、前記補強材を前記第１の接着材の上に載置した後前記第１の接着材を半硬化させるステップを含み、
前記第１の樹脂を充填・硬化する工程は前記第１の樹脂を前記半導体チップと前記搭載用基板との隙間に充填するステップと、前記第１の樹脂を半硬化させるステップを含み、
前記第２の樹脂を充填・硬化する工程は前記第２の樹脂を充填するステップと、前記第２の樹脂を半硬化させるステップを含み、
前記蓋部を取り付ける工程は第２の接着材を塗布するステップと、前記蓋部を前記第２の接着材の上に載置するステップと、前記第２の接着材を硬化させるステップを含み、
前記第２の樹脂を硬化させるステップにおいて、前記第１の接着材，前記第２の接着材，前記第１の樹脂及び前記第２の樹脂の全てが本硬化される請求項２１記載の半導体装置の製造方法。
The step of bonding a reinforcing material to the mounting substrate includes applying a first adhesive to the mounting substrate, and placing the reinforcing material on the first bonding material and then performing the first bonding. Semi-curing the material,
The step of filling and curing the first resin includes a step of filling the gap between the semiconductor chip and the mounting substrate with the first resin, and a step of semi-curing the first resin.
The step of filling and curing the second resin includes a step of filling the second resin and a step of semi-curing the second resin,
The step of attaching the lid includes applying a second adhesive, placing the lid on the second adhesive, and curing the second adhesive.
22. The semiconductor device according to claim 21, wherein in the step of curing the second resin, all of the first adhesive, the second adhesive, the first resin, and the second resin are fully cured. Manufacturing method.
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US8324718B2 (en) 2012-12-04

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