US20150262902A1 - Integrated circuits protected by substrates with cavities, and methods of manufacture - Google Patents

Integrated circuits protected by substrates with cavities, and methods of manufacture Download PDF

Info

Publication number
US20150262902A1
US20150262902A1 US14214365 US201414214365A US2015262902A1 US 20150262902 A1 US20150262902 A1 US 20150262902A1 US 14214365 US14214365 US 14214365 US 201414214365 A US201414214365 A US 201414214365A US 2015262902 A1 US2015262902 A1 US 2015262902A1
Authority
US
Grant status
Application
Patent type
Prior art keywords
substrate
die
cavity
manufacture
surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US14214365
Inventor
Hong Shen
Charles G. Woychik
Arkalgud R. Sitaram
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Invensas Corp
Original Assignee
Invensas Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/055Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486Via connections through the substrate with or without pins
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/14Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147Semiconductor insulating substrates
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/315Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the encapsulation having a cavity
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367Cooling facilitated by shape of device
    • H01L23/3675Cooling facilitated by shape of device characterised by the shape of the housing
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481Internal lead connections, e.g. via connections, feedthrough structures
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838Geometry or layout
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561Batch processing
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06548Conductive via connections through the substrate, container, or encapsulation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06555Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/10Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12042LASER
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

Dies (110) with integrated circuits are attached to a wiring substrate (120), possibly an interposer, and are protected by a protective substrate (410) attached to a wiring substrate. The dies are located in cavities in the protective substrate (the dies may protrude out of the cavities). In some embodiments, each cavity surface puts pressure on the die to strengthen the mechanical attachment of the die the wiring substrate, to provide good thermal conductivity between the dies and the ambient (or a heat sink), to counteract the die warpage, and possibly reduce the vertical size. The protective substrate may or may not have its own circuitry connected to the dies or to the wiring substrate. Other features are also provided.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • The present application claims priority of U.S. provisional application No. 61/952,066 filed on Mar. 12, 2014, titled “INTEGRATED CIRCUITS PROTECTED BY SUBSTRATES WITH CAVITIES, AND METHODS OF MANUFACTURE”, incorporated herein by reference.
  • BACKGROUND OF THE INVENTION
  • This document relates to integrated circuits, and more particularly to assemblies having dies that include semiconductor integrated circuits.
  • In fabrication of integrated circuits, one or more circuits are manufactured in a semiconductor wafer and are then separated into “dies” (also called “chips”) in a process called “singulation” or “dicing”. The dies, such as shown at 110 in FIG. 1, are attached to a wiring substrate (“WS”, e.g. printed wiring board) 120 which has conductive lines 130 connecting the dies to each other and to other elements of the system. More particularly, the dies have contact pads 110C connected to the dies' circuits (not shown), and these contact pads are attached to contact pads 120C of WS 120. Pads 120C are interconnected by conductive lines 130. The attachment of pads 110C to pads 120C is performed by connections 140 which may include solder, conductive epoxy, or other types.
  • Encapsulant 150 (e.g. epoxy with silica or other particles) protects the dies 110 and the connections 140 from moisture and other contaminants, ultraviolet light, alpha particles, and possibly other harmful elements. The encapsulant also strengthens the die-to-WS attachment against mechanical stresses, and helps conduct heat away from the dies (to an optional heat sink 160 or directly to the ambient (e.g. air)).
  • It is desirable to provide improved protection of dies from mechanical stresses, heat, and harmful elements.
  • SUMMARY
  • This section summarizes some of the exemplary implementations of the invention.
  • In some embodiments, the dies are protected by an additional, protective substrate attached to a wiring substrate. The dies are located in cavities in the protective substrate (the dies may protrude out of the cavities). The protective substrate may be similar to cap wafers used to protect MEMS components (Micro-Electro-Mechanical Structures); see K. Zoschke et al., “Hermetic Wafer Level Packaging of MEMS Components Using Through Silicon Via and Wafer to Wafer Bonding Technologies” (2013 Electronic Components & Technology Conference, IEEE, pages 1500-1507); see also U.S. Pat. No. 6,958,285 issued Oct. 25, 2005 to Siniaguine. However, in some embodiments, the protective substrate puts pressure on the die (e.g. each die may physically contact the cavity surface) to strengthen the die-to-WS 120 mechanical attachment, to provide good thermal conductivity between the die and the protective substrate, to help flatten the die if it is warped, and to reduce the vertical dimension. The protective substrate may or may not have its own circuitry connected to the dies or to the wiring substrate.
  • In some embodiments, the die does not contact the cavity surface, but the die is separated from the cavity surface by solid material (e.g. a bonding layer) which physically contacts the die and the cavity surface. In some embodiments, the die or the solid material physically contacts the cavity surface at some but not all operating temperatures (e.g. the physical contact may exist only at higher temperatures at which the die expands). An operating temperature is a temperature at which electrically functionality can be obtained.
  • In some embodiments, the cavity contains a stack of dies, and the top die in a stack contacts the cavity surface (or a solid material overlying the top die physically contacts the cavity surface). In some embodiments, the entire top surface of each die, or the top die in the stack if there is a stack, physically contacts the cavity surface. In some embodiments, the protective substrate puts downward pressure on the dies in each cavity to strengthen the dies' attachment to the wiring substrate and to counteract the die warpage.
  • In some embodiments, the wiring substrate is an interposer. Interposers are commonly used as intermediate substrates to accommodate a mismatch between die fabrication technology and printed wiring substrates (PWSs). More particularly, the die's contact pads 110C can be placed much closer to each other (at a smaller pitch) than PWS pads 120C. Therefore (FIG. 2), an intermediate substrate 120.1 can be used between the dies 120 and the PWS (shown at 120.2). Interposer 120.1 includes a substrate 120.1S (e.g. semiconductor or other material), a redistribution layer (RDL) 210.T on top of substrate 120.1S, and another redistribution layer 210.B on the bottom of substrate 120.1S. Each RDL 210.T, 210.B includes interconnect lines 216 insulated from each other and from substrate 120.1S by the RDL's dielectric 220. Lines 216 are connected to contact pads 120.1C.T on top of the interposer and contact pads 120.1C.B on the bottom. Lines 216 of RDL 210.T are connected to lines 216 of RDL 210.B by conductive (e.g. metallized) through-vias 224. Pads 120.1C.T are attached to the dies' pads 110C by connections 140.1 as in FIG. 1. Pads 120.1C.B are attached to pads 120.2C of PWS 120.2 with connections 140.2. Pads 120.1C.B are at a larger pitch than pads 120.1C.T, to accommodate the pitch of the PWS contacts 120.2C.
  • The interposer substrate 120.1S should be as thin as possible to shorten the signal paths between dies 110 and PWS 120.2 and thus make the system faster and less power hungry. Also, if the interposer is thin, fabrication of metallized vias 224 is facilitated. However, thin interposers are hard to handle: they are brittle, easily warped, and do not absorb or dissipate heat during fabrication. Therefore, a typical fabrication process (such as described in Zoschke et al. cited above) attaches the interposer to a temporary substrate (“support wafer”) during fabrication. The support wafer is later removed. Attaching and detaching temporary support wafers is burdensome. The process of the aforementioned U.S. Pat. No. 6,958,285 does not use the support wafer. Neither some of the novel processes described below.
  • The invention is not limited to the features and advantages described above, and includes other features described below.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIGS. 1 and 2 illustrate vertical cross-sections of assemblies including integrated circuits and constructed according to prior art.
  • FIGS. 3A, 3B, 3C, 3D, 3E, 4A, 4B, 4C, 5A, 5B, 5C, 5D, 5E.1, 6, 7, 8A, 8B, 8C, 9A, 9B, 9C, 9D, 10 illustrate vertical cross-sections of structures according to some embodiments as set forth in detail below.
  • FIGS. 5E.2 and 5E.3 are bottom views of horizontal cross sections according to some embodiments as set forth in detail below.
  • FIGS. 6, 7, 8A, 8B, 8C, 9A, 9B, 9C, 9D, 10, 11, 12 illustrate vertical cross-sections of structures according to some embodiments as set forth in detail below.
  • DESCRIPTION OF SOME EMBODIMENTS
  • The embodiments described in this section illustrate but do not limit the invention. In particular, the invention is not limited to particular materials, processes, dimensions, or other particulars except as defined by the appended claims.
  • FIG. 3A shows the beginning stages of fabrication of an interposer 120.1 according to some embodiments of the present invention. The interposer substrate 120.1S is initially chosen to be sufficiently thick to provide easy handling and adequate heat dissipation in fabrication. In some embodiments, substrate 120.1S is a monocrystalline silicon wafer of a 200 mm or 300 mm diameter and a thickness of 650 micron or more. These materials and dimensions are exemplary and do not limit the invention. For example, substrate 120.1S can be made of other semiconductor materials (e.g. gallium arsenide), or glass, or sapphire, or metal, or possibly other materials. Possible materials include NbTaN and LiTaN. The substrate will later be thinned; for example, in case of silicon, the final thickness could be 5 to 50 microns. Again, these dimensions are not limiting.
  • Substrate 120.1S is patterned to form blind vias 224B (FIG. 3B). “Blind” means that the vias do not go through substrate 120.1S. This can be done, for example, as follows for silicon substrates. First, optional layer 310 (FIG. 3A) is formed on substrate 120.1S to protect the substrate and/or improve the adhesion of subsequently formed photoresist 320. For example, layer 310 can be silicon dioxide formed by thermal oxidation, chemical vapor deposition (CVD), or sputtering. Then photoresist 320 is deposited and photolithographically patterned to define the vias. Layer 310 and substrate 120.1S are etched in areas exposed by resist 320 to form the blind vias. The via depth is equal or slightly greater than the final depth of substrate 120.1S, e.g. 5 to 51 microns for some silicon-substrate embodiments. The vias can be formed by a dry etch, e.g. dry reactive ion etching (DRIE). An exemplary diameter of each via can be 60 microns or less, but other dimensions are possible. The vias can be vertical (as shown) or may have sloped sidewalls. As noted above, the particular dimensions, processes and other features are illustrative and not limiting.
  • The vias are then metallized. If substrate 120.1S is silicon, this can be done as follows. Photoresist 320 and protective layer 310 are removed, and a dielectric layer 324 (FIG. 3C) is formed on the entire top surface of substrate 120.1S. Dielectric 324 lines the via surfaces. In some embodiments, dielectric 324 is formed by thermal oxidation of the silicon substrate or by CVD or physical vapor deposition (PVD). Dielectric 324 will electrically insulate the substrate from subsequently formed metal in vias 224B. The dielectric thickness depends on the desired process parameters, and is 1 micron in an exemplary thermal-oxide embodiment (a thermal oxide is silicon dioxide formed by thermal oxidation). Other dimensions and materials can be used instead. Dielectric 324 can be omitted if substrate 120.1S is itself dielectric.
  • Then metal 224M (FIG. 3D) is formed in vias 224B over the dielectric 324. In the embodiment shown, metal 224M fills up the vias, but in other embodiments the metal is a liner on the via surfaces. In an exemplary embodiment, metal 224M is electroplated copper. For example, a barrier layer (metal or dielectric, not shown separately) is formed first on dielectric 324 to aid in copper adhesion and prevent copper diffusion into the dielectric 324 or substrate 120.1S. Suitable barrier layers may include a layer of titanium-tungsten (see Kosenko et al., US pre-grant patent publication 2012/0228778 published Sep. 13, 2012, incorporated herein by reference), and/or nickel containing layers (Uzoh et al., US 2013/0014978 published Jan. 17, 2013, incorporated herein by reference). Then a seed layer, e.g. copper, is formed on the barrier layer by physical vapor deposition (e.g. PVD, possibly sputtering). Then copper is electroplated on the seed layer to fill the vias 224B and cover the whole substrate 120.1S. The copper is then removed from the areas between the vias by chemical mechanical polishing (CMP). Optionally, the CMP may also remove the barrier layer (if present) from these areas, and may stop on dielectric 324. As a result, the copper and the barrier layer remain only in and over the vias 224B.
  • For ease of description, we will refer to vias 224 as “metallized”, but non-metal conductive materials can also be used (e.g. doped polysilicon).
  • If layer 224M does not fill the vias but only lines the via surfaces, some other material (not shown) can be formed on layer 224M as a filler to fill the vias and provide a planar top surface for the wafer. This filler material can be polyimide deposited by spin coating for example.
  • Optionally, RDL 210.T (FIG. 3E) is formed on top of substrate 120.1S to provide contact pads 120.1C.T at desired locations. RDL 210.T can be formed by prior art techniques described above in connection with FIGS. 1 and 2 for example. RDL 210.T is omitted if the contact pads 120.1C.T are provided by the top areas of metal 224M. In such a case, if substrate 120.1S is not dielectric, then a dielectric layer can be formed on the substrate and photolithographically patterned to expose the contact pads 120.1C.T.
  • Interposer 120.1 may include transistors, resistors, capacitors, and other devices (not shown) in substrate 120.1S and redistribution layer 210.T. These devices can be formed before, during and/or after the fabrication of vias 224 and RDL 210.T using the process steps described above and/or additional process steps. Such fabrication techniques are well known. See e.g. the aforementioned U.S. Pat. No. 6,958,285 and pre-grant patent publication 2012/0228778.
  • Dies 110 are attached to contact pads 120.1C.T with connections 140.1, using possibly prior art methods described above in connection with FIGS. 1 and 2 or other methods (e.g. diffusion bonding; in this case the connections 140.1 are not additional elements but are part of contact pads 110C and/or 120.1C.T).
  • Optionally, an encapsulant (not shown) can be formed around the dies and/or under the dies using the same techniques as described above in connection with FIG. 1 (e.g. by molding and/or underfilling). The encapsulant can be any suitable material (e.g. epoxy with silica or other particles). No encapsulant is used in some embodiments. Other embodiments use an encapsulant, but the requirements for the encapsulant are relaxed because the dies will be protected by an additional, protective substrate 410 (FIG. 5A) as described below. In some embodiments, the encapsulant is provided only underneath the dies (as underfill), i.e. only between the dies and substrate 120.1S (around the connections 140.1).
  • FIGS. 4A-4C illustrate fabrication of protective substrate 410. Many variations are possible. Substrate 410 should be sufficiently rigid to facilitate subsequent handling of the assembly as explained below. In the embodiment shown, substrate 410 includes monocrystalline silicon substrate 410S of a thickness 650 microns or higher. Other materials and thicknesses are possible, based on any factors that may be important (including the availability of materials and processes). One possible factor is reducing the mismatch of the coefficients of thermal expansion (CTE) between substrates 410 and 120.1S: if substrate 120.1S is silicon, then substrate 410S could be silicon or another material with a similar CTE. Another factor is reducing the CTE mismatch between substrate 410 and dies 110. In some embodiments, substrate 410S will not have any circuitry, but if circuitry is desired in or on substrate 410S then this may affect the choice of material. The circuitry can be fabricated before, and/or during, and/or after the steps described below.
  • Another possible factor is high thermal conductivity to enable the substrate 410 to act as a heat sink. For example, metal may be appropriate.
  • Cavities 414 (FIG. 4C) are formed in substrate 410 to match the size and position of dies 110. An exemplary process is as follows (this process is appropriate for a silicon substrate 410S, and may be inappropriate for other materials; known processes can be used for silicon or other materials). First, an auxiliary layer 420 (FIG. 4B) is formed to cover the substrate 410S for protection or for improved adhesion of subsequently formed photoresist 430. Resist 430 is deposited and patterned photolithographically to define the cavities. Auxiliary layer 420 exposed by the resist openings is etched away. Then substrate 410S is etched in these openings to form cavities 414 with sloped, upward-expanding sidewalls. The cavity depth depends on the thickness of dies 414 and connections 140.1 as explained below. Non-sloped (vertical) or retrograde sidewalls, or other sidewall profiles are also possible.
  • Then photoresist 430 is removed. In the example shown, auxiliary layer 420 is also removed, but in other embodiments layer 420 remains in the final structure.
  • As shown in FIG. 5A, substrate 410 is attached to interposer 120.1 so that each die 110 fits into a corresponding cavity 414. More particularly, legs 410L of protective substrate 410 are attached to the top surface of interposer 120.1 (e.g. to RDL 210.T if the RDL is present; legs 410L are those portion(s) of protective substrate 410 that surround the cavities). The substrate-to-interposer attachment is shown as direct bonding, but other types of attachments (e.g. by adhesive) can also be used as described further below. The entire assembly is marked with numeral 504.
  • In FIG. 5A, the dies' top surfaces physically contact the top surfaces of cavities 414. In some embodiments, each die's top surface is bonded to the cavity top surface (directly or in some other way, e.g. by adhesive). This bonding increases the bonding strength between the two substrates and improves the thermal conductivity of the thermal path from the dies to the protective substrate. In addition, the bond between the dies and the cavity surfaces restricts the dies' lateral motion and thus counteracts lateral or other forces that could weaken the connections 140.1. For example, if the protective substrate 410 and interposer 120.1 have matching CTEs, then the bonding of the dies' top surfaces to the cavity surfaces will cause the protective substrate 410 to urge the dies to follow the interposer movement in thermal cycling; this is believed to relieve the stress on the die-to-interposer connections 140.1.
  • In other embodiments, the dies are not bonded to the cavities' top surfaces, and thus the dies' top surfaces can slide laterally along the cavities' top surfaces in thermal movement. This may reduce the thermal stresses, e.g. if the die-interposer CTE matching is better than the matching between the interposer and protective substrate 410.
  • In some embodiments, regardless of whether the dies are bonded to the cavity surfaces, the downward pressure of substrate 410 on the dies helps counteract the die warpage. In some embodiments, the dies' tendency to warp increases with temperature, and the pressure may also increase with temperature (e.g. if the dies expand vertically more than the protective substrate's legs 410L).
  • As noted above, in some embodiments the dies are underfilled and/or encapsulated from above by a suitable stress-relieving material, e.g. epoxy. In case of encapsulation from above, the encapsulant may be a solid material (possibly thermosetting) physically contacting the top surfaces of cavities 414. The encapsulant may or may not be bonded to the cavity surfaces as described above, with benefits similar to those described above for the no-encapsulant embodiments.
  • To ensure physical contact between the dies (or the encapsulant) and the cavities, the top surfaces of the dies (or encapsulant) should have uniform height. To improve the height uniformity, the dies (or encapsulant) can be polished before joining of substrate 410 to interposer 120.1. Suitable polishing processes include lapping, grinding, and chemical mechanical polishing (CMP). Also, before inserting the dies into cavities, the cavity surfaces and/or the dies can be provided with a suitable temperature interface material (TIM, not shown here but shown at 525 in FIGS. 5E.2 and 5E.3 discussed below) to improve the thermal transfer between the dies and substrate 410. TIM's thermal conductivity can usually be higher than that of air. Exemplary TIMs are those that exist in semisolid, gel-like (grease-like) state throughout the range of expected operating temperatures (e.g. 0° C. to 200° C. for some assemblies) or at least when the temperatures are high to make die cooling particularly desirable (20° C. to 200° C. for some assemblies). The gel-like materials fill free spaces between the dies and substrate 410 to provide a thermally conductive path away from the dies. An exemplary TIM material is a thermal grease available from Arctic Silver, Inc. (having an office in California, USA); the grease's thermal conductivity is 1 W/mK.
  • After the bonding of substrate 410 to interposer 120.1, the interposer is thinned from the bottom to expose the metal 224M (FIG. 5B). The thinning involves partial removal of substrate 120.1S and dielectric 324 (if the dielectric is present). The thinning may be performed by known techniques (e.g. mechanical grinding or lapping of substrate 120.1S followed by dry or wet, masked or unmasked etch of substrate 120.1S and dielectric 324; the substrate and the dielectric are etched simultaneously in some embodiments.) In some embodiments, dielectric 324 protrudes out of substrate 120.1S around metal 224M at the end of the thinning operation, and metal 224M protrudes out of the dielectric. See for example the aforementioned U.S. Pat. No. 6,958,285. As noted above, the invention is not limited to particular processes.
  • Advantageously, interposer 120.1 is kept flat by substrate 410, so the handling of the assembly 504 is facilitated. Substrate 410 also helps absorb and dissipate the heat generated during this and subsequent fabrication stages and in subsequent operation of assembly 504. The final thickness of substrate 120.1S can therefore be very low, e.g. 50 microns or even 5 microns or less. Hence, blind vias 224B (FIG. 3B) can be shallow. The shallow depth facilitates fabrication of the metallized vias (i.e. facilitates the via etch and subsequent deposition of dielectric and metal into the vias). The shallow depth also shortens the signal paths through the vias. Moreover, if the vias are shallow, each via can be narrower while still allowing reliable dielectric and metal deposition. The via pitch can therefore be reduced.
  • If desired, protective substrate 410 can be thinned from the top; this is not shown. The combined thickness of substrates 120.1S and 410 is defined by desired properties, such as rigidity, resistance to warpage, heat dissipation, and assembly size.
  • Subsequent process steps depend on the particular application. In some embodiments (FIG. 5C), RDL 210.B is formed on the bottom of substrate 120.1S, possibly using prior art techniques (as in FIG. 2 for example). The RDL provides contact pads 120.1C.B and connects them to metal 224M. (If the RDL is omitted, the contact pads are provided by metal 224M). If desired, the assembly 504 can be diced into stacks 504S (FIG. 5D). Then the stacks (or the entire assembly 504 if dicing is omitted) are attached to other structures, such as wiring substrate 120.2 (e.g. a printed wiring substrate) in FIG. 5E.1. In the example of FIG. 5E.1, a stack 504S is attached to PWS 120.2, and more particularly the stack's contacts 120.1C.B are attached to PWS contacts 120.2C, possibly by the same techniques as in FIG. 1 or 2. Conductive lines 130 of PWS 120.2 connect the contact pads 120.2C to each other or other elements. These details are not limiting.
  • FIG. 5E.2 shows a possible bottom view of the horizontal cross section along the line 5E.2-5E.2 in FIG. 5E.1. In the example of FIG. 5E.2, the dies are surrounded by temperature interface material (TIM) 525. The legs 410L form a region completely surrounding each die, and the interposer area bonded to the legs also completely surrounds each die.
  • FIG. 5E.3 shows another possible bottom view of the same horizontal cross section, also with TIM 525. In this example, the legs 410L are provided only on two opposite sides of each die (left and right sides) but are not provided above and below the dies. Each cavity 414 is a horizontal groove in substrate 410S, possibly containing multiple dies spread laterally along the groove. The groove may run through the entire substrate. Other cavity shapes are also possible.
  • As noted above, protective substrate 410 and interposer 120.1 can be bonded by adhesive, and FIG. 6 illustrates such bonding by adhesive 610. Adhesive 610 is provided on legs 140L or the corresponding areas of interposer 120.1 or both. The structure is shown at the stage of FIG. 5A (before interposer thinning). In some embodiments, the adhesive is elastic, with a low elasticity modulus (e.g. silicone rubber with elasticity modulus of 50 MPa), to help absorb the thermal expansion of dies 110 (so that the pressure from the expanding dies 110 would not damage the protective substrate 410 or the dies). In some embodiments, this is beneficial if the dies' CTE is equal to or greater than the CTE of protective substrate 410 or substrate 410S. The adhesive's elasticity also absorbs the height non-uniformity of the top surfaces of dies 110 or the top surfaces of cavities 414. Also, to absorb the dies expansion, the adhesive may have a CTE equal to or greater than the dies' CTE. Exemplary adhesives are epoxy-based underfills.
  • FIG. 7 shows a similar embodiment, but the adhesive 610 covers the whole bottom surface of protective substrate 410S. The adhesive bonds the dies' (or encapsulant's) top surfaces to the top surfaces of the cavities. The adhesive's CTE can be equal to, or greater than, or less than, the dies' CTE.
  • FIGS. 8A-8C illustrate the use of separate bonding layers 810, 820 to directly bind the protective substrate 410 to interposer 120.1. In some embodiments, the bonding layers are silicon dioxide, but other materials can also be used (e.g. metals for eutectic bonding). Referring to FIG. 8A, the dies are attached to interposer 120.1 as in FIG. 3E; the dies are then optionally underfilled and/or encapsulated from above (in FIG. 8A, encapsulant 150 encapsulates and underfills the dies). Bonding layer 810, e.g. silicon dioxide or metal, is formed to cover the interposer and the dies (and the encapsulant if present), by any suitable techniques (e.g. sputtering).
  • Referring to FIG. 8B, the protective substrate 410 is provided with cavities as in FIG. 4C. Then a bonding layer 820, e.g. silicon dioxide or metal, is formed to cover the substrate surface by any suitable techniques (e.g. sputtering, or thermal oxidation if substrate 410S is silicon).
  • Referring to FIG. 8C, the interposer is joined to substrate 410 so that the layers 810, 820 physically contact each other. The structure is then heated to bond the layer 820 to layer 810 where the two layers meet, i.e. at legs 410L and at the cavities' top surfaces. In some embodiments however, before the bonding, the layer 820 is removed at the cavities' top surfaces not to bond the dies to the cavities' top surfaces.
  • Subsequent processing of the structures of FIGS. 6-8A (interposer thinning, possible dicing, etc.) can be as described above for other embodiments.
  • The process step sequences described above are not limiting; for example, the vias 224 can be formed after the interposer thinning. FIGS. 9A-9D illustrate an exemplary process. Interposer 120.1 is fabricated essentially as in FIG. 3E or 6 or 8A, but without vias 224 (the vias will be formed later). In particular, dielectric 324 is a flat layer on interposer substrate 120.1S. Then contact pads 910 are formed on substrate 120.1S at the locations of future vias 224. RDL 210.T is optionally fabricated on top of the interposer to connect the contact pads 910 to pads 120.1C.T on top of the interposer. (Alternatively, the pads 120.1C.T can be provided by pads 910.) Dies 110 are attached to pads 120.1C.T, and optionally underfilled and encapsulated. Bonding layer 810 (as shown) is optionally deposited as in FIG. 8A for bonding to the protective substrate (alternatively, the bonding can be by an adhesive as in FIG. 6 or 7, or by a direct bonding process as described above in relation to FIG. 5A).
  • Interposer 120.1 with the dies attached is then bonded to protective substrate 410 (FIG. 9B) as in any embodiment described above. Then the interposer is thinned (FIG. 9C). The dies will be protected by substrate 410 during subsequent steps. Substrate 410 can be thinned at any desired stage.
  • Then metallized vias 224 are formed from the interposer bottom. An exemplary process is as follows:
  • 1. Dielectric 920 (e.g. silicon dioxide or silicon nitride) is deposited (e.g. by sputtering or CVD) to cover the bottom surface of interposer substrate 120.1S.
  • 2. Vias (through-holes) are etched from the bottom through dielectric 920 and substrate 120.1S. This is a masked etch which stops on contact pads 910.
  • 3. Dielectric 930 (e.g. silicon dioxide or silicon nitride) is deposited (e.g. by sputtering or CVD) to cover the bottom surface of interposer substrate 120.1S and to line the vias. Dielectric 930 covers the contact pads 910 from the bottom.
  • 4. Dielectric 930 is etched to expose the contact pads 910. This can be a masked etch. Alternatively, a blanket anisotropic (vertical) etch can be used to remove the dielectric 930 from over at least a portion of each contact pad 910 while leaving the dielectric on the via sidewalls. The vertical etch may or may not remove dielectric 930 outside the vias.
  • 5. A conductive material 224M (e.g. metal) is formed in the vias, possibly by the same techniques as described above (e.g. copper electroplating). The conductive material is not present outside the vias (e.g. it can be polished away by CMP). The conductive material may fill the vias or just line the via surfaces. The conductive material in each via physically contacts the corresponding pad 910.
  • Subsequent processing steps can be as described above in connection with FIGS. 5C-5E.3. In particular, the bottom RDL 210.B (FIG. 5C) and connections 140.2 can be formed as described above. The structure can be diced if desired (FIG. 5D), and attached to another structure (e.g. PWS 120.2 in FIG. 5E.1).
  • Vias 224 are optional, and further the substrate 120.1 can be any wiring substrate, such as shown at 120 in FIG. 10. This figure illustrates an embodiment using an adhesive 610 to bond the protective substrate 410 to WS 120 at legs 410L and at the cavity top surfaces, but any other bonding method described above can be used. No underfill or other encapsulant is shown, but underfill with or without encapsulation of the entire die can be present.
  • The techniques described above in connection with FIGS. 5A-10 can be used to attach any number of separate protective substrates 410 to the same interposer 120.1 or WS 120; different protective substrates 410 can be attached to the same side of a substrate 120.1 or 120, with different dies in different cavities of the same or different protective substrates 410. Other protective substrates 410 can be attached to the opposite side of substrate 120.1 or 120. Some of the dies may have no protective substrate 410 to protect them. Each substrate 120.1S or 410S can be a wafer, and the two substrates can be of the same size in a given assembly 504; but different sizes are also possible in the same assembly.
  • The dies can also be stacked one above another in the same cavity (see FIG. 11 showing the structure at the same fabrication stage as FIG. 6), with only the top die of each stack physically contacting the corresponding cavity's top surface. The dies in each stack may have their respective circuits interconnected through their contact pads 1110C and respective connections 140 (which can be of any type described above). In FIG. 11, substrates 120.1S, 410S are bonded together by adhesive 610 on legs 410L as in FIG. 6, but the other bonding methods described above can also be used. Stacked dies can also be used with other variations described above, e.g. when the protective substrate is bonded directly to the PWS.
  • In some embodiments, substrate 410S has circuitry, possibly connected to the circuitry in the dies and/or the interposer 120.1S or the PWS. See FIG. 12, showing the top dies connected to substrate 410S by structures 1210; each structure 1210 includes a contact pad in substrate 410S, a corresponding contact pad on a top die 110, and a connection (e.g. solder or any other type described above) bonding the two contact pads to each other. In the example of FIG. 12, encapsulant 150 underfills and completely surrounds each die, contacting the cavities' top surfaces. As noted above, encapsulation and/or underfilling are optional.
  • The invention is not limited to the embodiments described above. For example, the vias 224 can be formed after the RDLs, and can be etched through one or both of the RDLs.
  • Some embodiments provide a manufacture comprising:
  • a first substrate (e.g. 120.1 or 120) comprising one or more first contact pads (e.g. the top pads 120.1C.T);
  • one or more dies attached to the first substrate, each die comprising a semiconductor integrated circuit which comprises one or more contact pads each of which is attached to a respective first contact pad;
  • a second substrate (e.g. 410 or 410S) comprising one or more cavities, the second substrate being attached to the first substrate, wherein at least part of each die is located in a corresponding cavity in the second substrate, the second substrate comprising a surface area (e.g. a surface of legs 410L) which lies outside of the cavities and is attached to the first substrate;
  • wherein at least at some temperature at which the structure is electrically operable, at least one die satisfies one or both of conditions (A) and (B):
  • (A) the die physically contacts a surface of the corresponding cavity;
  • (B) the die is separated from the surface of the corresponding cavity by solid material (e.g. an encapsulant or a bonding layer) which physically contacts the die and the surface of the corresponding cavity.
  • In some embodiments, in a side view in which each cavity is in a bottom surface of the second substrate (e.g. as in FIG. 5C or 5E.1), said surface area of the second substrate laterally surrounds each cavity (e.g. as in FIG. 5E.2).
  • In some embodiments, the at least one die is attached to the surface of the corresponding cavity.
  • In some embodiments, the at least one die is not attached to the surface of the corresponding cavity.
  • In some embodiments, the one or more first contact pads are located at a first side of the first substrate;
  • the first substrate comprises one or more second contact pads at a second side opposite to the first side (e.g. contact pads 120.1C.B at the interposer bottom); and
  • the first substrate comprises one or more electrically conductive paths passing through the first substrate (e.g. metallized vias 224) and electrically connecting at least one first contact pad to at least one second contact pad.
  • In some embodiments, at least one of the conditions (A) and (B) is satisfied at room temperature.
  • In some embodiments, the at least one die is under pressure from the second substrate.
  • In some embodiments, the pressure does not exceed 200 MPa at room temperature. In some embodiments, the pressure is greater than the atmospheric pressure (1 bar, i.e. 105 Pa), and can be in the range from 1 bar to 200 MPa or any sub-range of this range. The pressure can also be above or below this range.
  • Some embodiments provide a method for fabricating an electrically functioning manufacture, the method comprising:
  • obtaining a first substrate (e.g. 120.1) comprising a first side and one or more first contact pads at the first side;
  • attaching one or more dies to the first substrate, each die comprising a semiconductor integrated circuit which comprises one or more contact pads each of which is attached to a respective first contact pad;
  • obtaining a second substrate (e.g. 410) comprising one or more cavities;
  • attaching the second substrate to the first substrate, with at least part of each die being located in a corresponding cavity in the second substrate, the second substrate comprising a surface area (e.g. bottom areal of legs 410L) which lies outside of the cavities and is attached to the first substrate;
  • wherein at least at some temperature at which the structure is electrically operable, at least one die satisfies one or both of conditions (A) and (B):
  • (A) the die physically contacts a surface of the corresponding cavity;
  • (B) the die is separated from the surface of the corresponding cavity by solid material which physically contacts the die and the surface of the corresponding cavity.
  • In some embodiments, in a side view in which each cavity is in a bottom surface of the second substrate, said surface area of the second substrate laterally surrounds each cavity.
  • In some embodiments, the at least one die is attached to the surface of the corresponding cavity.
  • In some embodiments, the at least one die is not attached to the surface of the corresponding cavity.
  • In some embodiments, the one or more first contact pads are located at a first side of the first substrate;
  • the first substrate comprises one or more second contact pads at a second side opposite to the first side; and
  • the first substrate comprises one or more electrically conductive paths passing through the first substrate and electrically connecting at least one first contact pad to at least one second contact pad.
  • In some embodiments, at least one of the conditions (A) and (B) is satisfied at room temperature.
  • In some embodiments, the at least one die is under pressure from the second substrate when the first substrate is attached to the second substrate.
  • In some embodiments, the pressure does not exceed 200 MPa at room temperature.
  • In some embodiments, the one or more dies are a plurality of dies, and the method further comprises polishing a solid surface at a first side of the dies before attaching the first substrate to the second substrate, the first side of the dies being a side opposite to each die's one or more contact pads, the solid surface being a surface of the dies or of an encapsulant formed on the dies.
  • In some embodiments, the solid surface is a surface of the encapsulant which comprises an epoxy.
  • Some embodiments provide a manufacture comprising:
  • a first substrate comprising one or more first contact pads;
  • one or more dies attached to the first substrate, each die comprising a semiconductor integrated circuit which comprises one or more contact pads each of which is attached to a respective first contact pad;
  • a second substrate comprising one or more cavities, the second substrate being attached to the first substrate, wherein at least part of each die is located in a corresponding cavity in the second substrate, the second substrate comprising a surface area which lies outside of the cavities and is attached to the first substrate;
  • wherein at least at some temperature at which the structure is electrically operable, at least one die is under pressure from the second substrate.
  • In some embodiments, the pressure does not exceed 200 MPa at room temperature.
  • In some embodiments, in a side view in which each cavity is in a bottom surface of the second substrate, said surface area of the second substrate laterally surrounds each cavity.
  • In some embodiments, the at least one die is attached to the surface of the corresponding cavity.
  • In some embodiments, wherein the at least one die is not attached to the surface of the corresponding cavity.
  • In some embodiments, wherein the one or more first contact pads are located at a first side of the first substrate;
  • the first substrate comprises one or more second contact pads at a second side opposite to the first side; and
  • the first substrate comprises one or more electrically conductive paths passing through the first substrate and electrically connecting at least one first contact pad to at least one second contact pad.
  • Other embodiments and variations are within the scope of the invention, as defined by the appended claims.

Claims (21)

  1. 1. A manufacture comprising:
    (a) a structure comprising:
    a first substrate comprising one or more first contact pads; and
    one or more dies attached to the first substrate, each die comprising a semiconductor integrated circuit which comprises one or more contact pads each of which is attached to a respective first contact pad;
    wherein the first structure comprises a region of a first material;
    (b) a second substrate comprising one or more cavities in the bottom, an entire bottom surface of the second substrate being made of a second material, the second substrate being attached to said structure, wherein at least part of each die is located in a corresponding cavity in the second substrate;
    wherein said region underlies the second substrate, and in top view said region reaches an outer lateral boundary of the second substrate and also reaches at least one of the one or more dies;
    wherein the first material is or is not the same as the second material and has substantially the same coefficient of thermal expansion (CTE) as the second material;
    wherein said region is directly bonded to the bottom surface of the second substrate to physically contact the bottom surface of the second substrate;
    wherein at least a first cavity of the one or more cavities comprises an encapsulant which fills the first cavity over each die at least partially located in the first cavity but a top surface of the encapsulant is not attached to a top surface of the first cavity.
  2. 2. The manufacture of claim 1 wherein the bottom surface of the second substrate comprises a surface area attached to said structure, and said surface area laterally surrounds each cavity.
  3. 3. The manufacture of claim 32 wherein the at least one die is attached to the surface of the corresponding cavity.
  4. 4. The manufacture of claim 32 wherein the at least one die is not attached to the surface of the corresponding cavity.
  5. 5. The manufacture of claim 1 wherein:
    the first substrate comprises one or more second contact pads at a bottom side of the first substrate; and
    the first substrate comprises one or more electrically conductive paths passing through the first substrate and electrically connecting at least one first contact pad to at least one second contact pad.
  6. 6. The manufacture of claim 32 wherein at least one of the conditions (A) and (B) is satisfied at room temperature.
  7. 7-24. (canceled)
  8. 25. The manufacture of claim 1 wherein for at least one cavity, each die in the cavity has substantially the same CTE as the first and second materials.
  9. 26. The manufacture of claim 1 wherein the entire second substrate is made of the second material.
  10. 27. The manufacture of claim 1 wherein at least one of the first and second materials is semiconductor.
  11. 28. The manufacture of claim 1 further comprising an encapsulant covering and physically contacting each die, the encapsulant being a molding compound, wherein none of the first and second materials is a molding compound.
  12. 29. The manufacture of claim 1 wherein the first region is part of the first substrate.
  13. 30. The manufacture of claim 1 wherein the second substrate has a first thickness except at a location of each cavity, the second substrate being thinner at the location of each cavity than the first thickness.
  14. 31. The manufacture of claim 1 wherein the second substrate is thinner over each cavity than at a location not overlying any one of the one or more cavities.
  15. 32. The manufacture of claim 1 wherein at least at some temperature at which the structure is electrically operable, at least one die satisfies one or both of conditions (A) and (B):
    (A) the die physically contacts a surface of the corresponding cavity;
    (B) the die is separated from the surface of the corresponding cavity by solid material which physically contacts the die and the surface of the corresponding cavity.
  16. 33. A manufacture comprising:
    (a) a structure comprising:
    a first substrate comprising one or more first contact pads; and
    one or more dies attached to the first substrate, each die comprising a semiconductor integrated circuit which comprises one or more contact pads each of which is attached to a respective first contact pad;
    wherein the first structure comprises a region of a predefined material;
    (b) a second substrate comprising one or more cavities in the bottom, an entire bottom surface of the second substrate being made of the predefined material, the second substrate being attached to said structure, wherein at least part of each die is located in a corresponding cavity in the second substrate;
    wherein said region underlies the second substrate, and in top view said region reaches an outer lateral boundary of the second substrate and also reaches at least one of the one or more dies;
    wherein said region is directly bonded to the bottom surface of the second substrate to physically contact the bottom surface of the second substrate;
    wherein in at least a first cavity of the one or more cavities, for at least one die at least partially located in the first cavity, the die is attached to a top surface of the first cavity without a molding compound between the die and the top surface of the first cavity.
  17. 34. The manufacture of claim 33 wherein at least at some temperature at which the structure is electrically operable, at least one die satisfies one or both of conditions (A) and (B):
    (A) the die physically contacts a surface of the corresponding cavity;
    (B) the die is separated from the surface of the corresponding cavity by solid material which physically contacts the die and the surface of the corresponding cavity.
  18. 35. The manufacture of claim 33 wherein said region is part of the first substrate.
  19. 36. A manufacture comprising:
    (a) a first substrate comprising:
    a first body made of a first material;
    one or more conductive vias each of which passes through the first body between a top surface and a bottom surface of the first body;
    a redistribution layer comprising one or more conductive lines and dielectric which is not the first material; and
    one or more first contact pads at a top of the redistribution layer and spaced from the first body, the one or more conductive lines interconnecting one or more of the one or more conductive vias and one or more of the one or more first contact pads;
    (b) one or more dies attached to the first substrate, each die comprising a semiconductor integrated circuit which comprises one or more contact pads each of which is attached to a respective first contact pad;
    (c) a second substrate comprising a second body made from a second material which is or is not the same as the first material, the second substrate comprising one or more cavities in the bottom, each cavity extending into the second body, the second body being thinner above each cavity than at a location not overlying any one of the one or more cavities, the second substrate comprising a bottom surface comprising an area which lies outside of the one or more cavities and is directly bonded to a top surface of the redistribution layer to physically contact the top surface of the redistribution layer;
    wherein the first material has substantially the same coefficient of thermal expansion (CTE) as the second material;
    wherein in at least a first cavity of the one or more cavities, for at least one die at least partially located in the first cavity, the die is attached to a top surface of the first cavity without a molding compound between the die and the top surface of the first cavity.
  20. 37. The manufacture of claim 36 wherein the first material is the same as the second material.
  21. 38. The manufacture of claim 36 wherein at least one of the first and second materials is semiconductor.
US14214365 2014-03-12 2014-03-14 Integrated circuits protected by substrates with cavities, and methods of manufacture Abandoned US20150262902A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US201461952066 true 2014-03-12 2014-03-12
US14214365 US20150262902A1 (en) 2014-03-12 2014-03-14 Integrated circuits protected by substrates with cavities, and methods of manufacture

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US14214365 US20150262902A1 (en) 2014-03-12 2014-03-14 Integrated circuits protected by substrates with cavities, and methods of manufacture
US14288064 US9355997B2 (en) 2014-03-12 2014-05-27 Integrated circuit assemblies with reinforcement frames, and methods of manufacture
KR20167028245A KR20160132093A (en) 2014-03-12 2015-03-10 Integrated circuits protected by substrates with cavities, and methods of manufacture
PCT/US2015/019609 WO2015138393A1 (en) 2014-03-12 2015-03-10 Integrated circuits protected by substrates with cavities, and methods of manufacture
US15165837 US9887166B2 (en) 2014-03-12 2016-05-26 Integrated circuit assemblies with reinforcement frames, and methods of manufacture
US15265148 US9899281B2 (en) 2014-03-12 2016-09-14 Integrated circuits protected by substrates with cavities, and methods of manufacture
US15865842 US20180130717A1 (en) 2014-03-12 2018-01-09 Integrated circuits protected by substrates with cavities, and methods of manufacture

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US14288064 Continuation-In-Part US9355997B2 (en) 2014-03-12 2014-05-27 Integrated circuit assemblies with reinforcement frames, and methods of manufacture
US15265148 Continuation US9899281B2 (en) 2014-03-12 2016-09-14 Integrated circuits protected by substrates with cavities, and methods of manufacture

Publications (1)

Publication Number Publication Date
US20150262902A1 true true US20150262902A1 (en) 2015-09-17

Family

ID=54069679

Family Applications (5)

Application Number Title Priority Date Filing Date
US14214365 Abandoned US20150262902A1 (en) 2014-03-12 2014-03-14 Integrated circuits protected by substrates with cavities, and methods of manufacture
US14558462 Active US9324626B2 (en) 2014-03-12 2014-12-02 Interposers with circuit modules encapsulated by moldable material in a cavity, and methods of fabrication
US15005220 Active US9691696B2 (en) 2014-03-12 2016-01-25 Interposers with circuit modules encapsulated by moldable material in a cavity, and methods of fabrication
US15265148 Active US9899281B2 (en) 2014-03-12 2016-09-14 Integrated circuits protected by substrates with cavities, and methods of manufacture
US15865842 Pending US20180130717A1 (en) 2014-03-12 2018-01-09 Integrated circuits protected by substrates with cavities, and methods of manufacture

Family Applications After (4)

Application Number Title Priority Date Filing Date
US14558462 Active US9324626B2 (en) 2014-03-12 2014-12-02 Interposers with circuit modules encapsulated by moldable material in a cavity, and methods of fabrication
US15005220 Active US9691696B2 (en) 2014-03-12 2016-01-25 Interposers with circuit modules encapsulated by moldable material in a cavity, and methods of fabrication
US15265148 Active US9899281B2 (en) 2014-03-12 2016-09-14 Integrated circuits protected by substrates with cavities, and methods of manufacture
US15865842 Pending US20180130717A1 (en) 2014-03-12 2018-01-09 Integrated circuits protected by substrates with cavities, and methods of manufacture

Country Status (3)

Country Link
US (5) US20150262902A1 (en)
KR (1) KR20160132093A (en)
WO (1) WO2015138393A1 (en)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160049361A1 (en) * 2014-05-02 2016-02-18 Invensas Corporation Making electrical components in handle wafers of integrated circuit packages
US9324626B2 (en) 2014-03-12 2016-04-26 Invensas Corporation Interposers with circuit modules encapsulated by moldable material in a cavity, and methods of fabrication
US9355997B2 (en) 2014-03-12 2016-05-31 Invensas Corporation Integrated circuit assemblies with reinforcement frames, and methods of manufacture
US20160190034A1 (en) * 2014-03-31 2016-06-30 Fuji Electric Co., Ltd. Power conversion device
US20160247742A1 (en) * 2015-02-19 2016-08-25 Micron Technology, Inc. Apparatuses and methods for semiconductor die heat dissipation
US20160293581A1 (en) * 2015-03-30 2016-10-06 Mediatek Inc. Semiconductor package assembly with embedded ipd
US9478504B1 (en) 2015-06-19 2016-10-25 Invensas Corporation Microelectronic assemblies with cavities, and methods of fabrication
US9536862B2 (en) 2014-07-10 2017-01-03 Invensas Corporation Microelectronic assemblies with integrated circuits and interposers with cavities, and methods of manufacture
US9666514B2 (en) * 2015-04-14 2017-05-30 Invensas Corporation High performance compliant substrate
WO2017099931A1 (en) * 2015-12-10 2017-06-15 Intel Corporation Reduced-height memory system and method
US9741649B2 (en) 2014-06-04 2017-08-22 Invensas Corporation Integrated interposer solutions for 2D and 3D IC packaging
EP3240027A1 (en) * 2016-04-25 2017-11-01 Technische Hochschule Ingolstadt Semiconductor package
US9922845B1 (en) * 2016-11-03 2018-03-20 Micron Technology, Inc. Semiconductor package and fabrication method thereof

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160004106A (en) * 2014-07-02 2016-01-12 삼성전기주식회사 Package structure and manufacturing method thereof
US9627285B2 (en) * 2014-07-25 2017-04-18 Dyi-chung Hu Package substrate
CN105405835A (en) * 2014-09-10 2016-03-16 恒劲科技股份有限公司 Interposer substrate and method of fabricating the same
US20160366762A1 (en) * 2014-12-15 2016-12-15 Bridge Semiconductor Corporation Wiring board with dual stiffeners and dual routing circuitries integrated together and method of making the same
US10056338B2 (en) * 2015-10-27 2018-08-21 Micron Technology, Inc. Methods of forming semiconductor packages including molding semiconductor chips of the semiconductor packages
US9818637B2 (en) * 2015-12-29 2017-11-14 Globalfoundries Inc. Device layer transfer with a preserved handle wafer section
US9984998B2 (en) * 2016-01-06 2018-05-29 Taiwan Semiconductor Manufacturing Company, Ltd. Devices employing thermal and mechanical enhanced layers and methods of forming same
US20170287870A1 (en) * 2016-04-01 2017-10-05 Powertech Technology Inc. Stacked chip package structure and manufacturing method thereof
KR20170142712A (en) * 2016-06-20 2017-12-28 삼성전기주식회사 Fan-out semiconductor package

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100084761A1 (en) * 2008-10-06 2010-04-08 Masatoshi Shinagawa Semiconductor device and fabrication method of the same
US20100230797A1 (en) * 2003-02-03 2010-09-16 Hirokazu Honda Warp-suppressed semiconductor device
US20110080713A1 (en) * 2009-10-06 2011-04-07 Shinko Electric Industries Co., Ltd. Interposer mounted wiring board and electronic component device
US20120101540A1 (en) * 2010-10-26 2012-04-26 Medtronic, Inc. Wafer-scale package including power source
US20130082399A1 (en) * 2011-10-04 2013-04-04 Won-keun Kim Semiconductor package and method of manufacturing the same
US20140134803A1 (en) * 2012-11-15 2014-05-15 Michael G. Kelly Method And System For A Semiconductor Device Package With A Die-To-Die First Bond

Family Cites Families (152)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5567653A (en) 1994-09-14 1996-10-22 International Business Machines Corporation Process for aligning etch masks on an integrated circuit surface using electromagnetic energy
US5701233A (en) 1995-01-23 1997-12-23 Irvine Sensors Corporation Stackable modules and multimodular assemblies
US6008536A (en) 1997-06-23 1999-12-28 Lsi Logic Corporation Grid array device package including advanced heat transfer mechanisms
US6157076A (en) 1997-06-30 2000-12-05 Intersil Corporation Hermetic thin pack semiconductor device
US6624505B2 (en) 1998-02-06 2003-09-23 Shellcase, Ltd. Packaged integrated circuits and methods of producing thereof
JP3630551B2 (en) 1998-04-02 2005-03-16 株式会社東芝 The semiconductor memory device and manufacturing method thereof
US6613672B1 (en) 1999-07-29 2003-09-02 Mosel Vitelic, Inc. Apparatus and process of fabricating a trench capacitor
US6322903B1 (en) 1999-12-06 2001-11-27 Tru-Si Technologies, Inc. Package of integrated circuits and vertical integration
CN1222024C (en) 1999-12-10 2005-10-05 壳箱有限公司 Method for producing packaged integrated circuit devices and packaged integrated circuit devices produced thereby
US6251796B1 (en) 2000-02-24 2001-06-26 Conexant Systems, Inc. Method for fabrication of ceramic tantalum nitride and improved structures based thereon
KR20010091916A (en) * 2000-03-17 2001-10-23 가나이 쓰토무 A semiconductor device and a method of manufacturing the same
US6384473B1 (en) 2000-05-16 2002-05-07 Sandia Corporation Microelectronic device package with an integral window
US6492726B1 (en) 2000-09-22 2002-12-10 Chartered Semiconductor Manufacturing Ltd. Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnection
US6717254B2 (en) 2001-02-22 2004-04-06 Tru-Si Technologies, Inc. Devices having substrates with opening passing through the substrates and conductors in the openings, and methods of manufacture
US6451650B1 (en) 2001-04-20 2002-09-17 Taiwan Semiconductor Manufacturing Company Low thermal budget method for forming MIM capacitor
US7061102B2 (en) 2001-06-11 2006-06-13 Xilinx, Inc. High performance flipchip package that incorporates heat removal with minimal thermal mismatch
US6856007B2 (en) 2001-08-28 2005-02-15 Tessera, Inc. High-frequency chip packages
US6787916B2 (en) 2001-09-13 2004-09-07 Tru-Si Technologies, Inc. Structures having a substrate with a cavity and having an integrated circuit bonded to a contact pad located in the cavity
US6620701B2 (en) 2001-10-12 2003-09-16 Infineon Technologies Ag Method of fabricating a metal-insulator-metal (MIM) capacitor
US7633765B1 (en) 2004-03-23 2009-12-15 Amkor Technology, Inc. Semiconductor package including a top-surface metal layer for implementing circuit features
JP2004014714A (en) 2002-06-05 2004-01-15 Mitsubishi Electric Corp Method for manufacturing capacitor
GB0221439D0 (en) 2002-09-16 2002-10-23 Enpar Technologies Inc Ion-exchange/electrochemical treatment of ammonia in waste-water
JP4056854B2 (en) 2002-11-05 2008-03-05 新光電気工業株式会社 A method of manufacturing a semiconductor device
US6919508B2 (en) 2002-11-08 2005-07-19 Flipchip International, Llc Build-up structures with multi-angle vias for chip to chip interconnects and optical bussing
US7400036B2 (en) 2002-12-16 2008-07-15 Avago Technologies General Ip Pte Ltd Semiconductor chip package with a package substrate and a lid cover
US20040174682A1 (en) 2003-03-04 2004-09-09 Siliconware Precision Industries, Ltd. Semiconductor package with heat sink
US6946325B2 (en) 2003-03-14 2005-09-20 Micron Technology, Inc. Methods for packaging microelectronic devices
JP2004281830A (en) 2003-03-17 2004-10-07 Shinko Electric Ind Co Ltd Substrate for semiconductor device, method of manufacturing substrate, and semiconductor device
US7102217B2 (en) 2003-04-09 2006-09-05 Micron Technology, Inc. Interposer substrates with reinforced interconnect slots, and semiconductor die packages including same
US7012326B1 (en) 2003-08-25 2006-03-14 Xilinx, Inc. Lid and method of employing a lid on an integrated circuit
KR100537892B1 (en) 2003-08-26 2005-12-21 삼성전자주식회사 Chip stack package and manufacturing method thereof
US7050304B2 (en) 2003-08-28 2006-05-23 Phoenix Precision Technology Corporation Heat sink structure with embedded electronic components for semiconductor package
US7031162B2 (en) 2003-09-26 2006-04-18 International Business Machines Corporation Method and structure for cooling a dual chip module with one high power chip
US7183643B2 (en) 2003-11-04 2007-02-27 Tessera, Inc. Stacked packages and systems incorporating the same
US7049170B2 (en) 2003-12-17 2006-05-23 Tru-Si Technologies, Inc. Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities
US7115988B1 (en) 2004-01-21 2006-10-03 Altera Corporation Bypass capacitor embedded flip chip package lid and stiffener
KR20050076742A (en) 2004-01-22 2005-07-27 마츠시타 덴끼 산교 가부시키가이샤 Fabrication method for optical transmission channel board, optical transmission channel board, board with built-in optical transmission channel, fabrication method for board with built-in optical transmission channel, and data processing apparatus
JP4441328B2 (en) 2004-05-25 2010-03-31 株式会社ルネサステクノロジ Semiconductor device and manufacturing method thereof
JP3972209B2 (en) 2004-05-26 2007-09-05 セイコーエプソン株式会社 Semiconductor device and manufacturing method thereof, the circuit board and electronic equipment
US7786591B2 (en) 2004-09-29 2010-08-31 Broadcom Corporation Die down ball grid array package
US6947275B1 (en) 2004-10-18 2005-09-20 International Business Machines Corporation Fin capacitor
CN100485910C (en) 2004-12-02 2009-05-06 株式会社村田制作所 Electronic component and its manufacturing method
KR100594952B1 (en) 2005-02-04 2006-06-22 삼성전자주식회사 Wafer level packaging cap and fablication method thereof
WO2006124597B1 (en) 2005-05-12 2007-06-14 Ron B Foster Infinitely stackable interconnect device and method
US7215032B2 (en) 2005-06-14 2007-05-08 Cubic Wafer, Inc. Triaxial through-chip connection
JP2007042719A (en) 2005-08-01 2007-02-15 Nec Electronics Corp Semiconductor device
JP4889974B2 (en) 2005-08-01 2012-03-07 新光電気工業株式会社 Electronic component mounting structure and a manufacturing method thereof
US7906803B2 (en) 2005-12-06 2011-03-15 Canon Kabushiki Kaisha Nano-wire capacitor and circuit device therewith
US7344954B2 (en) 2006-01-03 2008-03-18 United Microelectonics Corp. Method of manufacturing a capacitor deep trench and of etching a deep trench opening
US7560761B2 (en) 2006-01-09 2009-07-14 International Business Machines Corporation Semiconductor structure including trench capacitor and trench resistor
US7977579B2 (en) 2006-03-30 2011-07-12 Stats Chippac Ltd. Multiple flip-chip integrated circuit package system
US7390700B2 (en) 2006-04-07 2008-06-24 Texas Instruments Incorporated Packaged system of semiconductor chips having a semiconductor interposer
US7510928B2 (en) 2006-05-05 2009-03-31 Tru-Si Technologies, Inc. Dielectric trenches, nickel/tantalum oxide structures, and chemical mechanical polishing techniques
US7513035B2 (en) 2006-06-07 2009-04-07 Advanced Micro Devices, Inc. Method of integrated circuit packaging
JP5107539B2 (en) 2006-08-03 2012-12-26 新光電気工業株式会社 The method of manufacturing a semiconductor device and a semiconductor device
US8102039B2 (en) 2006-08-11 2012-01-24 Sanyo Semiconductor Co., Ltd. Semiconductor device and manufacturing method thereof
US8397013B1 (en) 2006-10-05 2013-03-12 Google Inc. Hybrid memory module
US7901989B2 (en) 2006-10-10 2011-03-08 Tessera, Inc. Reconstituted wafer level stacking
US7550857B1 (en) 2006-11-16 2009-06-23 Amkor Technology, Inc. Stacked redistribution layer (RDL) die assembly package
US20080128897A1 (en) 2006-12-05 2008-06-05 Tong Wa Chao Heat spreader for a multi-chip package
US7670921B2 (en) 2006-12-28 2010-03-02 International Business Machines Corporation Structure and method for self aligned vertical plate capacitor
US7800916B2 (en) * 2007-04-09 2010-09-21 Endicott Interconnect Technologies, Inc. Circuitized substrate with internal stacked semiconductor chips, method of making same, electrical assembly utilizing same and information handling system utilizing same
US8039309B2 (en) 2007-05-10 2011-10-18 Texas Instruments Incorporated Systems and methods for post-circuitization assembly
KR100909322B1 (en) 2007-07-02 2009-07-24 주식회사 네패스 An ultra-thin semiconductor package and a method of manufacturing the same
US20090057884A1 (en) * 2007-08-29 2009-03-05 Seah Sun Too Multi-Chip Package
KR101572600B1 (en) 2007-10-10 2015-11-27 테세라, 인코포레이티드 Robust multi-layer wiring elements and assemblies with embedded microelectronic elements
KR20090056044A (en) * 2007-11-29 2009-06-03 삼성전자주식회사 Semiconductor device package and method of fabricating the same
KR20150068495A (en) 2007-11-30 2015-06-19 스카이워크스 솔루션즈, 인코포레이티드 Wafer level packaging using flip chip mounting
US7928548B2 (en) 2008-01-07 2011-04-19 International Business Machines Corporation Silicon heat spreader mounted in-plane with a heat source and method therefor
US8072082B2 (en) 2008-04-24 2011-12-06 Micron Technology, Inc. Pre-encapsulated cavity interposer
US8008764B2 (en) 2008-04-28 2011-08-30 International Business Machines Corporation Bridges for interconnecting interposers in multi-chip integrated circuits
US7863096B2 (en) 2008-07-17 2011-01-04 Fairchild Semiconductor Corporation Embedded die package and process flow using a pre-molded carrier
JP2010034403A (en) 2008-07-30 2010-02-12 Shinko Electric Ind Co Ltd Wiring substrate and electronic component device
US8101494B2 (en) 2008-08-14 2012-01-24 International Business Machines Corporation Structure, design structure and method of manufacturing a structure having VIAS and high density capacitors
US8257985B2 (en) 2008-09-25 2012-09-04 Texas Instruments Incorporated MEMS device and fabrication method
KR20100037300A (en) 2008-10-01 2010-04-09 삼성전자주식회사 Method of forming semiconductor device having embedded interposer
US8071470B2 (en) 2008-10-23 2011-12-06 Carsem (M) Sdn. Bhd. Wafer level package using stud bump coated with solder
KR101015704B1 (en) 2008-12-01 2011-02-22 삼성전기주식회사 Chip embedded printed circuit board and manufacturing method thereof
US8354304B2 (en) 2008-12-05 2013-01-15 Stats Chippac, Ltd. Semiconductor device and method of forming conductive posts embedded in photosensitive encapsulant
US7858441B2 (en) 2008-12-08 2010-12-28 Stats Chippac, Ltd. Semiconductor package with semiconductor core structure and method of forming same
JP5308145B2 (en) 2008-12-19 2013-10-09 ルネサスエレクトロニクス株式会社 Semiconductor device
US8343806B2 (en) 2009-03-05 2013-01-01 Raytheon Company Hermetic packaging of integrated circuit components
US7989270B2 (en) 2009-03-13 2011-08-02 Stats Chippac, Ltd. Semiconductor device and method of forming three-dimensional vertically oriented integrated capacitors
US8216887B2 (en) 2009-05-04 2012-07-10 Advanced Micro Devices, Inc. Semiconductor chip package with stiffener frame and configured lid
EP2273545B1 (en) 2009-07-08 2016-08-31 Imec Method for insertion bonding and kit of parts for use in said method
US8143097B2 (en) 2009-09-23 2012-03-27 Stats Chippac, Ltd. Semiconductor device and method of forming open cavity in TSV interposer to contain semiconductor die in WLCSMP
US8531012B2 (en) 2009-10-23 2013-09-10 Stats Chippac, Ltd. Semiconductor device and method of forming a shielding layer over a semiconductor die disposed in a cavity of an interconnect structure and grounded through the die TSV
JP5295932B2 (en) 2009-11-02 2013-09-18 新光電気工業株式会社 Semiconductor package and method evaluation, and manufacturing method thereof
US8519537B2 (en) 2010-02-26 2013-08-27 Taiwan Semiconductor Manufacturing Company, Ltd. 3D semiconductor package interposer with die cavity
US8378480B2 (en) 2010-03-04 2013-02-19 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy wafers in 3DIC package assemblies
US8541886B2 (en) 2010-03-09 2013-09-24 Stats Chippac Ltd. Integrated circuit packaging system with via and method of manufacture thereof
US8183696B2 (en) 2010-03-31 2012-05-22 Infineon Technologies Ag Packaged semiconductor device with encapsulant embedding semiconductor chip that includes contact pads
FR2960339B1 (en) 2010-05-18 2012-05-18 Commissariat Energie Atomique Process for the realization of elements is provided with smart son of insertion grooves
US8349653B2 (en) 2010-06-02 2013-01-08 Maxim Integrated Products, Inc. Use of device assembly for a generalization of three-dimensional metal interconnect technologies
KR101394205B1 (en) 2010-06-09 2014-05-14 에스케이하이닉스 주식회사 Semiconductor packag
US8426961B2 (en) 2010-06-25 2013-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded 3D interposer structure
US20120001339A1 (en) 2010-06-30 2012-01-05 Pramod Malatkar Bumpless build-up layer package design with an interposer
KR101129909B1 (en) 2010-07-20 2012-03-23 주식회사 하이닉스반도체 Pillar type capacitor of semiconductor device and method for forming the same
US8847376B2 (en) 2010-07-23 2014-09-30 Tessera, Inc. Microelectronic elements with post-assembly planarization
US8598695B2 (en) 2010-07-23 2013-12-03 Tessera, Inc. Active chip on carrier or laminated chip having microelectronic element embedded therein
US20120049332A1 (en) 2010-08-25 2012-03-01 Advanced Semiconductor Engineering, Inc. Semiconductor package and method for manufacturing the same
US8617926B2 (en) 2010-09-09 2013-12-31 Advanced Micro Devices, Inc. Semiconductor chip device with polymeric filler trench
US9343436B2 (en) 2010-09-09 2016-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked package and method of manufacturing the same
US8830689B2 (en) 2010-09-16 2014-09-09 Samsung Electro-Mechanics Co., Ltd. Interposer-embedded printed circuit board
US9856132B2 (en) 2010-09-18 2018-01-02 Fairchild Semiconductor Corporation Sealed packaging for microelectromechanical systems
WO2012048137A3 (en) 2010-10-06 2012-07-12 The Charles Stark Draper Laboratory, Inc. Flexible circuits and methods for making the same
WO2012061633A3 (en) 2010-11-03 2013-03-21 Netlist, Inc. Method and apparatus for optimizing driver load in a memory package
US8525318B1 (en) 2010-11-10 2013-09-03 Amkor Technology, Inc. Semiconductor device and fabricating method thereof
US8502340B2 (en) 2010-12-09 2013-08-06 Tessera, Inc. High density three-dimensional integrated capacitors
US8575493B1 (en) 2011-02-24 2013-11-05 Maxim Integrated Products, Inc. Integrated circuit device having extended under ball metallization
US9018094B2 (en) 2011-03-07 2015-04-28 Invensas Corporation Substrates with through vias with conductive features for connection to integrated circuit elements, and methods for forming through vias in substrates
JP2012231096A (en) 2011-04-27 2012-11-22 Elpida Memory Inc Semiconductor device and manufacturing method of the same
JP2012256846A (en) 2011-05-16 2012-12-27 Elpida Memory Inc Manufacturing method of semiconductor device
WO2012169162A1 (en) 2011-06-06 2012-12-13 住友ベークライト株式会社 Reinforcing member, semiconductor package, semiconductor device, and fabrication method for semiconductor package
US8409923B2 (en) * 2011-06-15 2013-04-02 Stats Chippac Ltd. Integrated circuit packaging system with underfill and method of manufacture thereof
US8497558B2 (en) 2011-07-14 2013-07-30 Infineon Technologies Ag System and method for wafer level packaging
US9125333B2 (en) 2011-07-15 2015-09-01 Tessera, Inc. Electrical barrier layers
EP2555239A3 (en) 2011-08-04 2013-06-05 Sony Mobile Communications AB Thermal package with heat slug for die stacks
JP5396508B2 (en) 2011-08-05 2014-01-22 欣興電子股▲分▼有限公司 Package substrate and a manufacturing method thereof intervening layer is embedded
US8816404B2 (en) 2011-09-16 2014-08-26 Stats Chippac, Ltd. Semiconductor device and method of forming stacked semiconductor die and conductive interconnect structure through an encapsulant
US20130082383A1 (en) 2011-10-03 2013-04-04 Texas Instruments Incorporated Electronic assembly having mixed interface including tsv die
KR20130038602A (en) 2011-10-10 2013-04-18 삼성전자주식회사 Semiconductor package
US9287191B2 (en) 2011-10-12 2016-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device package and method
KR20130042936A (en) 2011-10-19 2013-04-29 에스케이하이닉스 주식회사 Chip carrier, semiconductor chip and semiconductor package using the same, and method of fabricating those
WO2013062533A1 (en) 2011-10-25 2013-05-02 Intel Corporation Interposer for hermetic sealing of sensor chips and for their integration with integrated circuit chips
US9153520B2 (en) 2011-11-14 2015-10-06 Micron Technology, Inc. Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods
US8518753B2 (en) 2011-11-15 2013-08-27 Taiwan Semiconductor Manufacturing Company, Ltd. Assembly method for three dimensional integrated circuit
US9627357B2 (en) 2011-12-02 2017-04-18 Intel Corporation Stacked memory allowing variance in device interconnects
US8975711B2 (en) 2011-12-08 2015-03-10 Infineon Technologies Ag Device including two power semiconductor chips and manufacturing thereof
US9548251B2 (en) 2012-01-12 2017-01-17 Broadcom Corporation Semiconductor interposer having a cavity for intra-interposer die
US8686570B2 (en) 2012-01-20 2014-04-01 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-dimensional integrated circuit structures and methods of forming the same
JP2013183120A (en) 2012-03-05 2013-09-12 Elpida Memory Inc Semiconductor device
US9000557B2 (en) 2012-03-17 2015-04-07 Zvi Or-Bach Semiconductor device and structure
US8557632B1 (en) 2012-04-09 2013-10-15 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US8872349B2 (en) 2012-09-11 2014-10-28 Intel Corporation Bridge interconnect with air gap in package assembly
US20140091461A1 (en) 2012-09-30 2014-04-03 Yuci Shen Die cap for use with flip chip package
US9040349B2 (en) 2012-11-15 2015-05-26 Amkor Technology, Inc. Method and system for a semiconductor device package with a die to interposer wafer first bond
US9136159B2 (en) 2012-11-15 2015-09-15 Amkor Technology, Inc. Method and system for a semiconductor for device package with a die-to-packaging substrate first bond
US9257355B2 (en) 2013-02-11 2016-02-09 The Charles Stark Draper Laboratory, Inc. Method for embedding a chipset having an intermediary interposer in high density electronic modules
US8778738B1 (en) 2013-02-19 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and packaging devices and methods
US20140246227A1 (en) 2013-03-01 2014-09-04 Bridge Semiconductor Corporation Method of making cavity substrate with built-in stiffener and cavity substrate manufactured thereby
US9704809B2 (en) 2013-03-05 2017-07-11 Maxim Integrated Products, Inc. Fan-out and heterogeneous packaging of electronic components
US9111930B2 (en) 2013-03-12 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Package on-package with cavity in interposer
KR20140130916A (en) * 2013-05-02 2014-11-12 삼성전자주식회사 Semiconductor Package Having a EMI shielding and heat dissipation function
JP6110734B2 (en) 2013-06-06 2017-04-05 ルネサスエレクトロニクス株式会社 Semiconductor device
US9685414B2 (en) 2013-06-26 2017-06-20 Intel Corporation Package assembly for embedded die and associated techniques and configurations
US20150262902A1 (en) 2014-03-12 2015-09-17 Invensas Corporation Integrated circuits protected by substrates with cavities, and methods of manufacture
US9355997B2 (en) 2014-03-12 2016-05-31 Invensas Corporation Integrated circuit assemblies with reinforcement frames, and methods of manufacture
US9165793B1 (en) 2014-05-02 2015-10-20 Invensas Corporation Making electrical components in handle wafers of integrated circuit packages
US9524883B2 (en) 2014-05-13 2016-12-20 Invensas Corporation Holding of interposers and other microelectronic workpieces in position during assembly and other processing
US9252127B1 (en) 2014-07-10 2016-02-02 Invensas Corporation Microelectronic assemblies with integrated circuits and interposers with cavities, and methods of manufacture

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100230797A1 (en) * 2003-02-03 2010-09-16 Hirokazu Honda Warp-suppressed semiconductor device
US20100084761A1 (en) * 2008-10-06 2010-04-08 Masatoshi Shinagawa Semiconductor device and fabrication method of the same
US20110080713A1 (en) * 2009-10-06 2011-04-07 Shinko Electric Industries Co., Ltd. Interposer mounted wiring board and electronic component device
US20120101540A1 (en) * 2010-10-26 2012-04-26 Medtronic, Inc. Wafer-scale package including power source
US20130082399A1 (en) * 2011-10-04 2013-04-04 Won-keun Kim Semiconductor package and method of manufacturing the same
US20140134803A1 (en) * 2012-11-15 2014-05-15 Michael G. Kelly Method And System For A Semiconductor Device Package With A Die-To-Die First Bond

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9691696B2 (en) 2014-03-12 2017-06-27 Invensas Corporation Interposers with circuit modules encapsulated by moldable material in a cavity, and methods of fabrication
US9324626B2 (en) 2014-03-12 2016-04-26 Invensas Corporation Interposers with circuit modules encapsulated by moldable material in a cavity, and methods of fabrication
US9355997B2 (en) 2014-03-12 2016-05-31 Invensas Corporation Integrated circuit assemblies with reinforcement frames, and methods of manufacture
US9887166B2 (en) 2014-03-12 2018-02-06 Invensas Corporation Integrated circuit assemblies with reinforcement frames, and methods of manufacture
US9899281B2 (en) 2014-03-12 2018-02-20 Invensas Corporation Integrated circuits protected by substrates with cavities, and methods of manufacture
US20160190034A1 (en) * 2014-03-31 2016-06-30 Fuji Electric Co., Ltd. Power conversion device
US9875952B2 (en) * 2014-03-31 2018-01-23 Fuji Electric Co., Ltd. Power conversion device
US9508638B2 (en) * 2014-05-02 2016-11-29 Invensas Corporation Making electrical components in handle wafers of integrated circuit packages
US20160049361A1 (en) * 2014-05-02 2016-02-18 Invensas Corporation Making electrical components in handle wafers of integrated circuit packages
US20170077076A1 (en) * 2014-05-02 2017-03-16 Invensas Corporation Making electrical components in handle wafers of integrated circuit packages
US9831302B2 (en) * 2014-05-02 2017-11-28 Invensas Corporation Making electrical components in handle wafers of integrated circuit packages
US9741649B2 (en) 2014-06-04 2017-08-22 Invensas Corporation Integrated interposer solutions for 2D and 3D IC packaging
US9536862B2 (en) 2014-07-10 2017-01-03 Invensas Corporation Microelectronic assemblies with integrated circuits and interposers with cavities, and methods of manufacture
US20160247742A1 (en) * 2015-02-19 2016-08-25 Micron Technology, Inc. Apparatuses and methods for semiconductor die heat dissipation
US20160293581A1 (en) * 2015-03-30 2016-10-06 Mediatek Inc. Semiconductor package assembly with embedded ipd
US9666514B2 (en) * 2015-04-14 2017-05-30 Invensas Corporation High performance compliant substrate
US9478504B1 (en) 2015-06-19 2016-10-25 Invensas Corporation Microelectronic assemblies with cavities, and methods of fabrication
US9812406B2 (en) 2015-06-19 2017-11-07 Invensas Corporation Microelectronic assemblies with cavities, and methods of fabrication
WO2017099931A1 (en) * 2015-12-10 2017-06-15 Intel Corporation Reduced-height memory system and method
WO2017186627A1 (en) * 2016-04-25 2017-11-02 Technische Hochschule Ingolstadt Semiconductor package
EP3240027A1 (en) * 2016-04-25 2017-11-01 Technische Hochschule Ingolstadt Semiconductor package
US9922845B1 (en) * 2016-11-03 2018-03-20 Micron Technology, Inc. Semiconductor package and fabrication method thereof

Also Published As

Publication number Publication date Type
US9691696B2 (en) 2017-06-27 grant
US9899281B2 (en) 2018-02-20 grant
WO2015138393A1 (en) 2015-09-17 application
US20160155695A1 (en) 2016-06-02 application
KR20160132093A (en) 2016-11-16 application
US20150262928A1 (en) 2015-09-17 application
US20180130717A1 (en) 2018-05-10 application
US9324626B2 (en) 2016-04-26 grant
US20170040237A1 (en) 2017-02-09 application

Similar Documents

Publication Publication Date Title
US8519537B2 (en) 3D semiconductor package interposer with die cavity
US20070287265A1 (en) Substrate treating method and method of manufacturing semiconductor apparatus
US20090212420A1 (en) integrated circuit device and method for fabricating same
US20130062760A1 (en) Packaging Methods and Structures Using a Die Attach Film
US20140217610A1 (en) 3D Semiconductor Package Interposer with Die Cavity
US20120273960A1 (en) Semiconductor Device and Method of Embedding TSV Semiconductor Die Within Encapsulant with TMV for Vertical Interconnect in POP
US20120146177A1 (en) Semiconductor Device and Method of Forming Recesses in Substrate for Same Size or Different Sized Die with Vertical Integration
US20100193928A1 (en) Semiconductor device
US20150001708A1 (en) Semiconductor Device and Method of Forming Low Profile 3D Fan-Out Package
US20080057620A1 (en) Redistribution layers for microfeature workpieces, and associated systems and methods
US20130307140A1 (en) Packaging with interposer frame
US7883991B1 (en) Temporary carrier bonding and detaching processes
US20070045836A1 (en) Stacked chip package using warp preventing insulative material and manufacturing method thereof
US7038316B2 (en) Bumpless die and heat spreader lid module bonded to bumped die carrier
US20120104580A1 (en) Substrateless power device packages
US20080169548A1 (en) Semiconductor package having a semiconductor chip in a substrate and method of fabricating the same
US20100159643A1 (en) Bonding ic die to tsv wafers
US20130105966A1 (en) Three-dimensional chip-to-wafer integration
US20130217188A1 (en) Structures and Formation Methods of Packages with Heat Sinks
US7858441B2 (en) Semiconductor package with semiconductor core structure and method of forming same
US20120112336A1 (en) Encapsulated die, microelectronic package containing same, and method of manufacturing said microelectronic package
US8288854B2 (en) Semiconductor package and method for making the same
US20130016477A1 (en) Electronic Assembly Including Die on Substrate With Heat Spreader Having an Open Window on the Die
US20090294959A1 (en) Semiconductor package device, semiconductor package structure, and fabrication methods thereof
US20100308455A1 (en) Method for Manufacturing Hetero-Bonded Wafer

Legal Events

Date Code Title Description
AS Assignment

Owner name: INVENSAS CORPORATION, CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SHEN, HONG;WOYCHIK, CHARLES G.;ARKALGUD, SITARAM R.;REEL/FRAME:032447/0512

Effective date: 20140314

AS Assignment

Owner name: ROYAL BANK OF CANADA, AS COLLATERAL AGENT, CANADA

Free format text: SECURITY INTEREST;ASSIGNORS:INVENSAS CORPORATION;TESSERA, INC.;TESSERA ADVANCED TECHNOLOGIES, INC.;AND OTHERS;REEL/FRAME:040797/0001

Effective date: 20161201