JP2003133656A - Mounting structure of semiconductor element - Google Patents

Mounting structure of semiconductor element

Info

Publication number
JP2003133656A
JP2003133656A JP2001325873A JP2001325873A JP2003133656A JP 2003133656 A JP2003133656 A JP 2003133656A JP 2001325873 A JP2001325873 A JP 2001325873A JP 2001325873 A JP2001325873 A JP 2001325873A JP 2003133656 A JP2003133656 A JP 2003133656A
Authority
JP
Japan
Prior art keywords
semiconductor element
wiring board
filler
groove
mounting structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001325873A
Other languages
Japanese (ja)
Inventor
Michio Shinozaki
道生 篠崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2001325873A priority Critical patent/JP2003133656A/en
Publication of JP2003133656A publication Critical patent/JP2003133656A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Structure Of Printed Boards (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a mounting structure having high mounting reliability even in the case that the difference in thermal expansions between a semiconductor element and a wiring board is large, in the mounting structure where a mounting part between both is filled with a filler. SOLUTION: The mounting structure of the semiconductor element is formed by placing the semiconductor element 13 provided with a connecting electrode 14 on the surface of the wiring board 1 provided with a wiring conductor layer 8, by connecting the layer 8 and the electrode 14 together through hard soldering, and by filling a filler 16 containing thermosetting resin into the connecting part of the layer 8 and the electrode 14. A groove 12 whose inner width is larger than the width of an opening 18 is formed on the surface of the wiring board 1 situated on a fillet part 17 made of the filler 16 which is formed on the periphery of the semiconductor element 13. Adhesive strength of the filler 16 against the wiring board 1 can be enhanced, generation of cracks on a boundary face between the filler 16 of the fillet part 17 and the wiring board 1 can be prevented, and progress of the cracks can be effectively prevented by the groove 12 even in the case of generation of the cracks.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、半導体素子の実装
構造に関し、特に大型の配線基板上に半導体素子をロウ
付けにより表面実装し、さらにその配線基板と半導体素
子の間に熱硬化性樹脂を含む充填剤を注入硬化させてな
る熱履歴特性・使用耐久性・信頼性に優れた半導体素子
の実装構造に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element mounting structure, and in particular, a semiconductor element is surface-mounted on a large wiring board by brazing, and a thermosetting resin is provided between the wiring board and the semiconductor element. The present invention relates to a mounting structure of a semiconductor element which is excellent in heat history characteristics, durability in use, and reliability obtained by injecting and curing a filler containing it.

【0002】[0002]

【従来の技術】従来、マイクロプロセッサやASIC
(Application Specific Integrated Circuit)等に代
表される半導体素子が搭載され、電子回路基板等に使用
される配線基板は、一般にアルミナ,ムライト等のセラ
ミックスからなる絶縁基板の表面および内部に、タング
ステン,モリブデン等の高融点金属粉末から成る複数個
のメタライズ配線層が配設されるものである。
2. Description of the Related Art Conventionally, microprocessors and ASICs have been used.
A wiring board on which a semiconductor element typified by (Application Specific Integrated Circuit) or the like is mounted and which is used for an electronic circuit board or the like is generally tungsten, molybdenum, etc. on the surface and inside of an insulating substrate made of ceramics such as alumina and mullite. A plurality of metallized wiring layers made of the refractory metal powder are disposed.

【0003】最近では、このような配線基板と半導体素
子との接続は、従来のワイヤボンディング方式から、半
導体素子の下面に接続用電極を設け、これと配線基板の
接続端子とを直接ロウ付けするフリップチップ実装方式
に移行しつつある。
Recently, in order to connect such a wiring board and a semiconductor element, a connection electrode is provided on the lower surface of the semiconductor element by a conventional wire bonding method, and this and the connection terminal of the wiring board are directly brazed. It is shifting to the flip chip mounting method.

【0004】また、このフリップチップ実装による接続
では、接続信頼性を高めるために、その接続部に熱硬化
性樹脂を含むアンダーフィルと呼ばれる充填剤を注入し
硬化させて、接続部を機械的に補強することがしばしば
行なわれる。
Further, in the connection by the flip chip mounting, in order to improve the connection reliability, a filler called underfill containing a thermosetting resin is injected into the connection portion and hardened to mechanically connect the connection portion. Reinforcement is often done.

【0005】一方、配線基板は、接続端子の実装密度を
高める要求から、半田ボールを介したいわゆるボールグ
リッドアレイ(BGA)方式にて、プリント基板等の樹
脂成分を含有する有機質材料または有機質材料と無機質
材料との複合材で構成されるマザーボードヘ実装されて
いる。
On the other hand, the wiring board is made of an organic material containing a resin component or an organic material containing a resin component such as a printed circuit board by a so-called ball grid array (BGA) method via solder balls in order to increase the mounting density of connection terminals. It is mounted on a motherboard that is composed of a composite material with an inorganic material.

【0006】しかしながら、アルミナ,ムライト等の絶
縁材料から成るセラミックス多層配線基板を、ガラスエ
ポキシ樹脂複合材料等の有機樹脂を含む絶縁材料から成
るマザーボードに表面実装した場合には、配線基板とマ
ザーボードとの熱膨張率の差が大きいため、熱応力によ
って、接続用端子が絶縁基板より剥離したり、接続部に
クラック等が生じたりし、配線基板のマザーボード上へ
の良好な実装状態を長期にわたり安定に維持できないと
いう問題があった。
However, when a ceramic multilayer wiring board made of an insulating material such as alumina or mullite is surface-mounted on a mother board made of an insulating material containing an organic resin such as a glass-epoxy resin composite material, the wiring board and the mother board are separated from each other. Due to the large difference in coefficient of thermal expansion, thermal stress may cause the connecting terminals to peel off from the insulating substrate or cause cracks in the connecting parts, ensuring a good mounting state of the wiring board on the motherboard for a long period of time. There was a problem that it could not be maintained.

【0007】したがって、BGAのような高密度で接続
端子を形成した配線基板においては、絶縁基板として、
マザーボードとの熱膨張係数差の小さな、高熱膨張特性
を有するセラミック多層配線基板やガラスエポキシ樹脂
基材にポリイミドまたはエポキシ樹脂等の有機系材料を
用いて形成したいわゆるビルドアップ多層配線基板が用
いられる。
Therefore, in a wiring board in which connection terminals are formed at a high density such as BGA, an insulating board is used.
A so-called build-up multilayer wiring board is used which has a small coefficient of thermal expansion difference from that of a mother board and which has a high thermal expansion characteristic, or a glass epoxy resin substrate formed of an organic material such as polyimide or epoxy resin.

【0008】このような配線基板を用いることによっ
て、マザーボートとの熱膨張差によって接続端子に発生
する熱応力を最小限に抑え、接続用端子と絶縁基板との
剥離や接続部のクラック等が生じることなく、配線基板
のマザーボード上への良好な実装状態を長期にわたり安
定に維持できる。
By using such a wiring board, the thermal stress generated in the connection terminal due to the difference in thermal expansion from the mother boat is minimized, and peeling between the connection terminal and the insulating board and cracks in the connection portion are prevented. A good mounting state of the wiring board on the mother board can be stably maintained for a long time without any occurrence.

【0009】しかしながら、このような高熱膨張特性を
有するセラミック多層配線基板およびビルドアップ多層
配線基板を用いた場合には、これらの配線基板に実装さ
れる、熱膨張係数が2〜3×10-6/℃のシリコン(S
i)より成る半導体素子との熱膨張係数差が大きくな
り、その結果、ビルドアップ多層配線基板の表面に半導
体素子をフリップチップ実装した場合に、半導体素子と
ビルドアップ多層配線基板との熱膨張係数差により半導
体素子の作動・停止に伴って発生する熱応力によって、
半導体素子と配線基板との間の充填材が剥離するという
新たな問題が発生することが判明した。
However, when the ceramic multilayer wiring board and the build-up multilayer wiring board having such high thermal expansion characteristics are used, the coefficient of thermal expansion mounted on these wiring boards is 2 to 3 × 10 −6. / ° C Silicon (S
The difference in coefficient of thermal expansion from the semiconductor element made of i) becomes large, and as a result, when the semiconductor element is flip-chip mounted on the surface of the buildup multilayer wiring board, the coefficient of thermal expansion between the semiconductor element and the buildup multilayer wiring board is increased. Due to the thermal stress caused by the operation / stop of the semiconductor element due to the difference,
It has been found that a new problem occurs that the filler between the semiconductor element and the wiring board is peeled off.

【0010】また、このような熱応力に対しては、半導
体素子との接続部に熱硬化性樹脂を含有する充填剤を充
填することが効果的であるが、このような充填剤を充填
しても、熱応力によって半導体素子の実装部の周辺に充
填剤によって形成されるフィレット部(裾拡がり部とも
いう)の充填剤と配線基板との界面にクラックが発生
し、このクラックが半導体素子の電極と配線基板の接続
端子とのロウ材による接続部まで進展し、これら電極と
接続端子との電気的な接続状態が損なわれるという問題
が発生する。
Further, it is effective to fill a filler containing a thermosetting resin in the connection portion with the semiconductor element against such thermal stress, but such a filler is filled. However, due to thermal stress, a crack occurs at the interface between the filler and the wiring board in the fillet portion (also referred to as the skirt spreading portion) formed by the filler around the mounting portion of the semiconductor element, and the crack is generated in the semiconductor element. There is a problem that the electrode is connected to the connection terminal of the wiring board by the brazing material and the electrical connection between the electrode and the connection terminal is impaired.

【0011】このようなクラックを防止する方法とし
て、例えば特開2001−188362号公報には、高熱膨張特性
を有するセラミックス多層配線基板に関して、半導体素
子の周囲に形成された充填剤によるフィレット部に位置
する配線基板表面に溝を形成する半導体素子の実装構造
が提案されている。
As a method for preventing such cracks, for example, Japanese Unexamined Patent Publication No. 2001-188362 discloses a ceramic multilayer wiring board having high thermal expansion characteristics, which is located at a fillet portion formed by a filler formed around a semiconductor element. There is proposed a mounting structure of a semiconductor element in which a groove is formed on the surface of a wiring board.

【0012】[0012]

【発明が解決しようとする課題】特開2001−188362号公
報において提案されたような配線基板表面に溝を設ける
構造は、半導体素子と配線基板との熱膨張率の差によっ
て発生する熱応力がフィレット部の充填剤と配線基板と
の界面に発生するせん断応力のみの場合は効果的であ
る。
In the structure in which a groove is provided on the surface of the wiring board as proposed in Japanese Patent Laid-Open No. 2001-188362, the thermal stress generated by the difference in the coefficient of thermal expansion between the semiconductor element and the wiring board is It is effective when only the shear stress generated at the interface between the filler in the fillet portion and the wiring board is used.

【0013】しかしながら、半導体素子の動作時に発す
る熱が配線基板に繰り返し印加されると、半導体素子と
配線基板の熱膨張差が大きい場合には、熱応力歪みが発
生し、配線基板に反りが発生する場合がある。この場
合、熱応力は、フィレット部の充填剤と配線基板との界
面にせん断と引っ張りの2つの方向に働くこととなる。
この場合は、配線基板表面に溝を設けただけでは、引っ
張り応力に対して効果が薄く、半導体素子の実装部の周
辺に充填剤によって形成されるフィレット部の充填剤と
配線基板との界面にクラックが発生してしまい、このク
ラックが半導体素子の電極と配線基板の接続端子とのロ
ウ材による接続部まで進展し、これら電極と接続端子と
の電気的な接続状態が損なわれるという問題が発生す
る。
However, when the heat generated during the operation of the semiconductor element is repeatedly applied to the wiring board, when the difference in thermal expansion between the semiconductor element and the wiring board is large, thermal stress strain occurs and the wiring board warps. There is a case. In this case, the thermal stress acts on the interface between the filler in the fillet portion and the wiring board in two directions of shear and tension.
In this case, only providing a groove on the surface of the wiring board has a small effect on the tensile stress, and the interface between the filler of the fillet formed by the filler around the mounting portion of the semiconductor element and the wiring board is reduced. A crack will occur, and this crack will progress to the connection part between the electrode of the semiconductor element and the connection terminal of the wiring board by the brazing material, and the electrical connection state between these electrodes and the connection terminal will be damaged. To do.

【0014】本発明は、上記のような半導体素子と配線
基板との実装部に充填剤を充填した実装構造において、
半導体素子と配線基板との熱膨張差が大きく、基板に反
りが発生する場合においても、高い実装信頼性を有する
半導体素子の実装構造を提供することを目的とするもの
である。
The present invention provides a mounting structure in which the mounting portion of the semiconductor element and the wiring board as described above is filled with a filler.
An object of the present invention is to provide a mounting structure of a semiconductor element having high mounting reliability even when the difference in thermal expansion between the semiconductor element and the wiring board is large and the board warps.

【0015】[0015]

【課題を解決するための手段】本発明者は、配線基板に
半導体素子をフリップチップ実装し、その実装部に熱硬
化性樹脂を含有する充填剤を充填した構造において、半
導体素子の周囲に形成された充填剤によるフィレット部
に位置する配線基板の表面に、開口の幅よりも内部の幅
が広い溝を形成することにより、上記の問題を解決で
き、強固な、かつ長期にわたり安定した電気接続を維持
できることを見出し、本発明を完成するに至ったもので
ある。
DISCLOSURE OF THE INVENTION The present inventor has formed a semiconductor element around a semiconductor element in a structure in which a semiconductor element is flip-chip mounted on a wiring board and the mounting portion is filled with a filler containing a thermosetting resin. The above problem can be solved by forming a groove with an internal width wider than the width of the opening on the surface of the wiring board located in the fillet part by the filled filler, and a strong and stable electrical connection over a long period of time can be achieved. The inventors have found that the above can be maintained and have completed the present invention.

【0016】即ち、本発明の半導体素子の実装構造は、
配線導体層を備えた配線基板の表面に、接続用電極を備
えた半導体素子を載置し、前記配線導体層と前記接続用
電極とをロウ付け接続し、かつその接続部に熱硬化性樹
脂を含む充填剤を充填して成る半導体素子の実装構造で
あって、前記半導体素子の周囲に形成された前記充填剤
によるフィレット部に位置する前記配線基板の表面に、
開口の幅よりも内部の幅が広い溝を形成したことを特徴
とするものである。
That is, the semiconductor element mounting structure of the present invention is
On the surface of a wiring board having a wiring conductor layer, a semiconductor element having a connecting electrode is placed, the wiring conductor layer and the connecting electrode are brazed and connected, and a thermosetting resin is provided at the connecting portion. In the mounting structure of a semiconductor element formed by filling a filler containing, on the surface of the wiring board located in the fillet portion by the filler formed around the semiconductor element,
It is characterized in that a groove having an inner width wider than the width of the opening is formed.

【0017】また、本発明の半導体素子の実装構造にお
いては、前記溝の内部の最も広い幅が前記開口の幅の1.
2〜5倍であること、前記溝の深さが30〜150μmである
こと、前記熱硬化性樹脂が、エポキシ樹脂を含むことが
望ましい。
In the semiconductor element mounting structure of the present invention, the widest width inside the groove is 1.
It is preferable that the groove depth is 2 to 5 times, the groove depth is 30 to 150 μm, and the thermosetting resin contains an epoxy resin.

【0018】本発明によれば、このような実装構造にお
いて、半導体素子の周囲に形成された充填剤によるフィ
レット部に位置する配線基板の表面に、開口の幅よりも
内部の幅が広い溝を形成したことで、この溝が充填剤の
フィレット部を引き剥がそうとする力に対してアンカー
として作用し、熱膨張差に起因する引っ張り応力に対し
ても配線基板に対する充填剤の接着強度を高めることが
でき、半導体素子の作動時に発する熱が配線基板に繰り
返し印加された場合に半導体素子と配線基板との熱膨張
係数差によって発生する熱応力歪みが原因となる、フィ
レット部の充填剤と配線基板との界面のクラックの発生
を防ぐことができ、仮にクラックが発生したとしても、
この溝によってクラックの進展を有効に防止することが
できる。
According to the present invention, in such a mounting structure, a groove having an inner width larger than the width of the opening is formed on the surface of the wiring substrate located in the fillet portion formed by the filler formed around the semiconductor element. By forming the groove, the groove acts as an anchor against the force of peeling the fillet portion of the filler, and enhances the adhesive strength of the filler to the wiring board even against the tensile stress caused by the difference in thermal expansion. The filler and the wiring of the fillet portion, which can be caused by the thermal stress distortion generated by the difference in the coefficient of thermal expansion between the semiconductor element and the wiring board when the heat generated during the operation of the semiconductor element is repeatedly applied to the wiring board. It is possible to prevent the occurrence of cracks at the interface with the substrate, and even if cracks occur,
This groove can effectively prevent the development of cracks.

【0019】また、本発明によれば、溝の内部の最も広
い幅を開口の幅の1.2〜5倍とすることで、この溝が半
導体素子の周囲に配設される微細配線の妨げとならず、
かつ充填剤が配線基板に十分固定され、アンカーとして
より効果的に作用するので、半導体素子の作動時に発す
る熱が配線基板に繰り返し印加された場合に半導体素子
と配線基板との熱膨張係数差によって発生する熱応力歪
みが原因となる、フィレット部の充填剤と配線基板との
界面のクラックの発生防止に、さらに有効に機能するも
のとできる。
Further, according to the present invention, the widest inside of the groove is set to 1.2 to 5 times the width of the opening, so that the groove does not interfere with fine wiring arranged around the semiconductor element. No
And since the filler is sufficiently fixed to the wiring board and acts more effectively as an anchor, when the heat generated during the operation of the semiconductor element is repeatedly applied to the wiring board, the difference in the thermal expansion coefficient between the semiconductor element and the wiring board causes It can more effectively function to prevent the occurrence of cracks at the interface between the filler in the fillet portion and the wiring board, which is caused by the generated thermal stress strain.

【0020】また、本発明によれば、溝の深さを30〜15
0μmとすることにより、溝にボイドを発生させずに充
填剤を充填することができ、さらに、フィレット部にお
いて溝に充填された充填剤を固定する十分な強度が確保
できるので、熱サイクル試験およびプレッシャークッカ
ー試験においても、充填剤が配線基板から剥がれること
がないものとすることができる。
Further, according to the present invention, the groove depth is 30 to 15 mm.
By setting the thickness to 0 μm, it is possible to fill the groove with the filler without generating voids, and further, it is possible to secure sufficient strength to fix the filler filled in the groove in the fillet portion. Even in the pressure cooker test, the filler can be prevented from peeling off from the wiring board.

【0021】また、本発明によれば、エポキシ樹脂を含
む熱硬化性樹脂を充填剤とすることにより、熱サイクル
試験等において充填剤が熱分解することがなく、配線基
板との密着をさらに強固に保つことが可能となり、熱サ
イクル試験およびプレッシャークッカー試験において
も、充填剤が配線基板から剥がれることがないものとす
ることができる。
Further, according to the present invention, by using a thermosetting resin containing an epoxy resin as the filler, the filler is not thermally decomposed in a heat cycle test or the like, and the adhesion with the wiring board is further strengthened. It is possible to keep the temperature of the filler in the heat cycle test and the pressure cooker test and prevent the filler from peeling off from the wiring board.

【0022】これにより、半導体素子と配線基板とを長
期にわたり強固に電気的接続することができ、長期使用
に対しても高い信頼性を確保できる半導体素子の実装構
造を提供することができる。
With this, it is possible to provide a semiconductor element mounting structure in which the semiconductor element and the wiring board can be firmly electrically connected to each other for a long period of time, and high reliability can be ensured even for long-term use.

【0023】[0023]

【発明の実施の形態】以下、本発明の半導体素子実装基
板について添付図面に基づき詳細に説明する。図1は本
発明の半導体素子の実装構造の実施の形態の一例を示す
要部断面図であり、図2はその半導体素子の実装部の拡
大断面図である。図1において、1は配線基板、2は絶
縁基体であり、絶縁基体2には貫通導体3が形成されて
いる。さらに絶縁基体2の表面には貫通導体3から延設
された接続ランド4が形成され、コア基板5を構成して
いる。また、貫通導体3の内部には絶縁材料もしくは導
電材料6が充填され、コア基板5の表面には複数の絶縁
層7および複数の配線導体層8が形成されており、この
配線導体層8の一部として、一方の表面には外部との電
気接続のための外部接続用パッド9が形成され、複数の
ビア導体10にて接続ランド4と電気的に接続されてい
る。また、他方の表面には、同様に配線導体層8の一部
として半導体素子接続用パッド11が形成され、複数のビ
ア導体10にて接続ランド4と電気的に接続されている。
BEST MODE FOR CARRYING OUT THE INVENTION A semiconductor element mounting substrate of the present invention will be described in detail below with reference to the accompanying drawings. FIG. 1 is a sectional view of an essential part showing an example of an embodiment of a mounting structure of a semiconductor element of the present invention, and FIG. 2 is an enlarged sectional view of a mounting part of the semiconductor element. In FIG. 1, 1 is a wiring board, 2 is an insulating base, and a through conductor 3 is formed on the insulating base 2. Further, a connection land 4 extending from the penetrating conductor 3 is formed on the surface of the insulating base 2 to form a core substrate 5. Further, the through conductor 3 is filled with an insulating material or a conductive material 6, and a plurality of insulating layers 7 and a plurality of wiring conductor layers 8 are formed on the surface of the core substrate 5. As a part, an external connection pad 9 for electrical connection to the outside is formed on one surface, and is electrically connected to the connection land 4 by a plurality of via conductors 10. Similarly, a semiconductor element connecting pad 11 is formed as a part of the wiring conductor layer 8 on the other surface, and is electrically connected to the connection land 4 by a plurality of via conductors 10.

【0024】本発明の実装構造に用いる配線基板におい
て、各絶縁層7は、例えばポリイミド,エポキシ樹脂,
フッ素樹脂,ポリノルボルネンまたはベンゾシクロブテ
ン等の有機絶縁材料を使用して、あるいはセラミックス
粉末等の無機絶縁物粉末をエポキシ樹脂等の熱硬化性樹
脂で結合して成る複合絶縁材料等の電気絶縁材料を使用
して形成される。
In the wiring board used in the mounting structure of the present invention, each insulating layer 7 is made of, for example, polyimide, epoxy resin,
Electrical insulating material such as composite insulating material formed by using organic insulating material such as fluororesin, polynorbornene or benzocyclobutene, or combining inorganic insulating powder such as ceramic powder with thermosetting resin such as epoxy resin Is formed using.

【0025】これらの絶縁層7は以下のようにして作製
される。例えばエポキシ樹脂から成る場合であれば、一
般に酸化アルミニウム質焼結体から成るセラミックスや
ガラス繊維を織り込んだ布にエポキシ樹脂を含浸させて
形成されるガラスエポキシ樹脂等から成る絶縁層の上面
に、有機樹脂前駆体をスピンコート法もしくはカーテン
コート法等の塗布技術により被着させ、これを熱硬化処
理することによって形成されるエポキシ樹脂等の有機樹
脂から成る絶縁層7と、銅を無電解めっき法や蒸着法等
の薄膜形成技術およびフォトリソグラフィ技術を採用す
ることによって形成される薄膜配線導体層8とを交互に
積層し、約170℃程度の温度で加熱硬化することによっ
て製作される。
These insulating layers 7 are manufactured as follows. For example, in the case of an epoxy resin, ceramics made of a sintered aluminum oxide or glass fiber woven cloth is generally impregnated with epoxy resin to form an insulating layer made of glass epoxy resin on the upper surface of the organic layer. An insulating layer 7 made of an organic resin such as an epoxy resin formed by applying a resin precursor by a coating technique such as a spin coating method or a curtain coating method and subjecting it to heat curing, and a copper electroless plating method. It is manufactured by alternately laminating thin film wiring conductor layers 8 formed by adopting a thin film forming technique such as a vapor deposition method and a photolithography technique, and heating and curing at a temperature of about 170 ° C.

【0026】また、各配線導体層8は、例えば銅(C
u),銀(Ag),ニッケル(Ni),クロム(C
r),チタン(Ti),金(Au)またはニオブ(N
b)やそれらの合金等の金属材料の薄膜等により形成す
ればよい。
Each wiring conductor layer 8 is made of, for example, copper (C
u), silver (Ag), nickel (Ni), chromium (C
r), titanium (Ti), gold (Au) or niobium (N)
It may be formed by a thin film of a metal material such as b) or an alloy thereof.

【0027】具体的には、例えば金属材料の薄膜で形成
する場合は、スパッタリング法,真空蒸着法またはメッ
キ法により金属膜を形成した後、フォトリソグラフィ法
により所定の配線パターンに形成することができる。
Specifically, in the case of forming a thin film of a metal material, for example, a metal film can be formed by a sputtering method, a vacuum deposition method or a plating method, and then formed into a predetermined wiring pattern by a photolithography method. .

【0028】この例では、配線基板1の上面にはマイク
ロプロセッサやASIC等の半導体素子13が搭載され、
Sn−Pb等の半田等から成る導体バンプ15および半導
体素子13接続用の半導体素子接続用パッド11を介して配
線基板1と電気的に接続されている。
In this example, a semiconductor element 13 such as a microprocessor or ASIC is mounted on the upper surface of the wiring board 1.
It is electrically connected to the wiring board 1 through the conductor bumps 15 made of solder such as Sn-Pb and the semiconductor element connecting pads 11 for connecting the semiconductor elements 13.

【0029】本発明の半導体素子の実装構造は、絶縁基
板の少なくとも表面に配線導体層が配設された配線基板
を用いるものであるが、この図1に示す例では、配線基
板としてBGA型パッケージを用いた場合の実装構造を
示している。すなわち、図1において、1はBGA型パ
ッケージを構成する配線基板であり、13が半導体素子で
ある。
The semiconductor element mounting structure of the present invention uses a wiring board in which a wiring conductor layer is provided on at least the surface of an insulating board. In the example shown in FIG. 1, a BGA type package is used as the wiring board. The mounting structure when using is shown. That is, in FIG. 1, reference numeral 1 is a wiring board constituting a BGA type package, and 13 is a semiconductor element.

【0030】半導体素子13は、フリップチップ型のもの
で、Si系等の半導体材料から成り、その下面には半田
バンプ等の導体バンプ15が形成されている。そして、こ
の半導体素子13は、図2の要部拡大図に示すように、配
線基板1の上面のランド部11に対して、導体バンプ15を
載置当接させ、しかる後、約250〜400℃の温度で加熱し
て導体バンプ15を溶融させることにより、半導体素子13
の接続用電極14を配線基板1のランド部11に接合させ、
実装されている。そして、この半導体素子13の実装部に
は、実装部の補強のために熱硬化性樹脂を含有する充填
剤16が充填されている。
The semiconductor element 13 is of a flip-chip type, is made of a semiconductor material such as Si, and has conductor bumps 15 such as solder bumps formed on its lower surface. As shown in the enlarged view of the main part of FIG. 2, in the semiconductor element 13, the conductor bumps 15 are placed and abutted on the land portions 11 on the upper surface of the wiring substrate 1, and thereafter, about 250 to 400. By heating at a temperature of ° C. to melt the conductor bumps 15, the semiconductor element 13
The connection electrode 14 of is connected to the land portion 11 of the wiring board 1,
It is implemented. Then, the mounting portion of the semiconductor element 13 is filled with a filler 16 containing a thermosetting resin for reinforcing the mounting portion.

【0031】本発明の半導体素子の実装構造において
は、半導体素子13の周囲に形成される充填剤16のフィレ
ット部17に位置する配線基板1の表面に、開口の幅より
も内側の幅が広い溝12が形成されている。図2に示した
例における溝12では、その開口18の幅よりも内部の幅が
広く、底の部分で最も幅の広い部分の寸法19となってい
る。この溝12には充填剤16が充填され、半導体素子13の
実装部の充填材16およびフィレット部17と一体となって
いる。この結果、この溝12内の充填剤16がアンカーとし
て作用することにより、充填剤16の配線基板1との接着
強度を高めることができる。
In the semiconductor element mounting structure of the present invention, the inner width is wider than the opening width on the surface of the wiring board 1 located in the fillet portion 17 of the filler 16 formed around the semiconductor element 13. Groove 12 is formed. In the groove 12 in the example shown in FIG. 2, the inner width is wider than the width of the opening 18, and the dimension is 19 at the widest portion at the bottom portion. The groove 12 is filled with a filler 16 and is integrated with the filler 16 and the fillet portion 17 of the mounting portion of the semiconductor element 13. As a result, the filler 16 in the groove 12 acts as an anchor, so that the adhesive strength of the filler 16 with the wiring board 1 can be increased.

【0032】また、溝12の幅は、フィレット部17の幅に
応じて適宜選択されるが、特にその開口18の幅が通常は
0.1〜0.5mmとされることから、この溝12内の充填剤16
にアンカーとしての効果を発揮させるためには、溝12の
内部の最も幅の広い部分の寸法19が開口18の幅の1.2〜
5倍であることが望ましい。この溝12の内部の最も幅の
広い部分の寸法19が開口18の幅の1.2倍未満である場合
は、溝12内の充填剤16が引っ張り応力に対するアンカー
としての機能を十分に発揮しない傾向がある。他方、5
倍を超える場合は、半導体素子13の周囲に形成される信
号線を微細配線とすることの妨げとなってしまうことが
ある。
The width of the groove 12 is appropriately selected according to the width of the fillet portion 17, but in particular, the width of the opening 18 is usually set.
Since it is 0.1 to 0.5 mm, the filler 16 in the groove 12 is
In order to exert the effect as an anchor on the inside, the dimension 19 of the widest portion inside the groove 12 is 1.2 to the width of the opening 18.
It is desirable to be 5 times. When the dimension 19 of the widest portion inside the groove 12 is less than 1.2 times the width of the opening 18, the filler 16 in the groove 12 tends not to sufficiently exhibit the function as an anchor for tensile stress. is there. On the other hand, 5
If the number exceeds twice, it may hinder the formation of fine wiring for the signal lines formed around the semiconductor element 13.

【0033】また、溝12による上記の効果を発揮させる
ためには、その深さが30〜150μmであることが望まし
い。この溝12の深さが30μmよりも小さいと、せん断応
力に対する効果が望めなくなる傾向がある。他方、150
μmを超えると、プレッシャークッカー試験のような信
頼性試験において充填剤16の剥離が生じやすくなり、ま
た、配線基板1に溝12を起点とするクラックが発生しや
すくなるために、配線基板1の絶対強度が低下しやすく
なる等の不具合が発生することがある。
Further, in order to exert the above effect by the groove 12, it is desirable that the depth thereof is 30 to 150 μm. If the depth of the groove 12 is less than 30 μm, the effect on the shear stress tends to be undesired. On the other hand, 150
When the thickness exceeds μm, the filler 16 is likely to be peeled off in a reliability test such as a pressure cooker test, and cracks originating from the groove 12 in the wiring board 1 are likely to occur. Problems such as that the absolute strength is likely to decrease may occur.

【0034】このような溝12の形成は、コア基板5の表
面の複数の絶縁層7を作製する際に、絶縁層7にレーザ
等を用いて孔開けしたものを硬化するか、硬化後のコア
基板5の表面をレーザ等によって加工することにより行
なうことができる。
The formation of such a groove 12 is performed by hardening the insulating layer 7 which is perforated by using a laser or the like when forming the plurality of insulating layers 7 on the surface of the core substrate 5, or after the hardening. This can be performed by processing the surface of the core substrate 5 with a laser or the like.

【0035】また、溝12の断面形状は、図3に図2と同
様の拡大断面図で示すように、幅の異なる溝が形成され
た絶縁層をそれら溝が重なるように2層以上重ねて、幅
の狭い溝を表層に、幅の広い溝を内層にして積層するよ
うに構成し、開口18の幅よりも内部の幅が広く、略下半
分が最も幅の広い部分の寸法19となっている溝12とされ
ていてもよい。また、溝12は、図4に同様の拡大断面図
で示すように、表裏で開口の幅寸法の異なる溝が形成さ
れた絶縁層を、それら溝の開口の幅の広い面同士が対向
するように積層して構成し、開口18の幅よりも内部の幅
が広く、中央部が最も幅の広い部分の寸法19となってい
る溝12とされていたり、図5に同様の拡大断面図で示す
ように、表裏で開口の幅寸法の異なる溝が形成された絶
縁層を、それら溝の開口の幅の広い面と幅の狭い面とが
対向するように積層して、開口の幅よりも内部の幅が広
い溝となるように構成し、開口18の幅よりも内部の幅が
広く、中央部と底の部分とが最も幅の広い部分の寸法19
となっている溝12とされていてもよい。さらに、溝12
は、図6に同様の拡大断面図で示すように、表裏で開口
の幅寸法の異なる溝が形成された絶縁層を、それら溝の
開口の幅の広い面と幅の狭い面とが対向するように積層
して構成し、開口18から幅が一旦狭くなって中央部で幅
が広くなり、中央部が最も幅の広い部分の寸法19となっ
ている溝12とされていたり、図7に同様の拡大断面図で
示すように、表裏で開口の幅寸法の異なる溝が形成され
た絶縁層を、それら溝の開口の幅の狭い面同士が対向す
るように積層して、絶縁層7内部において、開口18から
幅が一旦狭くなって中央部から徐々に幅が広くなり、底
部が最も幅の広い部分の寸法19となっている溝12とされ
ていてもよい。
The cross-sectional shape of the groove 12 is, as shown in FIG. 3 in an enlarged cross-sectional view similar to FIG. 2, by stacking two or more insulating layers having grooves of different widths so that they overlap. , A narrow groove is formed on the surface layer and a wide groove is formed as an inner layer, and the inner width is wider than the width of the opening 18, and the lower half is the dimension 19 of the widest part. The groove 12 may have a groove. Further, as shown in an enlarged cross-sectional view similar to FIG. 4, the groove 12 has an insulating layer in which grooves having different opening width dimensions are formed on the front and back sides so that the wide surfaces of the openings face each other. It is configured by stacking the layers into a groove 12 having an inner width wider than the width of the opening 18 and a central portion having a dimension 19 of the widest portion, or an enlarged sectional view similar to FIG. As shown in the drawing, insulating layers in which grooves having different widths of openings are formed on the front and back sides are laminated so that the wide and narrow surfaces of the openings face each other, and It is configured to have a groove with a wide inner width, and the inner width is wider than the width of the opening 18, and the central portion and the bottom portion have the widest dimension 19
The groove 12 may be a groove. In addition, the groove 12
As shown in the same enlarged cross-sectional view in FIG. 6, the insulating layer having grooves with different width dimensions of the openings formed on the front and back faces the wide and narrow surfaces of the openings. As shown in FIG. 7, the opening 12 has a width narrowing once and the width becomes wider at the central portion and the central portion has a groove 19 having a dimension 19 of the widest portion. As shown in a similar enlarged cross-sectional view, insulating layers in which grooves having different opening widths are formed on the front and back are laminated so that the narrow surfaces of the openings face each other. In, the groove 12 may be a groove 12 whose width is once narrowed from the opening 18 and gradually widens from the central portion, and whose bottom portion has a dimension 19 of the widest portion.

【0036】また、本発明の半導体素子の実装構造にお
ける充填剤16中に含まれる熱硬化性樹脂としては、例え
ばフェノール樹脂,ユリア樹脂,メラミン樹脂,エポキ
シ樹脂,不飽和ポリエステル樹脂,フタル酸ジアリル樹
脂,ポリイミド樹脂,シリコーン樹脂,ポリウレタン樹
脂等を用いることができる。これらの中でも、ビスフェ
ノール系エポキシ樹脂,ノボラック系エポキシ樹脂,ブ
ロム化エポキシ樹脂,脂環式エポキシ樹脂等の耐熱性に
優れるエポキシ樹脂が特に望ましい。
The thermosetting resin contained in the filler 16 in the semiconductor element mounting structure of the present invention includes, for example, phenol resin, urea resin, melamine resin, epoxy resin, unsaturated polyester resin, diallyl phthalate resin. , Polyimide resin, silicone resin, polyurethane resin, etc. can be used. Among these, epoxy resins having excellent heat resistance such as bisphenol epoxy resin, novolac epoxy resin, brominated epoxy resin, and alicyclic epoxy resin are particularly desirable.

【0037】また、この充填剤16中には、熱硬化性樹脂
以外に、無機フィラーを含有することが望ましい。この
無機質フィラーは、充填剤16の熱膨張係数を下げるため
に熱硬化性樹脂に添加されるものであり、無機質フィラ
ーが球状粒子を主体とする場合には、半導体素子13と配
線基板1との実装部の狭い空間に対する充填性を高める
ことができる結果、充填剤16中への充填不良によるクラ
ックの発生を防止することができる。
In addition to the thermosetting resin, it is desirable that the filler 16 contains an inorganic filler. This inorganic filler is added to the thermosetting resin in order to reduce the coefficient of thermal expansion of the filler 16, and when the inorganic filler is mainly composed of spherical particles, the semiconductor element 13 and the wiring substrate 1 As a result of being able to enhance the filling property in the narrow space of the mounting portion, it is possible to prevent the occurrence of cracks due to defective filling in the filler 16.

【0038】この球状粒子は、粒子の表面に角部が実質
的に存在せず、粒子間の摩擦が小さいことから良好な充
填性を示すものと推察される。特にこの球状粒子は、長
径/短径で計算される平均アスペクト比が1.2以下、特
に1.1以下であり、長径による平均粒径が0.3〜20μm、
特に1〜10μmであることが充填性の点から好適であ
る。この平均粒径が0.3μmよりも小さいと、充填剤16
の粘性が低くなり、充填性が悪化してボイドが発生しや
すくなる。他方、平均粒径が20μmを超えると、半導体
素子13と配線基板1との間にフィラーが充填されにくく
なり、ボイドの発生および充填剤16の不均一に伴うクラ
ックが発生しやくなる。
It is speculated that the spherical particles have good filling properties because there are substantially no corners on the surface of the particles and the friction between the particles is small. In particular, the spherical particles have an average aspect ratio calculated by major axis / minor axis of 1.2 or less, particularly 1.1 or less, and an average particle diameter depending on the major axis of 0.3 to 20 μm.
It is particularly preferably 1 to 10 μm from the viewpoint of filling property. If this average particle size is smaller than 0.3 μm, the filler 16
Has a low viscosity, the filling property is deteriorated, and voids are easily generated. On the other hand, if the average particle size exceeds 20 μm, it becomes difficult to fill the filler between the semiconductor element 13 and the wiring board 1, and voids and cracks due to unevenness of the filler 16 are likely to occur.

【0039】充填剤16に用いられる無機フィラーとして
は、石英ガラス,アルミナ,マイカ,ジルコニウムシリ
ケート,リチウムシリケート等の破砕状もしくは球状の
無機物が望ましい。
As the inorganic filler used for the filler 16, crushed or spherical inorganic substances such as quartz glass, alumina, mica, zirconium silicate and lithium silicate are desirable.

【0040】また、配線基板1が、ヤング率が10〜30G
Paであるガラスエポキシ樹脂基材から成る絶縁基体2
に、この絶縁基体2を貫通する貫通導体3および絶縁基
体2の表面に貫通導体3から延設された接続ランド4を
具備するコア基板5と、このコア基板5の表面に積層さ
れた複数の絶縁層7および複数の配線導体層8から成る
配線部とから成り、かつ絶縁層7の−100〜+300℃にお
けるヤング率が10〜100GPaである場合には、半導体
素子13の作動時に発する熱が配線基板1に繰り返し印加
された場合に、半導体素子13と配線基板1との熱膨張係
数差が大きいために発生する熱応力で配線基板1が大き
く反り、フィレット部17の充填剤16と配線基板1の表面
となる絶縁層7との界面に大きな引っ張りの力が働くた
め、開口18の幅よりも内部の幅が広い溝12は、アンカー
として特に有効に作用する。
The wiring board 1 has a Young's modulus of 10 to 30 G.
Insulating substrate 2 made of a glass epoxy resin substrate that is Pa
In addition, a core substrate 5 having a penetrating conductor 3 penetrating the insulating substrate 2 and a connection land 4 extending from the penetrating conductor 3 on the surface of the insulating substrate 2, and a plurality of core substrates 5 stacked on the surface of the core substrate 5. When the insulating layer 7 and the wiring portion composed of a plurality of wiring conductor layers 8 are formed and the Young's modulus of the insulating layer 7 at −100 to + 300 ° C. is 10 to 100 GPa, heat generated during the operation of the semiconductor element 13 is generated. When repeatedly applied to the wiring board 1, the wiring board 1 is largely warped by the thermal stress generated due to the large difference in thermal expansion coefficient between the semiconductor element 13 and the wiring board 1, and the filler 16 of the fillet portion 17 and the wiring board 1 are warped. Since a large tensile force acts on the interface with the insulating layer 7 which is the surface of the groove 1, the groove 12 having an inner width wider than the width of the opening 18 acts particularly effectively as an anchor.

【0041】そして、このような本発明の半導体素子の
実装構造により半導体素子13が実装された配線基板1
は、半導体素子収納用パッケージ等の電子部品収納用パ
ッケージや電子部品搭載用基板、多数の半導体素子が搭
載されるいわゆるマルチチップモジュールやマルチチッ
プパッケージ等として使用される。
Then, the wiring board 1 on which the semiconductor element 13 is mounted by the mounting structure of the semiconductor element of the present invention as described above.
Is used as an electronic component storage package such as a semiconductor element storage package, an electronic component mounting substrate, a so-called multi-chip module or a multi-chip package on which a large number of semiconductor elements are mounted.

【0042】なお、本発明は上記の実施の形態の例に限
定されるものではなく、本発明の要旨を逸脱しない範囲
で種々の変更を行なうことは何ら差し支えない。例え
ば、上記の例では配線基板1としてBGA型パッケージ
を用いた場合の実装構造を示したが、配線基板1として
LGA型パッケージを用いたり、PGA型パッケージを
用いたりした場合であってもよい。
The present invention is not limited to the above-mentioned embodiments, and various modifications may be made without departing from the scope of the present invention. For example, although the mounting structure in which the BGA type package is used as the wiring substrate 1 is shown in the above example, the LGA type package or the PGA type package may be used as the wiring substrate 1.

【0043】[0043]

【発明の効果】本発明は、配線導体層を備えた配線基板
の表面に、接続用電極を備えた半導体素子を載置し、前
記配線導体層と前記接続用電極とをロウ付け接続し、か
つその接続部に熱硬化性樹脂を含む充填剤を充填して成
る半導体素子の実装構造であって、前記半導体素子の周
囲に形成された前記充填剤によるフィレット部に位置す
る前記配線基板の表面に、開口の幅よりも内部の幅が広
い溝を形成したことから、この溝が充填剤のフィレット
部を引き剥がそうとする力に対してアンカーとして作用
し、熱膨張差に起因する引っ張り応力に対しても配線基
板に対する充填剤の接着強度を高めることができ、半導
体素子の作動時に発する熱が配線基板に繰り返し印加さ
れた場合に半導体素子と配線基板との熱膨張係数差が大
きいために発生する熱応力歪みが原因となる、半導体素
子の実装部の周辺に充填剤によって形成されるフィレッ
ト部の充填剤と配線基板との界面でのクラックの発生を
防ぐことができ、仮にクラックが発生したとしても、こ
の溝によってクラックの進展を有効に防止することが可
能となり、半導体素子等の電子部品を搭載する電子回路
基板等に使用される配線基板に対して好適な半導体素子
の実装構造を提供することができる。
According to the present invention, a semiconductor element having a connection electrode is placed on the surface of a wiring board having a wiring conductor layer, and the wiring conductor layer and the connection electrode are connected by brazing. And a mounting structure of a semiconductor element in which a filler containing a thermosetting resin is filled in the connection portion thereof, the surface of the wiring substrate located in a fillet portion formed by the filler formed around the semiconductor element Since a groove with an internal width wider than the width of the opening was formed in this, the groove acts as an anchor against the force to peel off the fillet portion of the filler, and the tensile stress caused by the difference in thermal expansion Also, the adhesive strength of the filler to the wiring board can be increased, and when the heat generated during the operation of the semiconductor element is repeatedly applied to the wiring board, the difference in the coefficient of thermal expansion between the semiconductor element and the wiring board is large. Occur As a result of thermal stress strain, it is possible to prevent the occurrence of cracks at the interface between the filler and the wiring board of the fillet portion formed by the filler around the mounting portion of the semiconductor element. Also, this groove makes it possible to effectively prevent the development of cracks, and provides a semiconductor element mounting structure suitable for a wiring board used for an electronic circuit board or the like on which electronic components such as a semiconductor element are mounted. be able to.

【0044】また、本発明によれば、前記溝の内部の最
も広い幅を前記開口の幅の1.2〜5倍とすることによ
り、この溝が半導体素子の周囲に配設される微細配線の
妨げとならず、かつ充填剤が配線基板に十分固定され、
アンカーとしてより効果的に作用するので、配線基板に
対する充填剤の接着強度を高めることができ、半導体素
子の作動時に発する熱が配線基板に繰り返し印加された
場合に半導体素子と配線基板との熱膨張係数差が大きい
ために発生する熱応力歪みが原因となる、半導体素子の
実装部の周辺に充填剤によって形成されるフィレット部
の充填剤と配線基板との界面でのクラックの発生防止に
さらに有効に機能させることができる。
Further, according to the present invention, the widest inside of the groove is set to 1.2 to 5 times the width of the opening, so that the groove interferes with fine wiring arranged around the semiconductor element. And the filler is sufficiently fixed to the wiring board,
Since it acts more effectively as an anchor, it can increase the adhesive strength of the filler to the wiring board, and when the heat generated during the operation of the semiconductor element is repeatedly applied to the wiring board, the thermal expansion of the semiconductor element and the wiring board. Further effective in preventing the occurrence of cracks at the interface between the filler of the fillet formed by the filler around the mounting area of the semiconductor element and the wiring board, which is caused by the thermal stress strain caused by the large coefficient difference Can be made to function.

【0045】また、本発明によれば、前記溝の深さを30
〜150μmとすることにより、この溝にボイドを発生さ
せずに充填剤を充填することができ、さらに、フィレッ
ト部において溝に充填された充填剤を固定する十分な強
度が確保できるので、熱サイクル試験およびプレッシャ
ークッカー試験においても、充填剤が配線基板から剥が
れることがないものとすることができる。
Further, according to the present invention, the depth of the groove is 30
By setting the thickness to 150 μm, the filler can be filled in the groove without generating voids, and further, sufficient strength for fixing the filler filled in the groove in the fillet portion can be secured, so that the thermal cycle Even in the test and the pressure cooker test, the filler can be prevented from peeling off from the wiring board.

【0046】また、本発明によれば、エポキシ樹脂を含
む熱硬化性樹脂を充填剤とすることにより、熱サイクル
試験等において充填剤が熱分解することがなく、配線基
板との密着をさらに強固に保つことが可能となり、熱サ
イクル試験およびプレッシャークッカー試験において
も、充填剤が配線基板から剥がれることがないものとす
ることができる。
Further, according to the present invention, by using a thermosetting resin containing an epoxy resin as the filler, the filler is not thermally decomposed in a heat cycle test or the like, and the adhesion with the wiring board is further strengthened. It is possible to keep the temperature of the filler in the heat cycle test and the pressure cooker test and prevent the filler from peeling off from the wiring board.

【0047】以上により、本発明によれば、半導体素子
と配線基板との実装部に充填剤を充填した実装構造にお
いて、半導体素子と配線基板との熱膨張差が大きく、基
板に反りが発生する場合においても、高い実装信頼性を
有する半導体素子の実装構造を提供することができた。
As described above, according to the present invention, in the mounting structure in which the mounting portion between the semiconductor element and the wiring board is filled with the filler, the difference in thermal expansion between the semiconductor element and the wiring board is large, and the board warps. Even in the case, it was possible to provide a mounting structure of a semiconductor element having high mounting reliability.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の半導体素子の実装構造の実施の形態の
一例を示す断面図である。
FIG. 1 is a cross-sectional view showing an example of an embodiment of a semiconductor element mounting structure of the present invention.

【図2】図1に示す例における半導体素子の実装部の拡
大断面図である。
FIG. 2 is an enlarged cross-sectional view of a mounting portion of a semiconductor element in the example shown in FIG.

【図3】本発明の半導体素子の実装構造の他の例におけ
る半導体素子の実装部の拡大断面図である。
FIG. 3 is an enlarged cross-sectional view of a semiconductor element mounting portion in another example of the semiconductor element mounting structure of the present invention.

【図4】本発明の半導体素子の実装構造の他の例におけ
る半導体素子の実装部の拡大断面図である。
FIG. 4 is an enlarged cross-sectional view of a semiconductor element mounting portion in another example of the semiconductor element mounting structure of the present invention.

【図5】本発明の半導体素子の実装構造の他の例におけ
る半導体素子の実装部の拡大断面図である。
FIG. 5 is an enlarged cross-sectional view of a semiconductor element mounting portion in another example of the semiconductor element mounting structure of the present invention.

【図6】本発明の半導体素子の実装構造の他の例におけ
る半導体素子の実装部の拡大断面図である。
FIG. 6 is an enlarged cross-sectional view of a semiconductor element mounting portion in another example of the semiconductor element mounting structure of the present invention.

【図7】本発明の半導体素子の実装構造の他の例におけ
る半導体素子の実装部の拡大断面図である。
FIG. 7 is an enlarged cross-sectional view of a semiconductor element mounting portion in another example of the semiconductor element mounting structure of the present invention.

【符号の説明】[Explanation of symbols]

1:配線基板 2:絶縁基体 3:貫通導体 4:接続ランド 5:コア基板 7:絶縁層 8:配線導体層 9:外部接続用パッド 10:ビア導体 11:半導体素子接続用パッド 12:溝 13:半導体素子 14:接続用電極 15:導体バンプ 16:充填剤 17:フィレット部 18:溝の開口 19:溝の内部における最も幅の広い部分の寸法 20:溝の深さ 1: Wiring board 2: Insulating substrate 3: Through conductor 4: Connection land 5: Core substrate 7: Insulation layer 8: Wiring conductor layer 9: Pad for external connection 10: Via conductor 11: Pad for semiconductor element connection 12: groove 13: Semiconductor element 14: Connection electrode 15: Conductor bump 16: Filler 17: Fillet part 18: Groove opening 19: Dimensions of the widest part inside the groove 20: Groove depth

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 配線導体層を備えた配線基板の表面に、
接続用電極を備えた半導体素子を載置し、前記配線導体
層と前記接続用電極とをロウ付け接続し、かつその接続
部に熱硬化性樹脂を含む充填剤を充填して成る半導体素
子の実装構造であって、前記半導体素子の周囲に形成さ
れた前記充填剤によるフィレット部に位置する前記配線
基板の表面に、開口の幅よりも内部の幅が広い溝を形成
したことを特徴とする半導体素子の実装構造。
1. A surface of a wiring board having a wiring conductor layer,
A semiconductor element comprising a semiconductor element provided with a connecting electrode, the wiring conductor layer and the connecting electrode being brazed and connected, and the connecting portion being filled with a filler containing a thermosetting resin. In the mounting structure, a groove having an inner width wider than the width of the opening is formed on the surface of the wiring board located in the fillet portion formed by the filler formed around the semiconductor element. Semiconductor element mounting structure.
【請求項2】 前記溝の内部の最も広い幅が前記開口の
幅の1.2〜5倍であることを特徴とする請求項1記載
の半導体素子の実装構造。
2. The mounting structure for a semiconductor device according to claim 1, wherein the widest width inside the groove is 1.2 to 5 times the width of the opening.
【請求項3】 前記溝の深さが30〜150μmである
ことを特徴とする請求項1記載の半導体素子の実装構
造。
3. The mounting structure for a semiconductor device according to claim 1, wherein the depth of the groove is 30 to 150 μm.
【請求項4】 前記熱硬化性樹脂が、エポキシ樹脂を含
むことを特徴とする請求項1記載の半導体素子の実装構
造。
4. The mounting structure for a semiconductor element according to claim 1, wherein the thermosetting resin contains an epoxy resin.
JP2001325873A 2001-10-24 2001-10-24 Mounting structure of semiconductor element Pending JP2003133656A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001325873A JP2003133656A (en) 2001-10-24 2001-10-24 Mounting structure of semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001325873A JP2003133656A (en) 2001-10-24 2001-10-24 Mounting structure of semiconductor element

Publications (1)

Publication Number Publication Date
JP2003133656A true JP2003133656A (en) 2003-05-09

Family

ID=19142350

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001325873A Pending JP2003133656A (en) 2001-10-24 2001-10-24 Mounting structure of semiconductor element

Country Status (1)

Country Link
JP (1) JP2003133656A (en)

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Cited By (12)

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Publication number Priority date Publication date Assignee Title
US9502624B2 (en) 2006-05-18 2016-11-22 Nichia Corporation Resin molding, surface mounted light emitting apparatus and methods for manufacturing the same
US9634204B2 (en) 2006-05-18 2017-04-25 Nichia Corporation Resin molding, surface mounted light emitting apparatus and methods for manufacturing the same
US9929318B2 (en) 2006-05-18 2018-03-27 Nichia Corporation Resin molding, surface mounted light emitting apparatus and methods for manufacturing the same
US10263161B2 (en) 2006-05-18 2019-04-16 Nichia Corporation Resin molding, surface mounted light emitting apparatus and methods for manufacturing the same
US10686102B2 (en) 2006-05-18 2020-06-16 Nichia Corporation Resin molding, surface mounted light emitting apparatus and methods for manufacturing the same
US10971656B2 (en) 2006-05-18 2021-04-06 Nichia Corporation Resin molding, surface mounted light emitting apparatus and methods for manufacturing the same
US11631790B2 (en) 2006-05-18 2023-04-18 Nichia Corporation Resin molding, surface mounted light emitting apparatus and methods for manufacturing the same
JP2007329249A (en) * 2006-06-07 2007-12-20 Nichia Chem Ind Ltd Surface-mount light-emitting device and method of manufacturing the same
US8802459B2 (en) 2006-12-28 2014-08-12 Nichia Corporation Surface mount lateral light emitting apparatus and fabrication method thereof
US9190588B2 (en) 2006-12-28 2015-11-17 Nichia Corporation Side-view type light emitting apparatus and package
JP2008210985A (en) * 2007-02-26 2008-09-11 Toshiba Corp Semiconductor device
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