JP5140961B2 - Semiconductor device and manufacturing method thereof, and semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor element and a manufacturing method thereof, and a semiconductor device and a manufacturing method thereof, and more particularly to a bump structure in a flip chip mounting form.

  In a semiconductor chip mounting form using a flip chip method, a solder material mainly composed of lead (Pb) such as high melting point solder (lead (Pb) 95% / tin (Sn) 5%) is used as a connection material. ing. FIG. 9 shows an example of the structure of a conventional semiconductor element using flip-chip solder bumps. As shown in FIG. 9, an electrode 102 and a cover coat film 103 having an opening on the electrode 102 are formed on the semiconductor substrate 101. A solder bump 109 is formed on the electrode 102 via an adhesion layer 104 and a barrier metal layer 108.

  As shown in FIG. 11, the above-described conventional semiconductor element is manufactured as follows. First, an adhesion layer 104 is formed by sputtering on the entire surface of the electrode 102 formed on the circuit formation surface of the semiconductor substrate 101 and the cover coat film 103 having an opening on the electrode 102 (FIG. 11A and FIG. 11). (B)). Thereafter, a plating resist film 117 is supplied to the entire surface of the substrate using a photoresist or the like, and an opening is provided on the electrode 102 (FIG. 11C). Next, after filling the opening of the plating resist film 117 with a solder layer that becomes the barrier metal layer 108 and the solder bump 109 by plating (FIG. 11D), the plating resist film 117 is removed by ashing or the like. Then, the adhesion layer 104 is removed by etching using the solder layer as a mask (FIG. 11E). Finally, the semiconductor substrate 101 is heat-treated to melt the solder layer and form spherical solder bumps 109 (FIG. 11 (f)). Although not shown, as another conventional solder bump manufacturing method, there is a method of forming a bump after melting a solder after forming a barrier metal layer and then mounting a solder ball or supplying solder by printing. is there.

  Recently, there has been proposed a technique for relaxing a stress caused by a difference in thermal expansion between a semiconductor substrate and a wiring substrate and providing a highly reliable flip chip connection structure. As such a connection structure, there is a structure in which a standoff is ensured between a semiconductor substrate and a wiring substrate. As an example, there is a conventional technique disclosed in Patent Document 1. FIG. 10 is a cross-sectional view schematically showing a conventional flip-chip semiconductor device based on FIG. 1 described in Patent Document 1. In FIG. As shown in FIG. 10, an electrode 102 and a cover coat film 103 having an opening on the electrode 102 are formed on the semiconductor substrate 101. Further, columnar bumps 107 made of copper (Cu) are formed on the electrode 102 via an adhesion layer 104. A wetting prevention film 123 made of an oxide film or the like is formed on the side surface of the columnar bump 107. As described above, in Patent Document 1, by using columnar protrusions made of copper (Cu) for bumps and making a standoff, filling of underfill resin is facilitated and reliability is improved at the time of connection of a wiring board. It has a structure.

  Further, as a highly reliable flip chip connection structure different from the above, a structure in which a stress relaxation layer made of an insulating resin is provided in the vicinity of a solder connection portion has been proposed. For example, in Patent Document 2, a semiconductor element in which a multilayer wiring layer including a plurality of low-stress heat-resistant resin layers and at least one conductive layer is provided between an electrode on a semiconductor substrate and a lower electrode of a solder bump. This insulating low stress heat resistant resin layer functions as a stress relaxation layer. Further, in Patent Document 3, a protruding electrode having an insulating resin layer as a stress relaxation layer inside is formed on the wiring board side, and a solder is provided between the wiring board and the electrode portion of the semiconductor element via the protruding electrode. Connected.

  Patent Document 4 discloses a flip chip connection structure provided with a stress relaxation layer made of conductive resin. That is, the connection between the electrode terminals of the semiconductor element and the wiring board is made by supplying a conductive resin to the wiring board side and connecting it to the protruding electrode on the semiconductor element side as a stress relaxation layer. Thus, the structure which relieves | moderates the stress of a connection part is proposed by using electroconductive resin.

JP 2003-234367 A Japanese Patent Laid-Open No. 01-209746 JP 2005-303021 A JP 2001-217281 A

  However, the above-described prior art has the following problems.

  In recent years, there has been an urgent need to eliminate lead in manufactured products in response to environmental regulations, and lead materials such as high-melting-point solder (Pb95% / Sn5%) are also used as connecting materials in flip-chip semiconductor device mounting forms. There is a shift from a solder material mainly composed of (Pb) to a solder material mainly composed of tin (Sn). However, since solder containing tin (Sn) as a main component is harder and less deformable than solder containing lead (Pb) as a main component, the stress caused by the difference in thermal expansion between the wiring board and the semiconductor element is alleviated. I can't do it. For this reason, in the semiconductor substrate, there is a problem that a crack is generated in the interlayer insulating film constituting the circuit formed under the electrode and is destroyed.

  Further, Patent Document 1 discloses a structure aiming at such stress relaxation. However, since a columnar bump made of Cu (copper) is used, the bump itself is a hard material, and the bump It is difficult to relieve stress due to deformation. Therefore, there is a problem that stress relaxation cannot be sufficiently achieved only by increasing the standoff and improving the filling property of the underfill resin, and cracks are generated in the interlayer insulating film.

  Furthermore, Patent Documents 2 and 3 propose a structure in which a stress relaxation layer made of an insulating resin is provided in the vicinity of a solder connection portion. Specifically, Patent Document 2 discloses such a structure as a semiconductor element. Patent Document 3 is provided on the wiring board side. However, it is necessary to configure so as to obtain conduction with the electrodes on the wiring board. For this reason, in Patent Document 2, a multilayer wiring structure is formed, and in Patent Document 3, a protruding electrode having a resin layer therein. Is configured.

  On the other hand, in patent document 4, the stress relaxation layer which consists of electroconductive resin is utilized, and stress relaxation is aimed at by a simpler structure compared with the case where insulating resin is used. However, in Patent Document 4, the conductive resin is supplied to the wiring board side. By the way, recently, as the package becomes thinner, it is necessary to reduce the thickness of the semiconductor element. Therefore, the back surface of the semiconductor element is polished with the bumps formed. For this reason, in the manufacturing process of the semiconductor element, external stress generated by polishing the back surface of the wafer may damage the interlayer insulating film through the bumps. As described above, in particular, in the backside polishing process of the semiconductor element, there is a problem that the interlayer insulating film constituting the circuit formed under the electrode of the semiconductor substrate is destroyed. Since the conductive resin as a layer is provided on the wiring board side, it is difficult to cope with such a problem.

  One of the causes is that, recently, with the miniaturization and high performance of semiconductor elements, fragile low-k (low dielectric constant) materials have been applied to interlayer insulating films constituting circuits. It is done. This is because the interlayer insulating film is more fragile than the conventional one, so that the durability is poor, and the interlayer insulating film itself is cracked and easily broken.

  The present invention has been made in view of such a problem, and alleviates external stress generated in the manufacturing process of a semiconductor element, particularly in the back surface polishing process of the semiconductor element, and reduces damage to the interlayer insulating film constituting the circuit. An object of the present invention is to provide a semiconductor element having a bump structure that can be formed, a method for manufacturing the same, a semiconductor device having the semiconductor element, and a method for manufacturing the same.

The semiconductor device according to the present onset Ming, a semiconductor substrate, an electrode formed on the semiconductor substrate, a cover coat film which is provided with an opening on the electrode is formed on the semiconductor substrate formed the upper electrode And a first adhesion layer formed on the electrode including the opening, and a conductive portion formed on the electrode through the first adhesion layer and having a flat portion formed on at least a part of the surface thereof. A conductive resin layer, a second adhesion layer formed on the flat portion of the conductive resin layer, and a metal bump formed on the second adhesion layer, and the conductive resin layer Contains first alloy particles and second alloy particles having a low melting point alloy phase lower than the melting point of the first alloy, and the first alloy particles and the second alloy particles are It is characterized by having electrical conductivity by bonding between metals.

  The metal bump may be a columnar bump made of copper (Cu). Alternatively, the metal bump may be a solder bump containing tin (Sn) as a main component.

  The first and second adhesion layers may each be a single layer of titanium (Ti), titanium nitride (TiN), titanium (Ti) -tungsten (W) alloy, or copper (Cu), or one or a plurality of types. It is possible to form a stack of these layers.

  The semiconductor device according to the present invention includes the semiconductor element, a wiring substrate disposed opposite to the semiconductor element and having a pad at a position corresponding to the electrode of the semiconductor element, and between the semiconductor element and the wiring substrate. An underfill resin filled in the formed gap, and the elastic modulus and thermal expansion coefficient of the underfill resin are equal to the elastic modulus and thermal expansion coefficient of the resin constituting the conductive resin layer. It is characterized by that.

A method of manufacturing a semiconductor device according to the present invention includes a step of forming a first adhesion layer on an entire surface of a cover coat film having an electrode formed on a circuit formation surface of a semiconductor substrate and an opening on the electrode; A step of supplying a conductive resin from above the first adhesion layer to a position where the electrode is disposed, a step of curing the conductive resin, and a flatness of the surface without variation in height. have a, a step of grinding the electrically conductive resin, the conductive resin includes a first alloy particles, and a second alloy particles having a low low melting point alloy phase than the melting point of the first alloy contains, as the first alloy particles and the second alloy particles, characterized in that have a conductivity by the intermetallic bond.

A method for manufacturing a semiconductor device according to the present invention includes a step of forming a first adhesion layer on an entire surface of an electrode formed on a circuit formation surface of a semiconductor substrate and a cover coat film having an opening on the electrode; A step of supplying a conductive resin from above the first adhesion layer to a position where the electrode is disposed, a step of curing the conductive resin, and a flatness of the surface without variation in height. Grinding the conductive resin, removing the first adhesion layer, forming a second adhesion layer on a circuit formation surface of the semiconductor substrate, and the flat portion of the conductive resin. forming a metal bump, said removing the second contact layer, have a, the conductive resin includes a first alloy particles, low melting point lower than the melting point of the first alloy Second alloy particles having an alloy phase, the first alloy Characterized in that said particle second alloy particles have a conductivity by the intermetallic bond.

According to the invention of claim 1 of the present application, by forming a conductive resin layer between the electrode and the metal bump, against the external stress generated in the manufacturing process of the semiconductor element, particularly in the back surface polishing process of the semiconductor element, The conductive resin layer formed on the semiconductor element side functions as a buffer material, and damage to the interlayer insulating film constituting the circuit formed under the electrode can be reduced.
Further, according to the invention of claim 1 of the present application, characteristics such as the elastic modulus and thermal expansion coefficient of the underfill resin supplied to the connection portion between the semiconductor element and the wiring board, the elastic modulus of the conductive resin layer of the semiconductor element, and By setting the characteristics such as the coefficient of thermal expansion to the same level, the conductive resin layer can be similarly deformed and flexibly followed with respect to the deformation of the underfill resin caused by the thermal cycle or the like. Accordingly, the stress applied to the interlayer insulating film and the connection portion constituting the circuit formed under the electrode is reduced, and high reliability can be obtained.

  In addition, when the semiconductor element of the present invention is mounted and after the mounting, the stress is reduced by the deformation of the conductive resin layer against the stress caused by the difference in thermal expansion between the semiconductor element and the wiring board. Therefore, the stress on the interlayer insulating film constituting the circuit formed under the electrode is reduced, and the generation of cracks can be suppressed. At the same time, the occurrence of cracks in the connecting portion can be suppressed.

  Furthermore, since the metal bump is formed on the flat portion of the conductive resin layer via the second adhesion layer, there is no variation in the height of the metal bump, and a stable connection state is ensured in the mounting of the semiconductor element. It becomes possible.

  Hereinafter, embodiments of the present invention will be specifically described with reference to the accompanying drawings. First, a semiconductor element according to the first embodiment of the present invention will be described. FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device according to the first embodiment of the present invention.

  As shown in FIG. 1, in the semiconductor element according to the present embodiment, an electrode 2 is formed on a semiconductor substrate 1 on which a wiring layer (not shown) is formed, and the semiconductor substrate including the outer periphery of the electrode 2 A cover coat film 3 is formed on 1. That is, the semiconductor substrate 1 and the electrode 2 are covered with the cover coat film 3 having an opening on the electrode 2. A conductive resin layer 5 made of a conductive resin having a flat portion formed on the surface thereof is formed on the electrode 2 via the first adhesion layer 4. Furthermore, columnar bumps 7 made of, for example, copper (Cu) are formed on the flat portion of the conductive resin layer 5 via the second adhesion layer 6. Since the second adhesion layer 6 is formed on the flat portion of the conductive resin layer 5, the upper surface thereof is similarly flat. The first and second adhesion layers 6 are, for example, a single layer of titanium (Ti), titanium nitride (TiN), titanium (Ti) -tungsten (W) alloy, or copper (Cu), or one or a plurality of genus. A stack of layers can be used.

  In addition, as shown in FIG. 3, the conductive resin shown here includes, in the resin component 11, metal particles 10 made of a material such as silver (Ag) whose cross-sectional shape is, for example, an ellipse or a flake shape. After the resin component 11 is cured, the metal particles 10 come into contact with each other to obtain conductivity.

  Further, the characteristics of the resin component 11 are characteristics that satisfy the reliability standard of the semiconductor package, and the characteristics such as the thermal expansion coefficient and the elastic modulus after curing are between the semiconductor element and the wiring board when the semiconductor element is mounted. It is preferable to be equivalent to the characteristics of a resin that is filled and generally called an underfill material.

  Furthermore, a structure in which a layer made of solder and / or gold (Au) is formed on the surface of the columnar bump 7 made of copper (Cu), as shown here, and wetting prevention by a copper oxide film or the like on the side wall of the columnar bump 7 A structure in which a film is formed is also possible.

  Next, the operation of the present embodiment configured as described above will be described. Recently, as the package becomes thinner, the thickness of the semiconductor element needs to be reduced. Therefore, the back surface of the semiconductor element is polished with the bumps formed. For this reason, in the manufacturing process of the semiconductor element, in particular, in the back surface polishing process of the semiconductor element, external stress is generated at the bump bonding portion. In this embodiment, the conductive resin layer 5 formed on the semiconductor element side is Such external stress is relieved. Further, the temperature of the semiconductor substrate and the wiring substrate changes due to a thermal cycle such as a heat treatment in the assembly process of the semiconductor device. Since the thermal expansion coefficients of the semiconductor substrate and the wiring substrate are different, the thermal expansion amounts are also different from each other. As a result, an external stress is applied between the semiconductor substrate and the wiring substrate via the columnar bumps 7. However, at that time, the external stress is relieved by the deformation of the conductive resin layer 5 formed on the semiconductor element side.

  In the present embodiment, a conductive resin layer 5 having a flat portion on the upper surface thereof is formed on the electrode 2 via a first adhesive layer, and further, a second adhesive is formed on the flat portion of the conductive resin layer 5. Columnar bumps 7 are formed through the layers. Thus, by forming the conductive resin layer 5 between the electrode 2 and the columnar bump 7, the semiconductor element side against the external stress generated in the manufacturing process of the semiconductor element, particularly in the back surface polishing process of the semiconductor element. The conductive resin layer 5 formed in this way functions as a buffer material, and damage to the interlayer insulating film in the semiconductor substrate 1 can be reduced.

  Further, in the mounting form of the present embodiment, the stress is relieved by the deformation of the conductive resin layer 5 against the stress generated by the difference in thermal expansion between the semiconductor element and the wiring board after mounting and after mounting. Therefore, the stress on the interlayer insulating film constituting the circuit formed under the electrode 2 is reduced, and the generation of cracks can be suppressed. At the same time, the occurrence of cracks in the connecting portion can be suppressed.

  Furthermore, since the columnar bumps 7 are formed on the flat portion of the conductive resin layer 5 via the second adhesion layer 6, there is no variation in the height of the columnar bumps 7, and stable connection is possible in the mounting of the semiconductor element. The state can be secured.

  In addition, since the bumps are columnar bumps 7 made of copper (Cu) having a melting point higher than that of the solder, a standoff after mounting can be secured, so that stress can be mitigated and solder short defect with the adjacent bumps can be suppressed. It is possible to improve the fillability of the fill resin, which is effective for mounting a fine pitch.

  Next, a method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described. FIG. 6 is a cross-sectional view showing the method of manufacturing the semiconductor element according to the first embodiment in the order of steps. First, the electrode 2 formed on the circuit formation surface of the semiconductor substrate 1 and the entire surface on the cover coat film 3 formed on the semiconductor substrate 1 having an opening on the electrode 2 and including the end of the electrode 2. Then, the first adhesion layer 4 is formed by sputtering or the like (FIGS. 6A and 6B). More specifically, a cover coat film 3 made of, for example, SiON having a thickness of 1 μm and polyimide having a thickness of 6 μm is formed on a wiring layer (not shown) made of an aluminum alloy formed on the semiconductor substrate 1. To do. For this cover coat film 3, an opening having a diameter of, for example, 70 μm is formed on each of SiON and polyimide on, for example, a square electrode 2 having a side length of about 120 μm formed at the tip of the wiring layer. . Further, the first adhesion layer 4 is formed on the entire surface of the opening of the cover coat film 3 and the cover coat film 3 by sputtering, for example, in the order of titanium (Ti) and copper (Cu). At this time, the thickness of titanium (Ti) is, for example, 30 nm, and the thickness of copper (Cu) is, for example, 300 nm.

  Thereafter, a conductive material containing metal particles such as silver (Ag) which becomes the conductive resin layer 5 from above the first adhesion layer 4 by a printing method or the like in the portion where the cover coat film 3 on the electrode 2 is opened. Resin is supplied (FIG. 6C). In FIG. 6C, the conductive resin is supplied through the printing mask 5 using the printing squeegee 16. More specifically, a printing mask having a plate thickness of about 40 μm in which an opening having a diameter of 70 μm is formed at a position facing the electrode 2 formed on the semiconductor substrate 1, for example, metal particles: silver (Ag) A conductive resin having a glass transition temperature Tg of about 100 ° C., a thermal expansion coefficient of about 100 ppm / ° C., and an elastic modulus of about 5.8 GPa is supplied by a printing method. As other resin supply methods, it is also possible to supply only a necessary portion by a lithography method using a dispensing method, a supply method by an ink jet method, and a resin having photosensitive characteristics.

  Next, the conductive resin layer 5 is cured. At this time, the shape after curing of the conductive resin is a shape that is rounded about several μm wider than the opening of the cover coat film 3 on the electrode 2 due to the fluidity of the resin, and the height varies. Has occurred. Next, the resin layer 5 is ground so that there is no height variation and the resin surface becomes flat (FIG. 6D). Thereafter, the first adhesion layer 4 is removed by etching using the conductive resin layer 5 as a mask (FIG. 6E).

  Next, the second adhesion layer 6 is formed on the entire surface of the semiconductor substrate 1 on the circuit formation surface by sputtering (FIG. 6F). As the second adhesion layer 6, for example, titanium (Ti) having a thickness of 30 nm and copper (Cu) having a thickness of 300 nm are sequentially formed by a sputtering method. Next, after supplying the plating resist film 17 from above the second adhesion layer 6, an opening is formed at the position of the electrode 2 of the semiconductor substrate 1. At this time, the opening size of the plating resist film 17 is set so that the columnar bumps made of copper (Cu) have a predetermined size in consideration of the etching rate of copper (Cu) which is the second adhesion layer. adjust. Thereafter, columnar bumps 7 made of copper (Cu) are formed by electrolytic plating. At this time, the dimensions of the columnar bump 7 are, for example, about 88 μm in diameter and about 70 μm in height, and the columnar bump 7 is formed at a position in the flat portion of the conductive resin layer 5 (FIG. 6G). Finally, the plating resist film 17 is removed by ashing or the like, and the second adhesion layer 6 is removed by etching using the columnar bumps 7 as a mask (FIG. 6 (h)).

  In the manufacturing method of the present embodiment, the conductive resin layer 5 can be formed without any height variation by performing grinding of the conductive resin when forming the conductive resin layer. Therefore, by forming bumps on the flat portion of the conductive resin layer 5, it is possible to form the columnar bumps 7 having no height variation. Further, by forming the conductive resin layer 5 after supplying the first adhesion layer 4 to the entire surface of the circuit formation surface of the semiconductor element, the first adhesion layer 4 functions as a protective film. The conductive resin is prevented from directly adhering to the circuit surface of the semiconductor element from printing sag, grinding scraps, or the like during grinding. Therefore, contamination of the semiconductor element can be avoided.

  Next, a semiconductor device including the semiconductor element according to the first embodiment of the present invention will be described. FIG. 8 is a cross-sectional view showing a configuration of a semiconductor device including the semiconductor element according to the first embodiment of the present invention. In FIG. 8, the semiconductor element according to the first embodiment is mounted on a wiring substrate 18 in which pads 20 are formed at positions facing the electrodes 2 of the semiconductor substrate 1. That is, the solder 21 is supplied onto the pads 20 of the wiring board 18, and the columnar bumps 7 on the semiconductor substrate 1 side and the solder 21 are joined. Further, a solder resist film 19 is formed in a region on the wiring substrate 18 where the pad 20 is not formed. Furthermore, an underfill resin 22 is sealed in the gap between the semiconductor element of the present embodiment and the wiring board 18, that is, the space between the columnar bump 7 and the solder 21 which are connecting portions. Yes. The characteristics of the underfill resin 22 are preferably about the same as the characteristics of the conductive resin layer 5 formed on the semiconductor substrate side except for conductivity, and in particular, the thermal expansion coefficient after the underfill resin 22 is cured. And the elastic modulus is preferably equal to the thermal expansion coefficient and elastic modulus of the resin of the conductive resin layer 5.

  When solder is supplied to the surface of the columnar bump 7 on the semiconductor substrate 1 side, a structure in which gold (Au) plating is supplied onto the pad 20 of the wiring board 18 or a structure in which flux is supplied to the copper (Cu) surface is used. Can take. Further, at this time, it is possible to further secure a standoff by mounting by the local reflow method. As another connection structure, the metal combination of the surface of the columnar bump 7 on the semiconductor substrate 1 side and the surface of the pad 20 on the wiring substrate 18 side is gold (Au) plating, or thin solder plating and copper (Cu), or It is possible to combine thin solder platings, clean the surface and mount by diffusion bonding technology.

  In such a semiconductor device mounting structure, characteristics (thermal expansion coefficient, elastic modulus, etc.) excluding the conductivity of the underfill resin 22 supplied to the joint between the semiconductor element of the first embodiment and the wiring board 18. Is equivalent to the characteristics (thermal expansion coefficient, elastic modulus, etc.) of the resin of the conductive resin layer 5, so that the conductive resin layer is resistant to deformation of the underfill resin 22 resulting from a temperature cycle after mounting. 5 can flexibly deform and follow. Therefore, the stress applied to the interlayer insulating film and the connection part constituting the circuit formed under the electrode 2 can be reduced, and high reliability can be obtained. Further, when the diffusion bonding technique is applied, the surface of the columnar bump 7 is flattened, so that low stress mounting is possible.

  Next, a method for manufacturing the semiconductor device of this embodiment will be described with reference to FIG. The semiconductor substrate 1 on which the columnar bumps 7 made of copper (Cu) are formed is flip-chip mounted on a wiring substrate 18 in which pads 20 are arranged at positions facing the electrodes 2 of the semiconductor substrate 1. At this time, Sn—Ag—Cu solder 21 is supplied onto the pads 20 of the wiring board 18, and Sn—Ag solder is supplied to the surface of the columnar bumps 7 of the semiconductor substrate 1 by plating. Yes. At the time of mounting, the solder is melted and the pads 20 and the columnar bumps 7 made of copper (Cu) are connected. Thereafter, an underfill resin 22 having a glass transition temperature Tg: about 125 ° C., a thermal expansion coefficient: about 98 ppm / ° C., and an elastic modulus: about 7.7 GPa is enclosed in the connection portion between the semiconductor element and the wiring board 18. To do. Finally, the underfill resin 22 is thermally cured.

  Next, a semiconductor device according to a second embodiment of the present invention will be described with reference to FIGS. FIG. 2 is a cross-sectional view showing a configuration of a semiconductor device according to the second embodiment of the present invention, and FIG. 7 is a cross-sectional view showing a method of manufacturing the semiconductor device according to the second embodiment in the order of steps. In the first embodiment, columnar bumps made of copper (Cu) or the like are used, but as shown in FIG. 2, in this embodiment, the bump metal on the second adhesion layer 6 is a barrier metal. Solder bumps 9 formed through the layer 8 are used. In addition, since the other structure is the same as that of FIG. 1 which shows the structure of 1st Embodiment, the same code | symbol is attached | subjected to the same structure and the detailed description is abbreviate | omitted.

  As the solder material, tin (Sn) -silver (Ag) based solder containing tin (Sn) as a main component can be used. Here, the diameter of the solder bump 9 may be larger than the size of the resin layer 5, and the flat portion of the resin layer 5 is a portion where the solder bump 9 is connected to the second adhesion layer 6 through the barrier metal layer 8. It suffices if it is in the part and does not protrude from the flat part.

  In the present embodiment, by using a solder material softer than copper (Cu) as the metal bump material, the metal bump itself is easily deformed. Therefore, by deforming the metal bumps themselves, it is possible to improve the ability to relieve the stress caused by the difference in thermal expansion between the semiconductor element and the wiring board 1.

  Next, a method for manufacturing a semiconductor element according to the second embodiment of the present invention will be described. As shown in FIG. 7, the second embodiment is the same manufacturing method (FIG. 6 (a) to FIG. 6 (f)) as the first embodiment from FIG. 7 (a) to FIG. 7 (f). Form. Next, after the barrier metal layer 8 is formed on the second adhesion layer 6 by plating, a solder layer to be the solder bump 9 is formed by plating using the same plating resist film 17 (FIG. 7G). ). The barrier metal layer 8 prevents tin (Sn), which is the main component of the solder bump 9, from diffusing into the second adhesion layer 6 and the like. When tin (Sn) diffuses into the second adhesion layer 6 or the like, a hard and brittle alloy layer is formed, which causes a decrease in reliability. Therefore, the barrier metal layer 8 is formed of a metal such as tin (Sn) and nickel (Ni) that is difficult to diffuse. Finally, the second adhesive layer 6 is etched using the solder layer to be the solder bumps 9 as a mask, and the semiconductor substrate 1 is heated to form the spherical solder bumps 9 (FIG. 7 (h)). . In FIG. 7, solder bumps are formed by electrolytic plating. However, after forming the barrier metal layer 8, a solder ball is mounted or solder is supplied by printing, and then the solder is melted to form the bump. Also, solder bumps can be formed.

  In the manufacturing method of the present embodiment, since the conductive resin layer 5 made of a conductive resin is flattened by grinding, variation in the height of the spherical solder bumps 9 formed immediately thereon can be eliminated.

  A semiconductor device including the semiconductor element of the present embodiment can be configured in the same manner as in the first embodiment. That is, in FIG. 8, the semiconductor element of the second embodiment may be used instead of the semiconductor element of the first embodiment. Specifically, instead of the columnar bumps 7 made of copper (Cu) or the like, By providing the solder bump 9 via the barrier metal layer 8, the semiconductor device of this embodiment can be configured.

  The semiconductor device of this embodiment can secure a standoff after connection by mounting a semiconductor element on a wiring board by a local reflow method. In addition, stress relaxation is achieved from the three synergistic effects of securing the standoff and following the conductive resin layer 5 on the semiconductor element side with respect to the underfill resin as in the first embodiment, and the deformation of the solder bump 9 itself. As a result, connection reliability can be improved.

  Next, a third embodiment of the present invention will be described in detail with reference to FIG. FIG. 4 is a cross-sectional view illustrating a configuration of a conductive resin that is a material of the conductive resin layer according to the third embodiment. In this embodiment, the difference from the first and second embodiments is that a conductive resin containing metal particles 10 and metal nanoparticles 12 is used for the conductive resin layer 5 (see FIG. 4). As shown in FIG. 4, the conductive resin used in the present embodiment is made of a material such as silver (Ag) having a cross-sectional shape of, for example, an ellipse or a flake shape, and has a particle diameter of 0.1 to 0.1. The resin component 11 contains metal particles 10 having a diameter of about 5.0 μm and metal nanoparticles 12 having a particle diameter of about 1 to 20 nm. A large number of metal nanoparticles 12 are gathered between the metal particles 10 adjacent to each other so as to achieve conduction between the metal particles 10.

  In the present embodiment, the metal nanoparticles 12 are sintered during the heat treatment in the conductive resin layer 5 forming step, and the connection between the metal particles 10 is obtained. Therefore, it is possible to obtain stable conductivity between the electrode and the conductive resin layer and between the conductive resin layer and the metal bump by connecting not only the metal particles 10 but also the metal nanoparticles 12. It becomes. In addition, as a ratio with respect to the metal particle 10 of the metal nanoparticle 12 contained in the conductive resin layer 5, (the content mass of the metal nanoparticle) / (the content mass of the metal nanoparticle + the content mass of the metal particle) is 10 to 70. It is preferable to be in the range of mass%. Thus, by containing the metal nanoparticles 12, the metal particles 10 can be bonded to each other by the fusion reaction of the metal nanoparticles 12, and the conductivity is further improved. Other configurations, operations, and effects are the same as those in the first and second embodiments.

  Next, a fourth embodiment of the present invention will be described in detail with reference to FIG. FIG. 5 is a cross-sectional view illustrating a configuration of a conductive resin that is a material of the conductive resin layer according to the fourth embodiment. In the present embodiment, the difference from the first, second and third embodiments is that the conductive resin layer 5 is mixed with two kinds of particles, that is, a mother alloy particle 13 and an alloy particle 14 having a low melting point alloy phase. The conductive metal bond type conductive resin made is used (FIG. 5).

  In this embodiment, the mother alloy particles 13 and the alloy particles 14 having a low melting point alloy phase react during the heat treatment in the resin layer forming step, and are bonded between metals. The mother alloy particles 13 are made of Cu, for example, and the alloy particles 14 having a low melting point alloy phase are made of Sn, for example. Furthermore, heat resistance is ensured by changing the alloy phase due to thermal diffusion and increasing the melting point. Therefore, the conductivity between the electrode and the conductive resin layer and between the conductive resin layer and the metal bump can be improved as compared with the first, second, and third embodiments. Other configurations, operations, and effects are the same as those in the first, second, and third embodiments.

It is sectional drawing which shows the structure of the semiconductor element which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor element which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows the structure of the conductive resin which is the material of the conductive resin layer in 1st Embodiment. It is sectional drawing which shows the structure of the conductive resin which is the material of the conductive resin layer in 3rd Embodiment. It is sectional drawing which shows the structure of the conductive resin which is the material of the conductive resin layer in 4th Embodiment. It is sectional drawing which shows the manufacturing method of the semiconductor element which concerns on 1st Embodiment in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor element which concerns on 2nd Embodiment in process order. It is sectional drawing which shows the structure of the semiconductor device provided with the semiconductor element which concerns on the 1st Embodiment of this invention. It is an example of the structure of the conventional semiconductor element which uses a flip chip type solder bump. 1 is a cross-sectional view schematically showing a conventional flip-chip semiconductor device based on FIG. 1 described in Patent Document 1. FIG. FIG. 10 is a cross-sectional view showing a manufacturing process of the conventional semiconductor element shown in FIG. 9.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 101; Semiconductor substrate 2, 102; Electrode 3, 103; Cover coat film 4; First adhesion layer 5; Conductive resin layer 6; Second adhesion layer 7; 109; Solder bump 10; Metal particle 11; Resin component 12; Metal nanoparticle 13; Master alloy particle 14; Alloy particle having low melting point alloy phase 15; Printing mask 16; Wiring board 19; solder resist film 20; pad 21; solder 22; underfill resin 23; wetting prevention film 24; dry film 104;

Claims (6)

A semiconductor substrate, an electrode formed on the semiconductor substrate, a cover coat film formed on the semiconductor substrate on which the electrode is formed and provided with an opening on the electrode, and the electrode including the opening A first adhesion layer formed thereon, a conductive resin layer formed on the electrode through the first adhesion layer and having a flat portion formed on at least a part of the surface thereof; and the conductive resin A second adhesion layer formed on the flat portion of the layer, and a metal bump formed on the second adhesion layer, and the conductive resin layer includes first alloy particles, Second alloy particles having a low-melting-point alloy phase lower than the melting point of the first alloy, and the first alloy particles and the second alloy particles form an intermetallic bond, thereby providing conductivity. A semiconductor device comprising: The semiconductor element according to claim 1, wherein the metal bumps are columnar bumps made of copper (Cu). The semiconductor element according to claim 1, wherein the metal bump is a solder bump containing tin (Sn) as a main component. The first and second adhesion layers may each be a single layer of titanium (Ti), titanium nitride (TiN), titanium (Ti) -tungsten (W) alloy, or copper (Cu), or one or more of them. 4. The semiconductor element according to claim 1, wherein the semiconductor element is a stacked layer. A step of forming a first adhesion layer on the entire surface of the electrode formed on the circuit formation surface of the semiconductor substrate and a cover coat film having an opening on the electrode; and the first adhesion layer at a position where the electrode is disposed. A step of supplying a conductive resin from above the adhesion layer, a step of curing the conductive resin, and a step of grinding the conductive resin so that the surface is flat without variation in height. And the conductive resin contains first alloy particles and second alloy particles having a low melting point alloy phase lower than the melting point of the first alloy, and the first alloy particles and the A method for manufacturing a semiconductor element, wherein the second alloy particles have conductivity by intermetallic bonding. A step of forming a first adhesion layer on the entire surface of the electrode formed on the circuit formation surface of the semiconductor substrate and a cover coat film having an opening on the electrode; and the first adhesion layer at a position where the electrode is disposed. A step of supplying a conductive resin from above the adhesion layer, a step of curing the conductive resin, a step of grinding the conductive resin so that its surface is flat without variation in height, and Removing the first adhesion layer; forming a second adhesion layer on the circuit forming surface of the semiconductor substrate; forming metal bumps on the flat portion of the conductive resin; 2, and the conductive resin includes first alloy particles and second alloy particles having a low melting point alloy phase lower than the melting point of the first alloy. Containing, the first alloy particles and the second alloy particles are intermetallic The method of manufacturing a semiconductor device characterized by having conductivity by a slip.

Images