CN116403989B - IC substrate, preparation method and electronic package using same - Google Patents
IC substrate, preparation method and electronic package using same Download PDFInfo
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- CN116403989B CN116403989B CN202310671893.1A CN202310671893A CN116403989B CN 116403989 B CN116403989 B CN 116403989B CN 202310671893 A CN202310671893 A CN 202310671893A CN 116403989 B CN116403989 B CN 116403989B
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- substrate
- metal bump
- forming
- support body
- groove
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- 239000000758 substrate Substances 0.000 title claims abstract description 97
- 238000002360 preparation method Methods 0.000 title description 4
- 239000002184 metal Substances 0.000 claims abstract description 77
- 229910052751 metal Inorganic materials 0.000 claims abstract description 77
- 238000005520 cutting process Methods 0.000 claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 13
- 238000000151 deposition Methods 0.000 claims description 6
- 238000005240 physical vapour deposition Methods 0.000 claims description 5
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 238000009713 electroplating Methods 0.000 claims description 4
- 230000008018 melting Effects 0.000 claims description 4
- 238000002844 melting Methods 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 239000012212 insulator Substances 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- 238000004806 packaging method and process Methods 0.000 abstract description 2
- 230000008021 deposition Effects 0.000 description 4
- 238000004891 communication Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention belongs to the technical field of integrated circuit packaging, and particularly relates to an IC (integrated circuit) substrate, which comprises a rewiring layer, a substrate for bearing the rewiring layer and a metal bump formed on the rewiring layer, wherein the substrate is prepared by the following steps: forming a substrate groove on the substrate around a position where a metal bump is to be formed; forming a support body higher than the upper surface of the substrate on the substrate groove; forming a metal bump on the substrate at a position to be formed with the metal bump surrounded by the support; cutting a support body groove from the upper surface of the support body; forming a dielectric wall block in the support body groove; and wherein the dielectric block is not lower than the metal bump in the height direction and is not in contact with the metal bump. The invention also discloses an electronic package applying the IC substrate, which has better mechanical and electrical reliability and reduces the manufacturing difficulty.
Description
Technical Field
The present invention relates to the field of Integrated Circuit (IC) packaging technology, and in particular, to an IC substrate, a method for manufacturing the same, and an electronic package using the same.
Background
In IC packaging technology, a redistribution layer (Redistribution layer, RDL) is often used. A plurality of metal BUMPs (BUMP) are formed on the RDL with very small gaps (micron-sized) but independent of each other. In different testing and use environments, metal bumps may oxidize or deform, degrading the insulation between the bumps to the point that failures such as electromigration or micro-leakage (mismatching) occur, and disabling the package.
Some schemes have emerged to protect the rewiring layer structure, such as chinese patent No. 111128755B, which forms a blanket protective seed layer and dielectric layer over the metal blocks of the RDL substrate. And discloses a method for forming the microstructure. However, in this scheme, the seed layer and the dielectric layer are made to completely cover the microstructure of the re-wiring layer, and then deep grooves are cut to restore the outer contour of the re-wiring layer to the original separated bump structure. The gaps between the metal blocks are very small, after the gaps are completely covered by the seed layer and the dielectric layer, the observation and reference of the gap positions are lost, the cost of cutting the grooves at the positions of the original gaps is greatly increased, meanwhile, the possibility of accidentally damaging the bumps is greatly increased, and the overall packaging yield is reduced.
Disclosure of Invention
First technical problem
In view of the above state of the art, the present invention is directed to the following technical problems:
and the manufacturing difficulty and the yield of finished products of the rewiring layer protection structure are reduced.
(II) technical scheme
In order to solve the technical problems, the invention provides the following technical scheme:
an IC substrate comprising a rerouting layer, a substrate carrying the rerouting layer, and a metal bump formed on the rerouting layer is made by:
s1, forming a substrate groove on the substrate around a position where a metal bump is to be formed;
s2, forming a supporting body higher than the upper surface of the substrate on the substrate groove;
s3, forming metal bumps at positions, which are surrounded by the support body and are to be formed with the metal bumps, on the substrate;
s4, cutting a support body groove from the upper surface of the support body;
s5, forming a dielectric wall block in the support body groove;
and wherein the dielectric block is not lower than the metal bump in the height direction and is not in contact with the metal bump.
As a preferable embodiment of the IC substrate according to the present invention, wherein: the side surface of the metal bump is closely contacted with the supporting body.
As a preferable embodiment of the IC substrate according to the present invention, wherein: the support is a non-conductive insulator.
As a preferable embodiment of the IC substrate according to the present invention, wherein: the support body is formed by one of chemical vapor deposition, physical vapor deposition, ion implantation and the like.
As a preferable embodiment of the IC substrate according to the present invention, wherein: the metal bump is a copper block and is formed by one of an electroplating method, a deposition method or a laser melting method.
As a preferable embodiment of the IC substrate according to the present invention, wherein: the side surface of the dielectric wall block is tightly contacted with the inner wall of the supporting body groove.
The preparation method of the IC substrate comprises the following steps:
s1, forming a substrate groove on the substrate around a position where a metal bump is to be formed;
s2, forming a supporting body higher than the upper surface of the substrate on the substrate groove;
s3, forming metal bumps at positions, which are surrounded by the support body and are to be formed with the metal bumps, on the substrate;
s4, cutting a support body groove from the upper surface of the support body;
s5, forming a dielectric wall block in the support body groove;
the IC substrate includes a re-wiring layer, a substrate carrying the re-wiring layer, and a metal bump formed on the re-wiring layer, and wherein the dielectric wall block is not lower than the metal bump in a height direction and is not in contact with the metal bump.
The invention also discloses an electronic package applying the IC package substrate.
(III) beneficial effects
The invention relates to an IC substrate, a preparation method and an electronic package applying the same, wherein the IC substrate comprises a re-wiring layer, a substrate for bearing the re-wiring layer and a metal bump formed on the re-wiring layer, and the IC substrate is prepared by the following steps: forming a substrate groove on the substrate around a position where a metal bump is to be formed; forming a support body higher than the upper surface of the substrate on the substrate groove; forming a metal bump on the substrate at a position to be formed with the metal bump surrounded by the support; cutting a support body groove from the upper surface of the support body; forming a dielectric wall block in the support body groove; and wherein the dielectric block is not lower than the metal bump in the height direction and is not in contact with the metal bump. The invention has better mechanical and electrical reliability and reduces the manufacturing difficulty.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to the structures shown in these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of an IC substrate with a protection structure according to the present invention;
FIG. 2 is a schematic diagram showing steps of a method for manufacturing an IC substrate according to the present invention;
reference numerals:
1-substrate
2-substrate groove
3-support
4-metal bump
5-support groove
6-dielectric wall blocks.
Detailed Description
The following description will be made clearly and fully with reference to the technical solutions in the embodiments, and it is apparent that the described embodiments are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The technical schemes described in the embodiments of the present invention may be arbitrarily combined without any collision. The invention is further illustrated below with reference to examples.
As shown in fig. 1-2, an IC substrate according to the present invention, which includes a re-wiring layer, a substrate 1 carrying the re-wiring layer, and a metal bump 4 formed on the re-wiring layer, is manufactured by the steps of:
s1, forming a substrate groove 2 on the substrate 1 around a position where a metal bump 4 is to be formed;
s2, forming a supporting body 3 which is higher than the upper surface of the substrate on the substrate groove 2;
s3, forming metal bumps 4 on the substrate 1 at positions, which are surrounded by the supporting body 3 and are to be formed with the metal bumps 4;
s4, cutting a support body groove 5 from the upper surface of the support body 3;
s5, forming a dielectric wall block 6 in the support body groove 5;
and wherein the dielectric block 6 is not lower than the metal bump 4 in the height direction and is not in contact with the metal bump 4.
The present embodiment is directed to the difficulty that after the dielectric layer is used to cover the upper surface of the substrate, the metal bump cannot be repositioned to perform the dicing, and if there is an offset in the dicing, the offset will be an integral offset, so that the electrical performance between the metal bumps is unreliable.
In this embodiment, a ring groove is formed on the upper surface of the substrate and around the position where the metal bump is to be formed by mechanical cutting, and the groove is convenient for forming the support. On the surface of the very small substrate pattern, the structure may be formed by oxide deposition (chemical vapor deposition CVD, physical vapor deposition PVD), electrochemical deposition, or the like, for example, by cutting the support grooves at the locations where the support is to be formed, which greatly simplifies the process flow, and makes the support easier to position than the metal bump.
In the place where the support has been surrounded, metal bumps in RDL of the prior art are formed, such as by electroplating or deposition, laser melting, etc. as is commonly used in the art, since the place where they are formed is already surrounded by the support, no further etching is required, and the process is simplified and in further embodiments:
the side surface of the metal bump is closely contacted with the supporting body.
This makes it impossible to form the metal bump in any way, which has more bonding surface with the main body of the substrate, and which makes the metal bump more firm and less likely to fall off than the scheme of forming the cover layer on the metal bump.
The supporting body is a non-conductive insulator and mainly plays a role in reinforcing structural strength.
In the next step, a groove is cut in the upper surface of the support body to obtain a support body groove. Because the metal bumps are already formed, cutting based on machine vision or other similar technologies can be realized, and the cutting can be corrected in real time, so that higher cutting precision can be obtained easily by using simple equipment.
Similarly, the formation of dielectric blocks in the support trenches, whether by thermal oxidation or deposition, is simplified by the fact that in the trenches already cut. The dielectric block of this embodiment is similar to the dielectric layer (Intermetal Dielectric, IMD) of the prior art, but differs in that the typical intermediate dielectric layer is a low dielectric constant conductor that is in communication with the metal bump; in this embodiment, the side surface of the dielectric wall block is in close contact with the inner vertical surface of the supporting body groove, but the dielectric wall block is not in contact (conduction) with the metal bump, so that the design firstly further strengthens the mechanical structure, forms a capacitor with the metal bump, and reduces the problems of delay, crosstalk and the like of signal transmission.
In a specific embodiment, the support is formed by one of chemical vapor deposition, physical vapor deposition, ion implantation, and the like.
In a specific embodiment, the metal bump is a copper block and is formed by one of electroplating, deposition or laser melting.
In a specific embodiment, the side surface of the dielectric wall block is tightly contacted with the inner wall of the groove of the supporting body.
In a specific embodiment, a method for manufacturing an IC substrate according to the above embodiment is provided, and the method includes the following steps:
s1, forming a substrate groove 2 on the substrate 1 around a position where a metal bump 4 is to be formed;
s2, forming a supporting body 3 which is higher than the upper surface of the substrate on the substrate groove 2;
s3, forming metal bumps 4 on the substrate 1 at positions, which are surrounded by the supporting body 3 and are to be formed with the metal bumps 4;
s4, cutting a support body groove 5 from the upper surface of the support body 3;
s5, forming a dielectric wall block 6 in the support body groove 5;
the IC substrate includes a re-wiring layer, a substrate 1 carrying the re-wiring layer, and metal bumps 4 formed on the re-wiring layer, and wherein the dielectric wall blocks 6 are not lower than the metal bumps 4 in the height direction and are not in contact with the metal bumps 4.
The invention also discloses an electronic package applying the IC package substrate.
The IC substrate comprises a re-wiring layer, a substrate for bearing the re-wiring layer and a metal bump formed on the re-wiring layer, and is prepared by the following steps: forming a substrate groove on the substrate around a position where a metal bump is to be formed; forming a support body higher than the upper surface of the substrate on the substrate groove; forming a metal bump on the substrate at a position to be formed with the metal bump surrounded by the support; cutting a support body groove from the upper surface of the support body; forming a dielectric wall block in the support body groove; and wherein the dielectric block is not lower than the metal bump in the height direction and is not in contact with the metal bump. The invention has better mechanical and electrical reliability and reduces the manufacturing difficulty.
In the description of the present invention, furthermore, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present invention, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly, through intermediaries, or both, may be in communication with each other or in interaction with each other, unless expressly defined otherwise. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
For purposes of this disclosure, the terms "one embodiment," "some embodiments," "example," "a particular example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
While embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the invention.
Claims (8)
1. An IC substrate comprising a rerouting layer, a substrate carrying the rerouting layer, and a metal bump formed on the rerouting layer, characterized by being made by the steps of:
s1, forming a substrate groove on the substrate around a position where a metal bump is to be formed;
s2, forming a supporting body higher than the upper surface of the substrate on the substrate groove;
s3, forming metal bumps at positions, which are surrounded by the support body and are to be formed with the metal bumps, on the substrate;
s4, cutting a support body groove from the upper surface of the support body;
s5, forming a dielectric wall block in the support body groove;
and wherein the dielectric block is not lower than the metal bump in the height direction and is not in contact with the metal bump.
2. The IC substrate of claim 1, wherein: the side surface of the metal bump is closely contacted with the supporting body.
3. The IC substrate of claim 1, wherein: the support is a non-conductive insulator.
4. The IC substrate of claim 1, wherein: the support body is formed by one of chemical vapor deposition, physical vapor deposition and ion implantation.
5. The IC substrate of claim 1, wherein: the metal bump is a copper block and is formed by one of an electroplating method, a deposition method or a laser melting method.
6. The IC substrate of claim 1, wherein: the side surface of the dielectric wall block is tightly contacted with the inner wall of the supporting body groove.
7. A method for manufacturing an IC substrate according to any one of claims 1 to 6, characterized by comprising the steps of:
s1, forming a substrate groove on the substrate around a position where a metal bump is to be formed;
s2, forming a supporting body higher than the upper surface of the substrate on the substrate groove;
s3, forming metal bumps at positions, which are surrounded by the support body and are to be formed with the metal bumps, on the substrate;
s4, cutting a support body groove from the upper surface of the support body;
s5, forming a dielectric wall block in the support body groove;
the IC substrate includes a re-wiring layer, a substrate carrying the re-wiring layer, and a metal bump formed on the re-wiring layer, and wherein the dielectric wall block is not lower than the metal bump in a height direction and is not in contact with the metal bump.
8. An electronic package characterized by an IC substrate prepared by applying the IC substrate according to any one of claims 1 to 6 or the method for preparing an IC substrate according to claim 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310671893.1A CN116403989B (en) | 2023-06-08 | 2023-06-08 | IC substrate, preparation method and electronic package using same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310671893.1A CN116403989B (en) | 2023-06-08 | 2023-06-08 | IC substrate, preparation method and electronic package using same |
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| Publication Number | Publication Date |
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| CN116403989A CN116403989A (en) | 2023-07-07 |
| CN116403989B true CN116403989B (en) | 2023-09-15 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006310426A (en) * | 2005-04-27 | 2006-11-09 | Rohm Co Ltd | Semiconductor chip, electrode structure thereof and its forming method |
| JP2008047677A (en) * | 2006-08-15 | 2008-02-28 | Nec Corp | Semiconductor element and its manufacturing method, and semiconductor device and its manufacturing method |
| CN101599477A (en) * | 2008-06-06 | 2009-12-09 | 恩益禧电子股份有限公司 | Semiconductor device and make the method for this semiconductor device |
| CN111146170A (en) * | 2019-12-30 | 2020-05-12 | 颀中科技（苏州）有限公司 | Packaging structure and forming method thereof |
| CN113892173A (en) * | 2019-05-28 | 2022-01-04 | 苹果公司 | Fine-pitch metal bump and reinforcing structure of semiconductor packaging substrate |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6155571B2 (en) * | 2012-08-24 | 2017-07-05 | Tdk株式会社 | Terminal structure, and semiconductor element and module substrate having the same |
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- 2023-06-08 CN CN202310671893.1A patent/CN116403989B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006310426A (en) * | 2005-04-27 | 2006-11-09 | Rohm Co Ltd | Semiconductor chip, electrode structure thereof and its forming method |
| JP2008047677A (en) * | 2006-08-15 | 2008-02-28 | Nec Corp | Semiconductor element and its manufacturing method, and semiconductor device and its manufacturing method |
| CN101599477A (en) * | 2008-06-06 | 2009-12-09 | 恩益禧电子股份有限公司 | Semiconductor device and make the method for this semiconductor device |
| CN113892173A (en) * | 2019-05-28 | 2022-01-04 | 苹果公司 | Fine-pitch metal bump and reinforcing structure of semiconductor packaging substrate |
| CN111146170A (en) * | 2019-12-30 | 2020-05-12 | 颀中科技（苏州）有限公司 | Packaging structure and forming method thereof |
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| Publication number | Publication date |
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| CN116403989A (en) | 2023-07-07 |
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