KR20060054689A - Semiconductor device having backside input output terminal and method of manufacturing the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an input / output terminal on a back surface of a substrate and a method of manufacturing the same. The disclosed invention forms a conductive plug that penetrates into a semiconductor substrate through a first interlayer insulating film on a semiconductor substrate provided with a transistor. Next, a second interlayer insulating film is formed to insulate the metal wiring and the metal wiring connected to the upper surface of the conductive plug, thinning the rear surface of the semiconductor substrate to protrude the lower surface of the conductive plug against the rear surface of the semiconductor substrate, and then protruding conductive A rear insulating film is formed on the back surface of the semiconductor substrate to cover the lower surface of the plug, and a negative structure is formed on the rear insulating film to expose the lower surface of the conductive plug. Subsequently, an input / output terminal connected to the lower surface of the exposed conductive plug is formed on the back of the substrate. Therefore, the present invention does not have to flip the semiconductor device when the semiconductor device is connected for chip stacking and mounting, and can quickly conduct heat generated from the transistor.

Semiconductor, Board, Back, I / O Terminals, Studs, Bumps, Pads                                    

Description

A semiconductor device having a rear input / output terminal and a method of manufacturing the same {SEMICONDUCTOR DEVICE HAVING BACKSIDE INPUT OUTPUT TERMINAL AND METHOD OF MANUFACTURING THE SAME}

1A to 1N are cross-sectional views illustrating a method of manufacturing a semiconductor device having an input / output terminal on a rear surface of a substrate according to a first embodiment of the present invention;

2A to 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device having an input / output terminal on a rear surface of a substrate according to a second embodiment of the present invention;

3A to 3B are cross-sectional views illustrating a method of manufacturing a semiconductor device having an input / output terminal on a rear surface of a substrate according to a third embodiment of the present invention;

4A to 4D are cross-sectional views illustrating a method of manufacturing a rear metal wiring before forming a rear input / output terminal according to the present invention;

5A to 5C are cross-sectional views illustrating another method of manufacturing a back metal wiring before forming a back input / output terminal according to the present invention.

<Brief description of the major symbols in the drawings>

100 semiconductor substrate 200 transistor

300: first interlayer insulating film 310: hole

320 ': Internal insulation film 330': Liner

340 ': Metal body 360: Conductive plug

400: metal wiring 410: second interlayer insulating film

500: back insulation 510: engraved structure

520 ': barrier layer 530': conductive stud

540 ': UBM layer 560: bump

570 ': barrier layer 580': pad

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device having an input / output terminal on a back surface of a substrate and a method for manufacturing the same.

In general, an input / output (I / O) terminal of a semiconductor device is formed in the form of a bonding pad or a bump on an upper surface of a metal wiring process of the semiconductor device. In recent years, the metallization of semiconductor devices has been increasingly multilayered, and inter-layer dielectrics that insulate metallization have been replaced by low dielectric constant materials. However, the low dielectric constant material exhibits low mechanical strength and low thermal conductivity compared to the silicon oxide (SiO ₂ ) -based insulating film, which is used as an existing interlayer insulating film. As a result, an interlayer insulating layer supporting the pad may be destroyed during probe test and wire bonding through the pad formed on the upper surface of the semiconductor device, and the semiconductor device may be flipped and bonded. In this case, there arises a problem of not properly conducting heat generated in the transistor of the semiconductor device.

In addition, although the input / output and flip chip bonding using bumps have been expanded in recent years due to the increase in the number of input / output terminals and the reduction in package size, light through the upper surface of a semiconductor device such as a CMOS image sensor is increased. In the case where the upper surface of the semiconductor device is to be exposed to the outside, for example, it is impossible to flip and bond the semiconductor device. Therefore, the method of forming bumps on the upper surface of such a semiconductor device has been difficult to apply because of problems in bonding.

In addition, in chip stacking for multi chip manufacturing, if an input / output terminal is formed only on the upper surface of the semiconductor device, it is difficult to directly connect the chip and the chip, and thus stack the chips and stack the bonding wires after stacking the chips. Bonding to pads on the edges has been used to connect chips or stack chips across a substrate such as a PCB. As such, in chip stacking, when chips are connected through wiring or a printed circuit, inductance is increased to increase high frequency loss, crosstalk between wires is increased, and electromagnetic interference ( Electro Magnetic Interference) characteristics may also deteriorate.

An object of the present invention is to solve the problems of the prior art as described above, to increase the mechanical strength of the input and output terminal support layer, improve the thermal conductivity during input and output through the bump, and no bonding of the semiconductor device during bonding, and also multi The present invention provides a semiconductor device having an input / output terminal on a rear surface of a substrate to enable direct connection between chips during chip stacking for chip manufacturing.

Another object of the present invention is to provide a method of manufacturing a semiconductor device having the rear input / output terminals.

According to an aspect of the present invention, there is provided a semiconductor device including a semiconductor substrate including a transistor, a first interlayer insulating layer formed on the semiconductor substrate and having an inlet portion of a hole formed to a predetermined depth inside the semiconductor substrate; A second interlayer insulating film formed on the inner wall of the hole, a conductive plug formed of a liner and a metal body formed in the hole, and a second interlayer insulating film formed on the first interlayer insulating film and surrounding a metal wiring connected to an upper surface of the conductive plug; And a back insulating layer formed on the thinned back surface of the semiconductor substrate, the back insulating layer having an intaglio structure exposing a bottom surface of the conductive plug protruding with respect to the thinned back surface, and formed in the intaglio structure to the bottom surface of the conductive plug. A barrier layer connected to the barrier layer and formed on a surface of the barrier layer to form a barrier layer; Filling characterized in that it comprises a conductive stud.

In addition, in order to achieve the above object, the semiconductor device manufacturing method of the present invention according to the embodiment of the present invention, forming a first interlayer insulating film on a semiconductor substrate provided with a transistor, and from above the first interlayer insulating film Forming a hole through a first interlayer insulating film to a predetermined depth in the semiconductor substrate, forming an internal insulating film on the inner wall of the hole and an upper surface of the first interlayer insulating film, and forming a liner layer on the entire surface of the internal insulating film. Forming a conductive metal layer on the entire surface of the liner layer, filling the hole, and removing the conductive metal layer and the liner layer until at least the internal insulating layer is exposed to form a conductive plug filling the inside of the hole. And a metal wire connected to the upper surface of the conductive plug and the metal wire on the resultant product. Forming a second interlayer insulating film surrounding the substrate; thinning a rear surface of the semiconductor substrate to protrude a lower surface of the conductive plug with respect to a rear surface of the thinned semiconductor substrate; and a lower surface of the protruding conductive plug. Forming a back insulation film on the thinned back surface to cover the surface; forming a recess structure on the back insulation film to expose a bottom surface of the conductive plug; and a barrier on the inside of the intaglio structure and the bottom surface of the back insulation film. Forming a layer, forming a conductive stud layer on the surface of the barrier layer to fill the intaglio structure, and removing the conductive stud layer and the barrier layer until the backside insulating layer is exposed to remove the inside of the intaglio structure. Forming a conductive stud to fill.

The barrier layer may be formed of Ta, TaN, TaSiN, or a combination thereof, and may be formed by physical vapor deposition (PVD) or chemical vapor deposition (CVD). The conductive stud layer is preferably made of Cu and is formed through PVD or plating. The conductive stud layer and the barrier layer may be removed using a chemical mechanical polishing method.

In addition, a semiconductor device according to another embodiment of the present invention for achieving the above object, the first interlayer having a semiconductor substrate with a transistor and the inlet of the hole formed on the semiconductor substrate to a predetermined depth inside the semiconductor substrate A second insulating film, an inner insulating film formed on the inner wall of the hole, a conductive plug formed of a liner and a metal body formed in the hole, and a second wiring formed on the first interlayer insulating film and connected to an upper surface of the conductive plug. A back insulating film formed on the thin back surface of the semiconductor substrate and having an intaglio structure exposing a bottom surface of the conductive plug protruding from the thin back surface, the inside of the intaglio structure and adjacent to the intaglio structure; It is formed on the bottom surface of the back insulating film and connected to the bottom surface of the exposed conductive plug UBM (Under Bump Metal) layer and further characterized in that it comprises a bump formed on the UBM layer.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device of the present invention, the method including forming a first interlayer insulating film on a semiconductor substrate provided with a transistor; Forming a hole through a first interlayer insulating film to a predetermined depth in the semiconductor substrate, forming an internal insulating film on the inner wall of the hole and an upper surface of the first interlayer insulating film, and forming a liner layer on the entire surface of the internal insulating film. Forming a conductive metal layer on the entire surface of the liner layer, filling the hole, and removing the conductive metal layer and the liner layer until at least the internal insulating layer is exposed to form a conductive plug filling the inside of the hole. And a metal wire and the metal wire connected to an upper surface of the conductive plug on the resultant. Forming a second interlayer insulating film surrounding a line, thinning a rear surface of the semiconductor substrate to protrude a lower surface of the conductive plug with respect to a rear surface of the thinned semiconductor substrate, and a lower portion of the protruding conductive plug Forming a back insulation film on the thinned back surface to cover a surface; exposing a bottom surface of the conductive plug by forming an intaglio structure on the back insulation film; Forming a UBM layer, exposing a portion of the UBM layer formed inside the intaglio structure and a lower surface of the back insulating layer adjacent to the intaglio structure, and masking the remainder with an insulator layer; Forming a conductive bump material and removing the insulator layer and the UBM layer masked by the insulator layer Characterized by forming a loop.

The UBM layer may be made of Ti, Ta, Cr, Ni, Cu, Pd, Au, or a combination thereof, and may be formed by PVD or plating. The bumps are formed by a plating method. When the soldering is not required, the bumps may be made of Au or Cu. In the case of solder bumps requiring reshaping through reflow, an alloy of metals selected from Pb, Sn, Sb, Cu, Ni, Ag, Bi, In, and Zn may be used.

In addition, a semiconductor device according to another embodiment of the present invention for achieving the above object, the first substrate having a semiconductor substrate with a transistor and the inlet of the hole formed on the semiconductor substrate to a predetermined depth inside the semiconductor substrate An interlayer insulating film, an inner insulating film formed on the inner wall of the hole, a conductive plug formed of a liner and a metal body formed in the hole, and a metal wiring formed on the first interlayer insulating film and connected to an upper surface of the conductive plug. A back insulating film formed on a thin back surface of the semiconductor substrate and having an intaglio structure exposing a bottom surface of the conductive plug protruding with respect to the thin back surface; Is formed on the bottom surface of the back insulating film and the lower surface of the exposed conductive plug It characterized in that it comprises a pad formed on the barrier layer and the barrier layer surface to be determined.

In addition, in order to achieve the above object, the semiconductor device manufacturing method of the present invention according to another embodiment, the step of forming a first interlayer insulating film on a semiconductor substrate provided with a transistor, and from above the first interlayer insulating film Forming a hole through the first interlayer insulating film to a predetermined depth in the semiconductor substrate, forming an internal insulating film on the inner wall of the hole and an upper surface of the first interlayer insulating film, and a liner layer on the entire surface of the internal insulating film Forming a conductive metal layer on the entire surface of the liner layer, filling the hole, and removing the conductive metal layer and the liner layer until at least the internal insulating layer is exposed to fill the hole. Forming a metal wire connected to an upper surface of the conductive plug on the resultant and the gold; Forming a second interlayer insulating film surrounding the wiring, thinning a rear surface of the semiconductor substrate to protrude a lower surface of the conductive plug with respect to a rear surface of the thinned semiconductor substrate, and a lower portion of the protruding conductive plug Forming a back insulation film on the thinned back surface to cover a surface; exposing a bottom surface of the conductive plug by forming an intaglio structure on the back insulation film; Forming a barrier layer, and forming a pad by removing the pad layer and the barrier layer in the remaining areas except for the lower surface area of the back insulation layer adjacent to the intaglio structure and the intaglio structure by a photo and etching process. It is characterized by including.

The barrier layer for forming the pad may be formed of Ti, TiN, Ta, TaN, or a combination thereof, and is formed by PVD. The pad layer may be made of Al or an Al alloy, or may be formed in a multilayer form composed of a combination of Ni, Ti, Cr, Cu, and Au, and may be formed by PVD or plating.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. However, embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. Accordingly, the shape and the like of the elements in the drawings are exaggerated to emphasize a more clear description, and the elements denoted by the same reference numerals in the drawings means the same elements.

1A to 1N are cross-sectional views illustrating a method of manufacturing a semiconductor device having an input / output terminal on a rear surface of a substrate according to a first embodiment of the present invention. Referring to these drawings, the manufacturing method of the first embodiment of the present invention proceeds as follows.

As shown in FIG. 1A, a first interlayer insulating layer 300 is formed on a semiconductor substrate 100 including a transistor. A Si substrate is generally used as a semiconductor substrate, but a silicon on insulator (SOI) substrate or a substrate including a Si layer whose lattice is modified by a SiGe epi layer may be used. The illustrated transistor is an example of a CMOS transistor. The field oxide film 210, the wells 220 and 230, the gate electrode 260 and the spacer 270, the source regions 240s and 250s may be formed on the semiconductor substrate 100. It is produced by forming the drain regions 240d and 250d and the like. As the transistor, various transistors such as Bipolar or BiCMOS as well as CMOS may be used. Since the semiconductor substrate and the transistor used in the present embodiment can be variously changed by those skilled in the art, a detailed description thereof will be omitted. After the transistor formation is completed, a first interlayer insulating film 300 is formed on the semiconductor substrate 100 to insulate the gate electrode 260 and the source and drain regions 240s, 250s, 240d, and 250d. The first interlayer insulating layer 300 is generally formed of a material based on silicon oxide (SiO ₂ ) by a CVD method, and etch stop of a silicon nitride film (Si ₃ N ₄ ) or a silicon carbide film (SiC). It can be added as a layer or a diffusion barrier. In particular, the gap fill and gettering characteristics may be improved by doping elements such as boron (B) or phosphorus (P) when forming the SiO ₂ layer. The first interlayer insulating film 300 is planarized by chemical mechanical polishing to reduce defects in subsequent photographs and etching processes.

Referring to FIG. 1B, a hole 310 is formed from the upper portion of the first interlayer insulating layer 300 to the inside of the semiconductor substrate 100 through the first interlayer insulating layer 300. The diameter of the hole 310 is preferably about 0.2 μm to about 5 μm, and the depth d to the inside of the semiconductor substrate 100 is preferably about 8 μm to about 200 μm depending on the diameter of the hole. Thus, the first interlayer insulating film 300 has an inlet 312 of the hole 310. In this case, the region of the transistor through which the hole 310 passes may be a field oxide film 210 region or an active region as shown in the drawing. When passing through the active region, the gate electrode 260 may be formed. It passes through a dummy active region away from it so that the operation of the transistor is not disturbed. Along with the formation of the hole 310, a trench (not shown) for an alignment mark to be used in a backside process may be formed. The alignment mark may be formed when the rear structure is patterned. It is used for accurate alignment between the structure defined by 310 and the back structure.

Thereafter, the field oxide film 210, the wells 220 and 230, the gate electrode 260 and the spacer 270, and the source and drain regions 240s, 250s, 240d and 250d constituting the transistor are integrated for simplicity of the drawings. The transistor 200 will be described.

Referring to FIG. 1C, an internal insulating layer 320 is formed on an inner wall of the hole 310 and an upper surface of the first interlayer insulating layer 300 to expose a region exposed from the semiconductor substrate 100 to the inner wall of the hole 310. Insulate. The internal insulating layer 320 may be formed of a silicon oxide film (SiO ₂ ), a silicon nitride film (Si ₃ N ₄ ), a silicon carbide film (SiC), or a combination thereof (for example, Si ₃ N ₄ / SiO ₂ ). The internal insulating layer 320 is formed by depositing by CVD or atomic layer deposition (ALD).

Referring to FIG. 1D, a liner layer 330 is formed on the entire surface of the internal insulating layer 320, and then a conductive metal layer 340 is formed on the entire surface of the liner layer 330 to fill the hole 310. The liner layer 330 serves as a glue layer to allow the conductive metal layer 340 to adhere well to a surface of the internal insulating layer 320 and the valence forming the conductive metal layer 340 to the outside of the hole 310. It acts as a barrier to prevent spreading. The liner layer 330 may be made of Ti, TiN, TiSiN, Ta, TaN, TaSiN, or a combination thereof. The liner layer 330 may be formed using a PVD, CVD, or ALD method. The conductive metal layer 340 substantially fills the inside of the hole 310, and may be made of tungsten (W) formed by ALD or CVD, or copper (Cu) formed by PVD or plating. . In addition, although not shown, trenches necessary for fabricating the alignment mark for the backside process are also filled by the liner layer 330 and the conductive metal layer 340.

Referring to FIGS. 1E and 1F, as shown in FIG. 1E, the conductive metal layer 340 and the liner layer 330 are removed until the internal insulating layer 320 is exposed to remove the inside of the hole 310. Filling conductive plug 360 is formed. Alternatively, as illustrated in FIG. 1F, the conductive metal layer 340 and the liner layer 330 are sufficiently removed until the first interlayer insulating layer 300 is exposed, thereby leaving a residue of the conductive metal layer 340 or the liner layer 330 ( This further reduces the likelihood of residues remaining. The conductive metal layer 340 and the liner layer 330 may be removed using a chemical mechanical polishing method. When the conductive metal layer is made of W, an etch back or an etch back and a chemical mechanical polishing method may be used in parallel. Can be. The conductive plug 360 formed by the above method includes a liner 330 'having an outer shell contacting the inner insulation layers 320 and 320' and a metal body 340 'surrounded by the liner 330'. In the following drawings, for the sake of simplicity, the first interlayer insulating film 300 is exposed. In addition, although not shown, a liner and a metal body are formed in the trench required for fabricating the alignment mark to be used in the rear surface process.

Referring to FIG. 1G, a metal wire 400 connected to an upper surface of the conductive plug 360 on the first interlayer insulating film 300 and a second interlayer insulating film surrounding and insulated the metal wire 400 ( 410 is formed. Prior to this, although not shown, a W or Cu plug or a doped polysilicon pad electrode is formed in the first interlayer insulating layer 300 to contact the junction or gate electrode of the transistor. The metal wire 400 has a line form of Al or Cu or a via form of W or Cu. Lines formed of Al are formed through an etching process, and lines formed of Cu or vias of W and Cu are formed by damascene processes. The second interlayer insulating film 410 is made of a silicon oxide or a low dielectric constant material such as Applied Materials' Black Diamond, and a silicon nitride film or a silicon carbide film may be added to prevent diffusion of metal atoms. The second interlayer insulating layer 410 and the above layer may include metal wiring, a structure such as a capacitor and a poly plug in a DRAM, and a structure such as a resistor and an inductor in an RF chip. Since the structure in the layer of the second interlayer insulating film 410 or more can be variously changed by those skilled in the art according to the use of the semiconductor device, a detailed description thereof will be omitted.

Referring to FIGS. 1H and 1I, first, as shown in FIG. 1H, the back surface of the semiconductor substrate 100 is thinned, but the lower surface 362 of the conductive plug 360 is thinned. Protrudes against the backside 102 of 100. Although the drawing illustrates an example in which the metal body 340 'of the conductive plug 360 is exposed and protrudes, the thinning process may be controlled so that the liner 330' of the lower surface is not removed. Thinning is achieved by back grinding, chemical mechanical polishing or etching. A preferred thinning procedure on the back side of the semiconductor substrate 100 is to achieve first bulk removal by backgrinding followed by fine removal by chemical mechanical polishing or etching. When thinning the semiconductor substrate 100 very thin (for example, 20 μm or less), the semiconductor substrate 100 may be attached to a support (for example, another wafer) and then thinned. Upon fine removal by chemical mechanical polishing, the conductive plug 360 can be used as a polishing end point to control the polishing process. At this time, the back surface 102 of the semiconductor substrate 100 is lower than the lower surface 362 of the conductive plug 360 as shown through over polishing or additional etching after polishing at the polishing stop point. A recess is added, that is, a lower surface 362 of the conductive plug 360 is protruded, so that the semiconductor substrate 100 can be insulated in a subsequent process. On the other hand, when the polishing or etching selectivity of the semiconductor substrate 100 and the internal insulating layer 320 ′ in the thinning through chemical mechanical polishing or etching is large, as shown in FIG. 1I, the lower surface of the conductive plug 360 is It is covered with an internal insulating film 320 '. At this time, the thinning is sufficient so that the uncovered lower surface of the conductive plug 360 protrudes from the back surface 102 of the thinned semiconductor substrate 100. Also, although not shown, the alignment mark for the backside process is also exposed by the thinning process so as to be used in a subsequent patterning process.

Referring to FIGS. 1J and 1K, first, as shown in FIG. 1J, a rear insulating layer 500 is formed on the back side of the thinned semiconductor substrate in FIG. 1H, thereby lowering the lower surface 362 of the protruding conductive plug 360. After covering, the intaglio structure 510 is formed on the back insulation layer 500 through photolithography and etching to expose the lower surface 362 of the conductive plug 360. Meanwhile, referring to FIG. 1K, a rear insulating film 500 is formed on the rear surface of FIG. 1I, and then a lower surface of the conductive plug 360 is formed during an etching process for forming an intaglio structure 510 on the rear insulating film 500. The inner insulating layer 320 ′ is etched away at the same time to expose the lower surface of the conductive plug 360. The intaglio structure 510 is preferably in the shape of a circular or polygonal disk. At this time, although not shown, when the pattern for forming the intaglio structure 510 is formed with the help of the alignment mark manufactured together with the formation of the conductive plug 360, the alignment between the plug 360 and the intaglio structure 510 is aligned. Can be achieved. The back insulating layer 500 may be formed of a silicon oxide film, a silicon nitride film, a silicon carbide film, or a combination thereof, which is deposited by a CVD method, or a polymer such as BCB (BezoCycloButene) formed by curing followed by liquid coating.

Referring to FIG. 1L, a barrier layer 520 is formed on the inside of the intaglio structure 510 and the bottom surface 502 of the back insulation layer 500 in FIG. 1J to form a bottom surface of the exposed conductive plug 360. After connecting the 362 and the barrier layer 520, the conductive stud layer 530 is formed on the barrier layer 520 to fill the intaglio structure 510. The barrier layer 520 may be formed of Ta, TaN, TaSiN, or a combination thereof, and may be formed by PVD or CVD. The conductive stud layer 530 is preferably made of Cu and is formed by PVD or plating.

Referring to FIG. 1M, the conductive stud layer 530 and the barrier layer 520 are removed until the back insulation layer 500 is exposed to form a conductive stud 530 ′ which fills the inside of the intaglio structure 510. do. The conductive stud layer 530 and the barrier layer 520 may be removed using a chemical mechanical polishing method. When the conductive stud 530 ′ protrudes from the rear surface insulating film 500, the removal rate of the conductive stud layer 530 is increased when the barrier layer 520 is removed from chemical mechanical polishing. And a slurry lower than the polishing rate of the back insulation layer 500. For example, in the case of the back insulation layer 500 made of silicon oxide (SiO ₂ ), the barrier layer 520 made of Ta, and the conductive stud layer 530 made of Cu, Cu outside the intaglio structure 510 is removed. When removing Ta and SiO ₂ of a certain thickness with a Rodel CuS-1201 slurry, the polishing rate ratio of Cu: Ta: SiO ₂ is about 1: 4: 6, so the conductive stud 530 'made of Cu is as shown in FIG. 1N. Will protrude. Another method of protruding the conductive stud 530 ′ is that if the etching rate of the back insulation layer 500 is etched in an environment in which the etching rate of the rear insulating layer 500 is greater than the etching rate of the conductive stud 530 ′, the conductive stud 530 ′ is formed. The stud 530 'protrudes. For example, after the conductive stud 530 'is formed by chemical mechanical polishing in a structure composed of the above-described materials (SiO ₂ , Ta and Cu), the semiconductor substrate 100 is diluted with HF or BOE (Buffered Oxide Etchant). In the case of etching, the etching rate of the back insulation layer SiO ₂ is relatively high, so that the conductive stud 530 ′ may protrude.

As a result, in the first embodiment, as shown in FIG. 1M, the inlet portion 312 of the hole 310 formed on the semiconductor substrate 100 including the transistor 200 to a predetermined depth inside the semiconductor substrate 100 is provided. A first interlayer insulating film 300 having a structure is formed, and an internal insulating film 320 'is formed in the inner wall of the hole 310, and a liner 330' and a metal body 340 'are formed in the hole 310. A conductive plug 360 is formed on the first interlayer insulating film 300, and a metal interconnection 400 connected to an upper surface of the conductive plug 360 and a second interlayer insulation layer surrounding the metal interconnection 400 ( 410 is formed, and a backside insulating film 500 having an intaglio structure 510 exposing the bottom surface of the conductive plug 360 is formed on the thinned back surface of the semiconductor substrate 100, and the intaglio structure 510 is formed. ) A barrier layer 520 ′ is formed inside the exposed conductive plug 360 and connected to the lower surface of the exposed conductive plug 360. A barrier layer (520 ') the surface of the conductive stud (530 filling the interior of the concave structure 510', a semiconductor device, characterized in that a) is formed to be completed.

In the drawings of the above-described embodiment, one conductive plug 360 is formed per conductive stud 530 'for the purpose of simplicity of the drawing and is connected to the barrier layer 520', but for the purpose of reducing electrical resistance or rapid thermal conductivity, etc. A plurality of conductive plugs may be formed per conductive stud to connect to the barrier layer.

Through the above-described manufacturing method, a conductive stud may be formed on the rear surface of the substrate, and the conductive stud may thermally diffuse with a conductive stud formed on the upper surface of another semiconductor device during vertical connection between semiconductor devices such as chip stacking. It can be bonded (bonding) in the method, there is an advantage that the semiconductor device formed on the back of the conductive stud as described above does not need to flip. In addition, when the conductive stud is formed on the upper surface of the semiconductor device by the conventional method and the conductive stud is formed on the rear surface of the semiconductor device by the above-described method, the semiconductor device has an input / output terminal on the upper surface and the rear surface, respectively. This allows for direct stacking between chips without the need for wires or PCBs in stacking three or more chips.

2A to 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device having an input / output terminal on a rear surface of a substrate according to a second embodiment of the present invention. In the present embodiment, the process up to FIG. 1K of the first embodiment is the same, the same reference numerals are given to the same parts as the first embodiment, and redundant description is omitted.

Referring to FIG. 2A, the conductive plug 360 is formed on the semiconductor substrate 100 including the transistor 200 and the first interlayer insulating layer 300 in the same manner as shown in FIGS. 1A to 1K of the first embodiment. After that, an upper surface of the conductive plug 360 is connected to the metal wiring 400 on the first interlayer insulating film 300, and a lower surface of the conductive plug 360 is engraved on the rear insulating film 500 on the rear surface of the semiconductor substrate 100. 510 is formed and exposed.

Subsequently, an under bump metal (UBM) layer 540 is formed in the intaglio structure 510 of FIG. 1J and the lower surface of the back insulating layer 500 to form a lower surface 362 of the exposed conductive plug 360. The UBM layer 540 is connected. Subsequently, a portion of the UBM layer 540 formed in the intaglio structure 510 and the lower surface of the back insulation layer 500 adjacent to the intaglio structure 510 is exposed through a patterning process, and the rest of the insulator layer 550 is exposed. Mask with The UBM layer 540 may be made of Ti, Ta, Cr, Ni, Cu, Pd, Au, or a combination thereof, and may be formed by PVD or plating. As the insulator layer 550 for masking, an inorganic insulating material such as a silicon oxide film or a photoresist may be used. The inorganic insulating material is more thermally stable than the photoresist, and requires an additional process for removing the inorganic insulating material. It is preferable to use the photoresist as a non-conductor layer for masking if the subsequent process does not require a high temperature rise such as plating.

Referring to FIG. 2B, after the bump material is formed on the exposed surface of the UBM layer 540 by the plating method, the back surface is removed by removing the insulator layer 550 and the UBM layer 540 masked by the insulator layer. A bump 560 protruding from the insulating film 500 is formed. If plating is not required after plating, the bump material is preferably Au or Cu, and in the case of solder bumps requiring shaping through reflow, Pb, Sn, Alloys of metals selected from Sb, Cu, Ni, Ag, Bi, In, Zn (eg Pb-Sn or Sn-Ag-Cu) may be used. In the case of solder bumps, the bumps 560 may be reflowed to be shaped into bumps 560 'that are close to a spherical or hemispherical shape as shown in FIG. 2C.

As a result, in the second embodiment, as shown in FIG. 2B, the inlet portion 312 of the hole 310 formed on the semiconductor substrate 100 including the transistor 200 to a predetermined depth inside the semiconductor substrate 100 is provided. A first interlayer insulating film 300 having a structure is formed, and an internal insulating film 320 'is formed in the inner wall of the hole 310, and a liner 330' and a metal body 340 'are formed in the hole 310. A conductive plug 360 is formed on the first interlayer insulating film 300, and a metal interconnection 400 connected to an upper surface of the conductive plug 360 and a second interlayer insulation layer surrounding the metal interconnection 400 ( 410 is formed, and a backside insulating film 500 having an intaglio structure 510 exposing the bottom surface of the conductive plug 360 is formed on the thinned back surface of the semiconductor substrate 100, and the intaglio structure 510 is formed. The exposed conductivity on the bottom surface of the back insulation layer 500 adjacent to the recess structure 510. 'And is formed, the UBM layer (540 UBM layer 540' which is connected with the lower surface of the lug 360, the semiconductor device characterized in that the bumps 560 on) the surface to be formed is complete.

In the drawings of the above-described embodiment, one conductive plug 360 is formed per bump 560 for the purpose of simplifying the drawing, and is connected to the UBM layer 540 ', but each bump is used for the purpose of reducing electrical resistance or increasing thermal conductivity. A plurality of conductive plugs may be formed and connected to the UBM layer.

Bumps can be formed on the back surface of the substrate through the above-described manufacturing method, and these bumps can be mounted on a PCB or glass without flipping the semiconductor device. In addition, the bumps may be used for chip stacking. When the metal pads corresponding to the bumps are formed on the upper surface of another semiconductor device to form a stack, the two semiconductor devices are flipped when the bumps and the metal pads are bonded by soldering or the like. There is an advantage that can be connected directly without this.

3A and 3B are cross-sectional views illustrating a method of manufacturing a semiconductor device having an input / output terminal on a rear surface of a substrate according to a third embodiment of the present invention. In the present embodiment, the process up to FIG. 1K of the first embodiment is the same, the same reference numerals are given to the same parts as the first embodiment, and redundant description is omitted.

Referring to FIG. 3A, the conductive plug 360 is formed on the semiconductor substrate 100 including the transistor 200 and the first interlayer insulating layer 300 in the same manner as shown in FIGS. 1A to 1K of the first embodiment. Afterwards, an upper surface of the plug 360 is connected to the metal wiring 400 on the first interlayer insulating film 300, and a lower surface of the plug 360 is formed on the rear insulating film 500 on the rear surface of the semiconductor substrate 100. ) To form an exposure.

Subsequently, a barrier layer 570 is formed in the intaglio structure 510 of FIG. 1J and a lower surface of the back insulation layer 500 to form a bottom surface 362 and the barrier layer 570 of the exposed conductive plug 360. ) And then a pad layer 580 is formed on the surface of the barrier layer 570. Subsequently, the photoresist 590 masks an inner surface of the intaglio structure 510 and a lower surface area of the bottom insulating layer 500 adjacent to the intaglio structure 510 through a photolithography process. The barrier layer 570 may be formed of Ti, TiN, Ta, TaN, or a combination thereof, and may be formed through PVD. The pad layer 580 is made of Al or an Al alloy, or a multilayer form made of a combination of Ni, Ti, Cr, Cu, Au, and is formed through PVD or plating.

Referring to FIG. 3B, when the pad layer 580 and the barrier layer 570 outside the region masked by the photoresist 590 are etched away, the photoresist 590 is removed to electrically connect with the conductive plug 360. Pads 580 ′ connected to each other are formed in the intaglio structure 510 and on the bottom surface of the back insulating layer 500 adjacent to the intaglio structure 510.

As a result, in the third embodiment, as shown in FIG. 3B, the inlet portion 312 of the hole 310 formed on the semiconductor substrate 100 including the transistor 200 to a predetermined depth inside the semiconductor substrate 100 is provided. A first interlayer insulating film 300 having a structure is formed, and an internal insulating film 320 'is formed in the inner wall of the hole 310, and a liner 330' and a metal body 340 'are formed in the hole 310. A conductive plug 360 is formed on the first interlayer insulating film 300, and a metal interconnection 400 connected to an upper surface of the conductive plug 360 and a second interlayer insulation layer surrounding the metal interconnection 400 ( 410 is formed, and a backside insulating film 500 having an intaglio structure 510 exposing the bottom surface of the conductive plug 360 is formed on the thinned back surface of the semiconductor substrate 100, and the intaglio structure 510 is formed. The exposed conductivity on the bottom surface of the back insulation layer 500 adjacent to the recess structure 510. 'And is formed, wherein the barrier layer (a lower surface 570 and the barrier layer 570, which is connected of the lug 360 is a semiconductor device, characterized in that the surface of the pads 580') is formed it is to be completed.

In the drawings of the above-described embodiment, one conductive plug 360 is formed per pad 580 'for the purpose of simplifying the drawing, and is connected to the barrier layer 570', but the pad is used for the purpose of reducing electrical resistance or rapid thermal conduction. Multiple conductive plugs can be formed per one to connect to the barrier layer.

Through the above-described manufacturing method it is possible to form a pad on the back of the substrate. The pad made of Al or Al alloy can be used for probe testing and wire bonding of a semiconductor device like a conventional bonding pad. In the case of a semiconductor device in which a material having a weak mechanical strength, such as a low dielectric constant material, is used as an intermetallic insulating layer, the pad formed on the back side has an advantage that the substrate is a support layer and thus is not easily destroyed during probe testing or wire bonding. In addition, after the probe test, a process of forming a UBM layer on the pad surface and then forming a bump through plating may be further added. The multi-layer pad may be used to directly connect the two semiconductor devices by forming an uppermost layer of Au, Ni, or Cu, in which an oxide layer is not formed or easily removed, and bonding the bumps formed on other semiconductor devices during chip stacking.

In the above-described embodiments, only the case where the conductive plug and the rear input / output terminals are directly connected is illustrated, but the rear metal wiring may be added between the conductive plug and the rear input / output terminal for the connection between the conductive plugs or the position shift of the rear input / output terminals. Can be.

4A through 4D are cross-sectional views illustrating a method of adding a rear metal wiring using a damascene process in the above-described embodiments.

Referring to FIG. 4A, which illustrates a process after FIG. 1H, a rear insulating layer 500 is formed on a back side of the semiconductor substrate 100 thinned similarly to FIG. A trench 600 is formed to expose the bottom surface 362 of the conductive plug 360. Here, the trench 600 may expose the lower surface 362 of the conductive plug 360 and extend around to expose the lower surface of another conductive plug, although not shown.

Referring to FIGS. 4B and 4C, first, as shown in FIG. 4B, the wiring barrier layer 610 and the metal wiring layer 620 are sequentially formed on the lower surfaces of the trench 600 and the lower insulating layer 500. The trench 600 is buried. Subsequently, when the metal wiring layer 620 and the wiring barrier layer 610 are removed until the back insulation layer 500 is exposed by a chemical mechanical polishing method, the conductive plug 360 is formed inside the trench 600 as shown in FIG. 4C. A rear metal wiring 630 consisting of a wiring barrier layer 610 ′ and a metal wiring layer 620 ′ connected to the bottom surface of the bottom is completed. Although not shown, the bottom surface of the other conductive plugs may be connected by the rear metal wiring 630. The wiring barrier layer 610 may be formed of Ti, TiN, Ta, TaN, TaSiN, or a combination thereof. The metal wiring layer 620 is preferably made of W or Cu.

Referring to FIG. 4D, an insulating film 640 is formed on the entire rear surface of the resultant, and then an intaglio structure 650 is formed to form a rear input / output terminal through a photo and etching process, thereby forming the rear metal wiring 630. Expose The rear metal interlayer insulating film 640 may be formed of a silicon oxide film, a silicon nitride film, a silicon carbide film, or a combination thereof, or may be made of a polymer such as BCB (BezoCycloButene). Subsequent processes are the same as those of FIG. 1L of the first embodiment, FIG. 2A of the second embodiment, or FIG. 3A of the third embodiment and the subsequent processes according to the type of the rear input / output terminal. In this case, the exposed rear metal wiring 630 corresponds to the exposed conductive plug 360 in the first, second, and third embodiments described above, and the rear metal wiring insulating film 640 is formed on the rear insulating film 500. Corresponding.

The above-described method of forming the back metal wiring is made using a damascene process, and the back metal wiring can be formed by the etching method. 5A through 5C are cross-sectional views illustrating a method of adding a back metal wiring using an etching process in the above-described embodiments.

Referring to FIG. 5A, this illustrates a process after FIG. 1H. A back insulation film 500 is formed on the back surface of the semiconductor substrate 100 thinned in the same manner as in FIG. 1J, and then a first intaglio structure is formed on the back insulation film 500. 512 is formed to expose the bottom surface 362 of the conductive plug 360.

Referring to FIG. 5B, the wiring barrier layer 660 and the metal wiring layer 670 are sequentially formed on the lower surface of the exposed conductive plug 360 and the lower surface of the back insulation layer 500, and the region where wiring is to be formed. Masked with photoresist 680. The wiring barrier layer 660 may be formed of Ti, TiN TiSiN, or a combination thereof. The metal wiring layer 670 is preferably made of Al or Al alloy.

Referring to FIG. 5C, when the metallization layer 670 and the wiring barrier layer 660 are etched using the photoresist 680 as a mask, and the photoresist 680 is removed, the bottom surface of the conductive plug 360 is removed. The back metal wiring 690 including the wiring barrier layer 660 'and the metal wiring layer 670' connected to each other is completed. Although not shown, the bottom surface of the other conductive plugs may be connected by the rear metal wiring 690. Subsequently, an insulating film 700 between the rear metal wires is formed on the entire rear surface of the resultant metal so as to surround the rear metal wires, and then a second intaglio structure 710 is formed to form a rear input / output terminal through a photo and etching process. The wiring 690 is exposed. The rear metal interlayer insulating film 700 may be formed of a silicon oxide film, a silicon nitride film, a silicon carbide film, or a combination thereof, or may be made of a polymer such as BCB. Subsequent processes are the same as those of FIG. 1L of the first embodiment, FIG. 2A of the second embodiment, or FIG. 3A of the third embodiment and the subsequent processes according to the type of the rear input / output terminal. In this case, the exposed rear metal wiring 690 corresponds to the exposed conductive plug 360 in the first, second and third embodiments described above, and the rear metal wiring insulating film 700 is formed on the rear insulating film 500. Corresponding.

As described above, the present invention forms conductive studs or bumps on the rear surface of the substrate so that the semiconductor devices can be quickly flipped without the flip of the semiconductor devices when the semiconductor devices are connected for chip stacking and mounting. . In addition, the present invention can minimize the mechanical defects that may occur during the probe test and wire bonding by forming a pad on the back surface of the substrate, thereby making it possible to use a variety of intermetallic insulating material for the manufacture of semiconductor devices.

On the other hand, the present invention is not limited to the above-described embodiment, various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims to be described later.

Claims (43)

A semiconductor substrate provided with a transistor; A first interlayer insulating layer formed on the semiconductor substrate and having an inlet portion of a hole formed to a predetermined depth inside the semiconductor substrate; An internal insulating film formed on the inner wall of the hole; A conductive plug formed of a liner and a metal body formed in the hole; A second interlayer insulating film formed on the first interlayer insulating film and surrounding a metal wiring connected to an upper surface of the conductive plug; A back insulating layer formed on the thinned rear surface of the semiconductor substrate and having an intaglio structure exposing a bottom surface of the conductive plug protruding from the thinned rear surface; A barrier layer formed inside the engraved structure and connected to a bottom surface of the conductive plug; And And a conductive stud formed on a surface of the barrier layer to fill the inside of the intaglio structure. A semiconductor substrate provided with a transistor; A first interlayer insulating layer formed on the semiconductor substrate and having an inlet portion of a hole formed to a predetermined depth inside the semiconductor substrate; An internal insulating film formed on the inner wall of the hole; A conductive plug formed of a liner and a metal body formed in the hole; A second interlayer insulating film formed on the first interlayer insulating film and surrounding a metal wiring connected to an upper surface of the conductive plug; A back insulating layer formed on the thinned rear surface of the semiconductor substrate and having an intaglio structure exposing a bottom surface of the conductive plug protruding from the thinned rear surface; A UBM layer formed in the intaglio structure and on a bottom surface of the back insulation layer adjacent to the intaglio structure and connected to a bottom surface of the conductive plug; And And bumps formed on a surface of the UBM layer. A semiconductor substrate provided with a transistor; A first interlayer insulating layer formed on the semiconductor substrate and having an inlet portion of a hole formed to a predetermined depth inside the semiconductor substrate; An internal insulating film formed on the inner wall of the hole; A conductive plug formed of a liner and a metal body formed in the hole; A second interlayer insulating film formed on the first interlayer insulating film and surrounding a metal wiring connected to an upper surface of the conductive plug; A back insulating layer formed on the thinned rear surface of the semiconductor substrate and having an intaglio structure exposing a bottom surface of the conductive plug protruding from the thinned rear surface; A barrier layer formed in the intaglio structure and on a bottom surface of the back insulation layer adjacent to the intaglio structure and connected to a bottom surface of the conductive plug; And And a pad formed on the surface of the barrier layer. The method according to any one of claims 1 to 3, And the internal insulating film is formed of a silicon oxide film, a silicon nitride film, a silicon carbide film, or a combination thereof. The method according to any one of claims 1 to 3, And the liner constituting the conductive plug is made of Ti, TiN, TiSiN, Ta, TaN, TaSiN, or a combination thereof. The method according to any one of claims 1 to 3, The metal body constituting the conductive plug is made of W or Cu. The method according to any one of claims 1 to 3, And said back insulating film is made of a silicon oxide film, a silicon nitride film, a silicon carbide film, or a combination thereof. The method according to any one of claims 1 to 3, And said back insulating film is made of a polymer. The method of claim 1, The barrier layer is made of Ta, TaN, TaSiN or a combination thereof. The method of claim 1, And the conductive stud is made of Cu. The method of claim 1, At least one conductive plug bottom surface is connected to the barrier layer. The method of claim 1, And a back metal wiring is further formed between the bottom surface of the conductive plug and the conductive stud. The method of claim 2, The UBM layer is made of Ti, Ta, Cr, Ni, Cu, Pd, Au, or a combination thereof. The method of claim 2, The bump is made of Au or Cu semiconductor device. The method of claim 2, The bump is a semiconductor device, characterized in that consisting of a solder bump. The method of claim 15, The solder bump is made of an alloy of metals selected from Pb, Sn, Sb, Cu, Ni, Ag, Bi, In, Zn. The method of claim 2, At least one conductive plug bottom surface is connected to the UBM layer. The method of claim 2, And a back metal wiring is further formed between the bottom surface and the bump of the conductive plug. The method of claim 3, wherein The barrier layer is made of Ti, TiN, Ta, TaN or a combination thereof. The method of claim 3, wherein And the pad is made of Al or an Al alloy. The method of claim 3, wherein The pad is a semiconductor device, characterized in that the multi-layer form consisting of a combination of Ni, Ti, Cr, Cu, Au. The method of claim 3, wherein At least one conductive plug bottom surface is connected to the barrier layer. The method of claim 3, wherein And a back metal wiring is further formed between the bottom surface of the conductive plug and the pad. Forming a first interlayer insulating film on a semiconductor substrate provided with a transistor; Forming a hole from an upper portion of the first interlayer insulating layer to a predetermined depth in the semiconductor substrate through the first interlayer insulating layer; Forming an internal insulating film on the inner wall of the hole and an upper surface of the first interlayer insulating film; Forming a liner layer on the entire surface of the internal insulating film; Filling the hole by forming a conductive metal layer on the entire surface of the liner layer; Removing the conductive metal layer and the liner layer until at least the internal insulating layer is exposed to form a conductive plug filling the inside of the hole; Forming a metal interconnection connected to an upper surface of the conductive plug and a second interlayer insulating layer surrounding the metal interconnection on the resultant product; Thinning a rear surface of the semiconductor substrate to protrude a lower surface of the conductive plug with respect to a rear surface of the thinned semiconductor substrate; Forming a back insulation film on the thinned back surface to cover the bottom surface of the protruding conductive plug; Forming a concave structure on the rear insulating layer to expose a lower surface of the conductive plug; Forming a barrier layer in the intaglio structure and on a lower surface of the back insulation layer; Filling the intaglio structure by forming a conductive stud layer on the barrier layer surface; And Removing the conductive stud layer and the barrier layer until the back insulating layer is exposed to form a conductive stud filling the inside of the intaglio structure. Forming a first interlayer insulating film on a semiconductor substrate provided with a transistor; Forming a hole from an upper portion of the first interlayer insulating layer to a predetermined depth in the semiconductor substrate through the first interlayer insulating layer; Forming an internal insulating film on the inner wall of the hole and an upper surface of the first interlayer insulating film; Forming a liner layer on the entire surface of the internal insulating film; Filling the hole by forming a conductive metal layer on the entire surface of the liner layer; Removing the conductive metal layer and the liner layer until at least the internal insulating layer is exposed to form a conductive plug filling the inside of the hole; Forming a metal interconnection connected to an upper surface of the conductive plug and a second interlayer insulating layer surrounding the metal interconnection on the resultant product; Thinning a rear surface of the semiconductor substrate to protrude a lower surface of the conductive plug with respect to a rear surface of the thinned semiconductor substrate; Forming a back insulation film on the thinned back surface to cover the bottom surface of the protruding conductive plug; Forming a concave structure on the rear insulating layer to expose a lower surface of the conductive plug; Forming a UBM layer in the intaglio structure and on a lower surface of the back insulating layer; Masking a portion of the UBM layer formed in the intaglio structure and on a lower surface of the back insulation layer adjacent to the intaglio structure, and masking the remaining portion of the UBM layer with an insulator layer; Forming a bump material on the exposed UBM layer surface; And Removing the insulator layer and the UBM layer masked by the insulator layer to form bumps. Forming a first interlayer insulating film on a semiconductor substrate provided with a transistor; Forming a hole from an upper portion of the first interlayer insulating layer to a predetermined depth in the semiconductor substrate through the first interlayer insulating layer; Forming an internal insulating film on the inner wall of the hole and an upper surface of the first interlayer insulating film; Forming a liner layer on the entire surface of the internal insulating film; Filling the hole by forming a conductive metal layer on the entire surface of the liner layer; Removing the conductive metal layer and the liner layer until at least the internal insulating layer is exposed to form a conductive plug filling the inside of the hole; Forming a metal interconnection connected to an upper surface of the conductive plug and a second interlayer insulating layer surrounding the metal interconnection on the resultant product; Thinning a rear surface of the semiconductor substrate to protrude a lower surface of the conductive plug with respect to a rear surface of the thinned semiconductor substrate; Forming a back insulation film on the thinned back surface to cover the bottom surface of the protruding conductive plug; Forming a concave structure on the rear insulating layer to expose a lower surface of the conductive plug; Forming a barrier layer in the intaglio structure and on a lower surface of the back insulation layer; Forming a pad layer on the barrier layer surface; And Forming a pad by removing the pad layer and the barrier layer in the remaining region except for the lower surface area of the back insulating layer adjacent to the intaglio structure and the intaglio structure by a photolithography and an etching process. Manufacturing method. The method according to any one of claims 24 to 26, And the first interlayer insulating film is planarized by chemical mechanical polishing. The method according to any one of claims 24 to 26, And the internal insulating film is formed by CVD or ALD. The method according to any one of claims 24 to 26, And the liner layer is formed by PVD, CVD or ALD. The method according to any one of claims 24 to 26, Removing the conductive metal layer and the liner layer by a chemical mechanical polishing method. The method according to any one of claims 24 to 26, Removing the conductive metal layer and the liner layer by an etch back. The method according to any one of claims 24 to 26, And removing the conductive metal layer and the liner layer until the internal insulating layer is exposed. The method according to any one of claims 24 to 26, And removing the conductive metal layer and the liner layer until the first interlayer insulating film is exposed. The method according to any one of claims 24 to 26, And backside thinning of the semiconductor substrate is performed by backgrinding, chemical mechanical polishing or etching. The method according to any one of claims 24 to 26, And protruding the bottom surface of the conductive plug against the back surface of the thinned semiconductor substrate comprises over polishing. The method according to any one of claims 24 to 26, And protruding the bottom surface of the conductive plug with respect to the back surface of the thinned semiconductor substrate comprises etching. The method of claim 24, Removing the conductive stud layer and the barrier layer by a chemical mechanical polishing method. The method of claim 24, And etching the back insulation layer so that the metal stud protrudes after removing the conductive stud layer and the barrier layer. The method of claim 25, And the insulator layer is made of photoresist. The method of claim 25, And wherein the bump material is formed by a plating method. Preparing a semiconductor substrate having a lower surface of the conductive plug protruding from the rear surface thereof; Forming a rear insulating film on a rear surface of the semiconductor substrate to cover the lower surface of the conductive plug; Exposing a bottom surface of the conductive plug by forming a trench defining a rear metal wiring region in the back insulating layer; Filling the trench by sequentially forming a wiring barrier layer and a metal wiring layer in the trench and lower surfaces of the back insulating layer; Removing the metal wiring layer and the wiring barrier layer until the back insulating layer is exposed to form a back metal wiring inside the trench; Forming an insulating film between the back metal wires on the entire back surface of the resultant material; And And forming a concave structure in the insulating film between the back metal wires to expose the back metal wires. Preparing a semiconductor substrate having a lower surface of the conductive plug protruding from the rear surface thereof; Forming a rear insulating film on a rear surface of the semiconductor substrate to cover the lower surface of the conductive plug; Forming a first intaglio structure on the back insulating layer to expose a bottom surface of the conductive plug; Sequentially forming a wiring barrier layer and a metal wiring layer on the lower surfaces of the first intaglio structure and the bottom insulating layer; Patterning the metal wiring layer and the wiring barrier layer to form a back metal wiring; Forming an insulating film between the back metal wires on the entire back surface of the resultant material; And And forming a second recessed structure in the insulating film between the back metal wires to expose the back metal wires. The method of claim 41 or 42, And connecting lower surfaces of the plurality of conductive plugs by the rear metal wiring.

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