KR20060054690A - Semiconductor device having backside input output terminal and method of manufacturing the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an input / output terminal on a back surface of a substrate and a method of manufacturing the same. According to the present invention, a conductive plug separated by an internal insulating film and a capping insulating film is formed to a predetermined depth inside a semiconductor substrate, and then a transistor and an interlayer insulating film are formed on the semiconductor substrate, and then a metal wiring is formed to form an upper surface of the conductive plug. The bottom surface of the conductive plug is projected with respect to the back surface of the semiconductor substrate by thinning the back surface of the semiconductor substrate. Next, a rear insulating film is formed on the rear surface of the semiconductor substrate so as to cover the lower surface of the protruding conductive plug, and a negative structure is formed on the rear insulating film to expose the lower surface of the conductive plug. Subsequently, an input / output terminal connected to the lower surface of the exposed conductive plug is formed on the back of the substrate. Therefore, the present invention does not have to flip the semiconductor device when the semiconductor device is connected for chip stacking and mounting, and can quickly conduct heat generated from the transistor.

Semiconductor, Board, Back, I / O Terminals, Studs, Bumps, Pads                                                      

Description

A semiconductor device having a rear input / output terminal and a method of manufacturing the same {SEMICONDUCTOR DEVICE HAVING BACKSIDE INPUT OUTPUT TERMINAL AND METHOD OF MANUFACTURING THE SAME}

1A to 1J are cross-sectional views illustrating a method of embedding a conductive plug into a semiconductor substrate during a semiconductor device manufacturing process having an input / output terminal on a rear surface of a substrate according to the present invention;

2A to 2E are cross-sectional views illustrating a method of forming a transistor and a metal wiring during a semiconductor device manufacturing process having an input / output terminal on a back surface of a substrate according to the present invention;

3A to 3D are cross-sectional views illustrating a method of exposing a bottom surface of a conductive plug by processing a back side of a substrate during a process of manufacturing a semiconductor device having an input / output terminal on a back side of the substrate according to the present invention;

4A through 4C are cross-sectional views illustrating a method of manufacturing a semiconductor device having an input / output terminal on a back surface of a substrate according to an embodiment of the present disclosure;

5A through 5F are cross-sectional views illustrating a method of manufacturing a semiconductor device having an input / output terminal on a rear surface of a substrate according to another embodiment of the present invention;

6A through 6E are cross-sectional views illustrating a method of manufacturing a semiconductor device having an input / output terminal on a back surface of a substrate according to another embodiment of the present invention;

7A to 7D are cross-sectional views illustrating a method of adding a back metallization using a damascene process in embodiments of the present invention;

8A through 8C are cross-sectional views illustrating a method of adding a back metal wiring using an etching process in embodiments of the present invention.

<Brief description of the major symbols in the drawings>

100 semiconductor substrate 110 protective insulating film

120: hole 130, 130 ': internal insulating film

140 ': liner 150': metal body

160: conductive plug 200: transistor

300: interlayer insulating film 330, 340: metal wiring

500: back insulation 510: engraved structure

520 ': barrier layer 530': conductive stud

540 ', 540' ': UBM layer560, 562, 564: bump

570 ', 570' ': barrier layer

580 ', 580' ': Pad

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device having an input / output terminal on a back surface of a substrate and a method for manufacturing the same.

In general, an input / output (I / O) terminal of a semiconductor device is formed in the form of a bonding pad or a bump on an upper surface of a metal wiring process of the semiconductor device. In recent years, the metallization of semiconductor devices has been increasingly multilayered, and inter-layer dielectrics that insulate metallization have been replaced by low dielectric constant materials. However, the low dielectric constant material exhibits low mechanical strength and low thermal conductivity compared to the silicon oxide (SiO ₂ ) -based insulating film, which is used as an existing interlayer insulating film. As a result, an interlayer insulating layer supporting the pad may be destroyed during probe test and wire bonding through the pad formed on the upper surface of the semiconductor device, and the semiconductor device may be flipped to be mounted. In this case, there arises a problem of not properly conducting heat generated in the transistor of the semiconductor device.

In addition, although the input / output and flip chip bonding using bumps have been expanded in recent years due to the increase in the number of input / output terminals and the reduction in package size, light through the upper surface of a semiconductor device such as a CMOS image sensor is increased. In the case where the upper surface of the semiconductor device is to be exposed to the outside, for example, it is impossible to flip and bond the semiconductor device. Therefore, the method of forming bumps on the upper surface of such a semiconductor device has been difficult to apply because of problems in bonding.

In addition, in chip stacking for multi chip manufacturing, if an input / output terminal is formed only on the upper surface of the semiconductor device, it is difficult to directly connect the chip and the chip, and thus stack the chips and stack the bonding wires after stacking the chips. Bonding to pads on the edges has been used to connect chips or stack chips across a substrate such as a PCB. As such, in chip stacking, when chips are connected through wiring or a printed circuit, inductance is increased to increase high frequency loss, crosstalk between wires is increased, and electromagnetic interference ( Electro Magnetic Interference) characteristics may also deteriorate.

An object of the present invention is to solve the problems of the prior art as described above, to increase the mechanical strength of the input and output terminal support layer, improve the thermal conductivity during input and output through the bump, and no bonding of the semiconductor device during bonding, and also multi The present invention provides a semiconductor device having an input / output terminal on a rear surface of a substrate to enable direct connection between chips during chip stacking for chip manufacturing.

Another object of the present invention is to provide a method of manufacturing a semiconductor device having the rear input / output terminals.

A semiconductor device according to the present invention for achieving the above object is a semiconductor substrate having a hole formed to a predetermined depth therein, an internal insulating film formed on the inner wall of the hole, a conductive plug formed in the hole and recessed in the upper portion; A negative pattern for exposing the upper surface of the conductive plug through the capping insulating layer formed in the hole region where the conductive plug is recessed, the interlayer insulating layer formed on the semiconductor substrate and the capping insulating layer, and the interlayer insulating layer and the capping insulating layer; A rear surface having a recess formed in the intaglio pattern and connected to the upper surface of the conductive plug, and having an intaglio structure formed on the thinned rear surface of the semiconductor substrate and exposing the lower surface of the conductive plug protruding with respect to the thinned rear surface. An insulating film and a lower surface of the conductive plug formed under the rear insulating film And an input / output terminal to be connected.

In addition, in order to achieve the above object, the semiconductor device manufacturing method according to the present invention, forming a conductive plug to a predetermined depth inside the semiconductor substrate, wherein the conductive plug is separated by the internal insulating film and the capping insulating film, and Forming an interlayer insulating film on the semiconductor substrate and the capping insulating film, and then forming a metal wiring connected to the upper surface of the conductive plug by penetrating the interlayer insulating film and the capping insulating film, and thinning a rear surface of the semiconductor substrate to The lower surface protrudes from the rear surface of the thinned semiconductor substrate, and then a rear insulating film is formed on the thinned rear surface to cover the lower surface of the protruding conductive plug, and then a negative structure is formed on the rear insulating film to form the conductive plug. Exposing a bottom surface of the semiconductor substrate; Characterized in that it comprises the step of forming the input and output terminals connected to the lower surface of the conductive plug exposed group.

The internal insulating film is formed of a silicon oxide film (SiO ₂ ), a silicon nitride film (Si ₃ N ₄ ), a silicon carbide film (SiC), or a combination thereof and is deposited by chemical vapor deposition (CVD) or atomic layer deposition (ALD). Form. The conductive plug is made of a liner and a metal body. The liner is made of Ti, TiN, TiSiN, Ta, TaN, TaSiN, WN or a combination thereof and is formed by PVD, CVD or ALD methods. In addition, the metal body is made of tungsten (W) formed by CVD or ALD method.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. However, embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. Accordingly, the shape and the like of the elements in the drawings are exaggerated to emphasize a more clear description, and the elements denoted by the same reference numerals in the drawings means the same elements.

1A to 1J are cross-sectional views illustrating a method of manufacturing a semiconductor device until a step of embedding a conductive plug in a substrate during a process of manufacturing a semiconductor device having an input / output terminal on a rear surface of a substrate according to the present invention.

Referring to FIG. 1A, a hole 120 is formed on a semiconductor substrate 100 through a photolithography and an etching process. A Si substrate is generally used as the semiconductor substrate 100, but a silicon on insulator (SOI) substrate may be used. The diameter of the hole 120 is preferably about 0.2 μm to 5 μm, and the depth d to the inside of the semiconductor substrate 100 is preferably about 8 μm to 200 μm depending on the diameter of the hole 120. Along with the formation of the hole 120, a trench (not shown) for an alignment mark to be used in a backside process may be formed. The alignment mark may be formed when the rear structure is patterned. It is used for accurate alignment between the structure defined by 120 and the back structure.

Referring to FIG. 1B, an internal insulating layer 130 is formed on an inner wall of the hole 120 and an upper surface of the semiconductor substrate 100 to insulate the semiconductor substrate 100. The internal insulation layer 130 may be formed of a silicon oxide layer (SiO ₂ ), a silicon nitride layer (Si ₃ N ₄ ), a silicon carbide layer (SiC), or a combination thereof. The internal insulating layer 130 may be formed by deposition by CVD or ALD, or may be formed by thermally oxidizing a Si surface of the semiconductor substrate 100 to grow a silicon oxide layer on the surface.

Referring to FIG. 1C, the liner layer 140 is formed on the entire surface of the resultant, and then the conductive metal layer 150 is formed on the entire surface of the liner layer 140 to fill the hole 120. The liner layer 140 serves as a glue layer to allow the conductive metal layer 150 to adhere well to a surface of the internal insulating layer 130 and the valence forming the conductive metal layer 150 to the outside of the hole 120. It acts as a barrier to prevent spreading. The liner layer 140 may be made of Ti, TiN, TiSiN, Ta, TaN, TaSiN, WN, or a combination thereof. Physical vapor deposition (PVD), CVD, or ALD methods may be used to form the liner layer 140. The conductive metal layer 150 substantially fills the inside of the hole 120, and preferably includes W formed by ALD or CVD. In addition, although not shown, trenches necessary for fabricating the alignment mark for the backside process are also buried by the liner layer 140 and the conductive metal layer 150.

Referring to FIG. 1D, the conductive metal layer 150 and the liner layer 140 are removed until the internal insulating layer 130 is exposed to remove the liner 140 ′ and the metal body 150 ′ in the hole 120. ) To form a conductive plug 160, but removes a portion of the conductive plug 160 filling the upper portion of the hole 120 to recess the conductive plug 160 as shown. At this time, the upper surface of the conductive plug 160 is lowered below a position (indicated by a dotted line) formed between the interface between the semiconductor substrate 100 and the internal insulating layer 130, and preferably recessed from the interface. The size h is set to 50 nm or 300 nm or so. The conductive metal layer 150 and the liner layer 140 may be removed by chemical mechanical polishing or etch back, or may be used in combination with an etch back and a chemical mechanical polishing method. In this case, in order to achieve a recess of the conductive plug 160, over polishing or over etching may be performed. In addition, although not shown, a liner and a metal body are formed in the trench required for fabricating the alignment mark to be used in the rear surface process.

Referring to FIG. 1E, a capping insulating layer 170 is formed on the entire surface of the structure illustrated in FIG. 1D to fill a space formed by recessing the conductive plug 160. The capping insulating layer 170 may be formed of a silicon oxide film, a silicon nitride film, a silicon carbide film, or a combination thereof.

Referring to FIG. 1F, the remaining insulating layer 130 formed on the upper surface of the semiconductor substrate 100 is removed after removing the remaining portion of the capping insulating layer 170 except the portion formed in the recessed recess of the conductive plug 160. Is removed until the semiconductor substrate 100 is exposed. Then, the conductive plug 160 is embedded in the semiconductor substrate 100 in an isolated state by the internal insulating layer 130 ′ and the capping insulating layer 170 ′. The capping insulation layer 170 and the inner insulation layer 130 may be removed using a chemical mechanical polishing method.

FIG. 1G illustrates an example in which a protective insulating layer 110 is first formed on an upper surface of a semiconductor substrate 100 and then a hole 120 is formed through a photo and etching process. The protective insulating layer 110 serves to protect the surface of the semiconductor substrate 100 from etching and chemical mechanical polishing. The protective insulating film 110 may be formed of a silicon oxide film, a silicon nitride film, a silicon carbide film, or a combination thereof, for example, by depositing a silicon nitride film on a silicon oxide film formed by a thermal oxidation method.

1H and 1I, first, an internal insulating layer 130 is formed on an inner wall of the hole 120 and an upper surface of the protective insulating layer 110 in FIG. 1H to form an inner wall of the hole 120 in the semiconductor substrate 100. Insulate the exposed areas. Meanwhile, referring to FIG. 1I, this illustrates the formation of an internal insulating film 132 made of a silicon oxide film by thermally oxidizing the inner wall of the hole 120. At this time, the upper surface of the semiconductor substrate 100 has a protective insulating film 110 to suppress the generation of silicon oxide film. Therefore, the internal insulating film may be formed using a vapor deposition method or a thermal oxidation method, or both of the inner wall and the protective insulating film 110 oxidized by the vapor deposition method after thermal oxidation of the inner wall of the hole 120 in parallel with the two methods. An internal insulating film may be further formed on the surface.

Referring to FIG. 1J, this illustrates a case in which the protective insulating layer 110 is left when the conductive plug 160 and the capping insulating layer 170 ′ are formed in the hole 120. The protective insulating film 110 may be removed to expose the surface of the semiconductor substrate 100 as shown in FIG. 1F. However, the protective insulating film 110 may be used as a hard mask for forming a field oxide film in a subsequent transistor manufacturing process. It is desirable to leave as shown. As such, when the protective insulating film 110 is used in a subsequent transistor manufacturing process, the protective insulating film 110 may be formed of a silicon oxide film formed by thermal oxidation and a silicon nitride film formed by CVD.

2A to 2E illustrate a method of manufacturing a semiconductor device up to a step of forming a metal wiring connected to a transistor and an upper surface of the conductive plug 160 during a semiconductor device manufacturing process having an input / output terminal on a rear surface of a substrate according to the present invention. It is sectional drawing for description.

Referring to FIG. 2A, the conductive plug 160 is isolated by the internal insulating layer 130 ′ and the capping insulating layer 170 ′ to form a transistor on the embedded semiconductor substrate 100, and then includes a transistor. An interlayer insulating film 300 is formed on the semiconductor substrate 100 and the capping insulating film 170 ′. The illustrated transistor is an example of a CMOS transistor. The field oxide film 210, the wells 220 and 230, the gate electrode 260 and the spacer 270, the source regions 240s and 250s may be formed on the semiconductor substrate 100. It is produced by forming the drain regions 240d and 250d and the like. As the transistor, various transistors such as Bipolar or BiCMOS as well as CMOS may be used. Since the transistors used in the present embodiment can be variously changed by those skilled in the art, a detailed description thereof will be omitted. After the transistor is formed, the interlayer insulating film 300 is formed on the semiconductor substrate 100 to insulate the gate electrode 260 and the source and drain regions 240s, 250s, 240d and 250d. Generally, a material based on a silicon oxide film is formed by a CVD method, and a silicon nitride film or a silicon carbide film may be added as an etch stop layer or a diffusion barrier film. In particular, the gap fill and gettering characteristics may be improved by doping elements such as boron (B) or phosphorus (P) when forming the silicon oxide layer. The interlayer insulating layer 300 is planarized by chemical mechanical polishing to reduce the occurrence of defects in subsequent photographic and etching processes. Thereafter, the field oxide film 210, the wells 220 and 230, the gate electrode 260 and the spacer 270, and the source and drain regions 240s, 250s, 240d and 250d constituting the transistor are integrated for simplicity of the drawings. The transistor 200 will be described.

2B and 2C, first, the upper surface of the conductive plug 160 is exposed through the interlayer insulating layer 300 and the capping layer 170 ′ through a photolithography and etching process as shown in FIG. 2B. An intaglio pattern 310 is formed. The intaglio pattern 310 shown in the form of a hole, wherein the diameter of the intaglio pattern 310 is preferably smaller than the diameter of the conductive plug (160). FIG. 2C illustrates another example of the intaglio pattern 320. The intaglio pattern 320 includes a hole (indicated by H) and a trench (indicated by T) in communication with the upper portion of the hole. dual damascene). When the intaglio pattern 320 is formed, the transistor 200 region (for example, a junction or a gate region) is exposed as shown in addition to the top surface of the conductive plug 160, or is not shown, but the top of another conductive plug is not shown. You can expose the cotton.

2D and 2E, first, in FIG. 2D, a metal wire 330 is formed to be connected to the upper surface of the conductive plug 160 and fill the inside of the intaglio pattern 310. Since the metal wire 330 is formed in the intaglio pattern 310 having a hole shape, the metal wire 330 has a plug shape. Although not shown, conductive plugs or doped polysilicon may be formed in the interlayer insulating layer 300 to contact the junction or gate electrode of the transistor before or after the metal wiring 330 is formed. ) Form a pad electrode. FIG. 2E shows another example of the metal wiring 340. The metal wiring 340 has a plug (indicated by P) and a line (indicated by L) in communication with the upper portion of the plug. The conductive plug 160 and the transistor 200 may be directly connected through the metal wire 340, and although not shown, a connection between the conductive plugs may be performed. The metal wires 330 and 340 sequentially form a liner made of Ti, TiN, Ta, TaN, or a combination thereof, and a metal layer such as W or Cu on the intaglio patterns 310 and 320 and the interlayer insulating film 300. After forming, it is manufactured by removing a metal layer and a liner in an area except the intaglio patterns 310 and 320 by a chemical mechanical polishing method. In the following drawings to illustrate the case of the metal wire 330 having a plug shape for simplicity of the drawings. After the metal wiring is formed, a structure such as a capacitor and a poly plug in a DRAM, including a metal wiring (not shown) in another layer connected to the metal wirings 330 and 340 above the interlayer insulating layer 300. The RF chip may include structures such as resistors and inductors. Since the structure in the upper layer than the interlayer insulating film 300 can be variously changed by those skilled in the art according to the use of the semiconductor device, a description thereof will be omitted.

3A to 3D illustrate a method of fabricating a semiconductor device up to a step of exposing a bottom surface of the conductive plug 160 by processing a substrate back during a process of manufacturing a semiconductor device having an input / output terminal on a rear surface of a substrate according to the present invention. These are cross-sectional views.

Referring to FIGS. 3A and 3B, first, as shown in FIG. 3A, the rear surface of the semiconductor substrate 100 is thinned, and the lower surface 162 of the conductive plug 160 is thinned. Protrudes against the backside 102 of 100. Although the drawing illustrates the case where the metal body 150 'of the conductive plug 160 is exposed, the thinning process may be controlled so that the liner 140' of the lower surface may not be removed. Thinning is achieved by back grinding, chemical mechanical polishing or etching. A preferred thinning procedure on the back side of the semiconductor substrate 100 is to achieve first bulk removal by backgrinding followed by fine removal by chemical mechanical polishing or etching. When thinning the semiconductor substrate 100 very thin (for example, 20 μm or less), the semiconductor substrate 100 may be attached to a support (for example, another wafer) and then thinned. Upon fine removal by chemical mechanical polishing, the conductive plug 160 can be used as a polishing end point to control the polishing process. At this time, the back surface 102 of the semiconductor substrate 100 is lower than the lower surface 162 of the conductive plug 160, as shown through over polishing or additional etching after polishing at the polishing stop point. A recess is added, that is, the lower surface 162 of the conductive plug 160 is protruded, so that the semiconductor substrate 100 can be insulated in a subsequent process. On the other hand, when the polishing or etching selectivity of the semiconductor substrate 100 and the internal insulating layer 130 ′ in the thinning through chemical mechanical polishing or etching is large, as shown in FIG. 3B, the lower surface of the conductive plug 160 is It is covered with an internal insulating film 130 '. At this time, the thinning is sufficiently performed so that the uncovered lower surface of the conductive plug 160 protrudes with respect to the back surface 102 of the thinned semiconductor substrate 100. Also, although not shown, the alignment mark for the backside process is also exposed by the thinning process so as to be used in a subsequent patterning process.

Referring to FIGS. 3C and 3D, first, as shown in FIG. 3C, a rear insulating layer 500 is formed on the thinned back surface of the thinned semiconductor substrate of FIG. 3A to cover the bottom surface of the protruding conductive plug 160. An intaglio structure 510 is formed on the back insulation layer 500 through a photolithography and an etching process to expose the lower surface 162 of the conductive plug 160. Meanwhile, referring to FIG. 3D, a rear insulating film 500 is formed on the rear surface of FIG. 3B, and then a lower surface of the conductive plug 160 is formed during an etching process for forming an intaglio structure 510 on the rear insulating film 500. At the same time, the covering of the inner insulating layer 130 ′ is removed to expose the lower surface of the conductive plug 160. The intaglio structure 510 is preferably in the shape of a circular or polygonal disk. Although not shown, alignment between the plug 160 and the intaglio structure 510 is performed when patterning the intaglio structure 510 with the aid of the alignment mark manufactured together with the formation of the conductive plug 160. Can be achieved. The back insulating layer 500 may be formed of a silicon oxide film, a silicon nitride film, a silicon carbide film, or a combination thereof, which is deposited by a CVD method, or a polymer such as BCB (BezoCycloButene) formed by curing followed by liquid coating.

4A to 4C illustrate an input / output terminal connected to a lower surface of the exposed conductive plug 160 according to an embodiment of the present invention during a process of manufacturing a semiconductor device having an input / output terminal on a rear surface of a substrate according to the present invention. Are cross-sectional views for explaining the method for manufacturing a semiconductor device until the step of forming the semiconductor device.

Referring to FIG. 4A, a barrier layer 520 is formed in the intaglio structure 510 and the bottom surface 502 of the back insulation layer 500 of FIG. 3C to form a bottom surface 162 of the exposed conductive plug 160. ) Is covered with the barrier layer 520, and then a conductive stud layer 530 is formed on the surface of the barrier layer 520 to fill the intaglio structure 510. The barrier layer 520 may be formed of Ta, TaN, TaSiN, or a combination thereof, and may be formed by PVD or CVD. The conductive stud layer 530 is preferably made of Cu and is formed by PVD or plating.

Referring to FIG. 4B, the conductive stud layer 530 and the barrier layer 520 are removed until the back insulation layer 500 is exposed to form a conductive stud 530 ′ which fills the inside of the intaglio structure 510. do. The conductive stud layer 530 and the barrier layer 520 may be removed using a chemical mechanical polishing method. When the conductive stud 530 ′ protrudes from the rear surface insulating film 500, the removal rate of the conductive stud layer 530 is increased when the barrier layer 520 is removed from chemical mechanical polishing. And a slurry lower than the polishing rate of the back insulation layer 500. For example, in the case of the back insulation layer 500 made of silicon oxide (SiO ₂ ), the barrier layer 520 made of Ta, and the conductive stud layer 530 made of Cu, Cu outside the intaglio structure 510 is removed. When removing Ta and SiO ₂ of a certain thickness with a Rodel CuS-1201 slurry, the polishing rate ratio of Cu: Ta: SiO ₂ is about 1: 4: 6, so that the conductive stud 530 'made of Cu is as shown in FIG. 4C. Will protrude. Another method of protruding the conductive stud 530 ′ is that if the etching rate of the back insulation layer 500 is etched in an environment in which the etching rate of the rear insulating layer 500 is greater than the etching rate of the conductive stud 530 ′, the conductive stud 530 ′ is formed. The stud 530 'protrudes. For example, after the conductive stud 530 'is formed by chemical mechanical polishing in a structure composed of the above-described materials (SiO ₂ , Ta and Cu), the semiconductor substrate 100 is diluted with HF or BOE (Buffered Oxide Etchant). In the case of etching, the etching rate of the back insulation layer SiO ₂ is relatively high, so that the conductive stud 530 ′ may protrude.

In the drawings of the above-described embodiment, one conductive plug 160 is formed per conductive stud 530 'for the purpose of simplifying the drawing, but is connected to the barrier layer 520', but for the purpose of reducing electrical resistance or rapid thermal conduction. As a result, a plurality of conductive plugs may be formed per conductive stud and connected to the barrier layer.

Through the above-described manufacturing method, a conductive stud may be formed on the rear surface of the substrate, and the conductive stud may thermally diffuse with a conductive stud formed on the upper surface of another semiconductor device during vertical connection between semiconductor devices such as chip stacking. In this case, the semiconductor device having the conductive studs formed on the rear surface thereof does not need to be flipped. In addition, when the conductive stud is formed on the upper surface of the semiconductor device by the conventional method and the conductive stud is formed on the rear surface of the semiconductor device by the above-described method, the semiconductor device has input and output terminals on the upper and rear surfaces, respectively. This allows for direct stacking between chips without the need for wires or PCBs in stacking three or more chips.

5A to 5F illustrate an input / output terminal connected to a lower surface of the exposed conductive plug 160 according to another embodiment of the present invention during a process of manufacturing a semiconductor device having an input / output terminal on a rear surface of a substrate according to the present invention. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device until it forms in.

Referring to FIG. 5A, an under bump metal (UBM) layer 540 is formed in the intaglio structure 510 and the bottom surface 502 of the back insulation layer 500 of FIG. 3C to expose the exposed conductive plug 160. The lower surface 162 of the UBM layer 540 is covered. Subsequently, the patterning process exposes the UBM layer 540 formed in the intaglio structure 510 and the lower surface of the back insulation layer 500 adjacent to the intaglio structure 510 and exposes the rest of the UBM layer 540. Mask to layer 550. The UBM layer 540 may be made of Ti, Ta, Cr, Ni, Cu, Pd, Au, or a combination thereof, and may be formed by PVD or plating. As the insulator layer 550 for masking, an inorganic insulating material such as a silicon oxide film or a photoresist may be used. The inorganic insulating material is more thermally stable than the photoresist, and requires an additional process for removing the inorganic insulating material. Therefore, it is desirable to use photoresist as a non-conductor layer for masking if subsequent processes do not require high temperature rises, such as plating.

Referring to FIG. 5B, when the bump material is formed on the exposed surface of the UBM layer 540 by the plating method, the back insulation layer 500 may be removed by removing the insulator layer 550 and the UBM layer masked by the insulator layer. Bump 560 is formed. The bump 560 is connected to the conductive plug 160 through a UBM layer 540 ′. If the bumping is not required after plating, Au or Cu is preferable as the bump material, and in the case of solder bumps that require shaping through reflow, Pb, Sn, Alloys of metals selected from Sb, Cu, Ni, Ag, Bi, In, Zn (eg Pb-Sn or Sn-Ag-Cu) can be used. In the case of solder bumps, the bumps 560 may be reflowed to be shaped into bumps 560 'that are close to a spherical or hemispherical shape as shown in FIG. 5C.

5D to 5F show another example of the bump forming method. First, as shown in FIG. 5D, a UBM layer 540 is formed on the inside of the intaglio structure 510 of FIG. 3C and the bottom surface 502 of the back insulation layer 500 to form a bottom surface of the exposed conductive plug 160. 162 is covered with the UBM layer 540. Subsequently, the UBM layer 540 of the UBM layer 540 covering the lower surface of the conductive plug 160 in the intaglio structure 510 and the horizontal wall surface of the intaglio structure 510 adjacent to the bottom surface through a patterning process. 540 is exposed and the rest is masked with a non-conductive layer 552 such as photoresist. That is, the exposed area does not leave the engraved structure 510. Subsequently, as shown in FIG. 5E, the bump material is formed on the surface of the exposed UBM layer 540 by the plating method, and then the UBM layer masked by the insulator layer 552 and the insulator layer 552 ( Removing 540 forms bump 562. As described above, when the exposure of the UBM layer 540 is limited to the inside of the intaglio structure 510, the bump 564 may be fabricated by adjusting the plating thickness as shown in FIG. 5F. That is, in the drawing, the bump 564 may be manufactured such that the lower surface 566 of the bump is higher than the level L (shown by the dotted line) defined by the lower surface 502 of the back insulating film 500.

In the drawing of the embodiment described above, one conductive plug 160 is formed for each bump 560, 562, 564 for the purpose of simplifying the drawing, and is connected to the UBM layers 540 ′, 540 ″, but the electrical resistance is reduced or the thermal conductivity is reduced. For example, a plurality of conductive plugs may be formed per bump to connect to the UBM layer.

Bumps can be formed on the rear surface of the substrate through the above-described manufacturing method, and these bumps can be mounted on a PCB or glass without flipping the semiconductor device. In addition, the bumps may be used for chip stacking. When the metal pads corresponding to the bumps are formed on the upper surface of another semiconductor device to form a stack, the two semiconductor devices are flipped when the bumps and the metal pads are bonded by soldering or the like. There is an advantage that can be connected directly without this.

6A to 6E illustrate an input / output terminal connected to a lower surface of the exposed conductive plug 160 according to another embodiment of the present invention during a process of manufacturing a semiconductor device having an input / output terminal on a rear surface of a substrate according to the present invention. It is sectional drawing for demonstrating the manufacturing method of a semiconductor device until it forms in a back surface.

Referring to FIG. 6A, a barrier layer 570 is formed on the inside of the intaglio structure 510 of FIG. 3C and the bottom surface 502 of the back insulation layer 500 to form a bottom surface 162 of the exposed conductive plug 160. ) Is covered with the barrier layer 570, and then a pad layer 580 is formed on the barrier layer 570. Subsequently, a portion of the pad layer 580 covering the inside of the intaglio structure 510 and the lower surface of the back insulation layer 500 adjacent to the intaglio structure 510 is masked with a photoresist 590 through a photolithography process. . The barrier layer 570 may be formed of Ti, TiN, Ta, TaN, or a combination thereof, and may be formed through PVD. The pad layer 580 is made of Al or an Al alloy, or a multilayer form made of a combination of Ni, Ti, Cr, Cu, Au, and is formed through PVD or plating.

Referring to FIG. 6B, when the pad layer 580 and the barrier layer 570 outside the region masked by the photoresist 590 are etched away and the photoresist 590 is removed, the conductive plug 160 may be removed. An electrically connected pad 580 ′ is formed in the intaglio structure 510 and on the bottom surface of the back insulating layer 500 adjacent to the intaglio structure 510.

6C to 6E, this is another example of a pad forming method. First, as shown in FIG. 6C, the inside of the intaglio structure 510 of FIG. 3C and the bottom surface 502 of the back insulating film 500 are illustrated. A barrier layer 570 is formed to cover the lower surface 162 of the exposed conductive plug 160 with the barrier layer 570, and then form a pad layer 580 on the barrier layer 570 surface. Next, as shown in FIG. 6D, when the pad layer 580 and the barrier layer 570 in the region other than the inside of the intaglio structure 510 are removed until the back insulation layer 500 is exposed, the conductive plug is removed. A pad 580 ″ connected through the 160 and the barrier layer 570 ″ is formed inside the intaglio structure. Therefore, the pad 580 ″ is not exposed outside the intaglio structure 510. In this case, the pad layer 580 and the barrier layer 570 may be removed using a chemical mechanical polishing method, or as shown in FIG. 6E, such as photoresist or spin on glass (SOG) on the back of the structure of FIG. 6C. The process of applying and curing the liquid material 592 and then etching back may be used.

In the drawings of the above-described embodiment, for the sake of simplicity, one conductive plug 160 is formed per pad 580 'and 580' 'to connect the barrier layers 570' and 570 '' to reduce electrical resistance or For the purpose of rapid thermal conduction, a plurality of conductive plugs can be formed per pad to connect to the barrier layer.

Through the above-described manufacturing method it is possible to form a pad on the back of the substrate. The pad made of Al or Al alloy can be used for probe testing and wire bonding of a semiconductor device like a conventional bonding pad. In the case of a semiconductor device in which a material having a weak mechanical strength, such as a low dielectric constant material, is used as an intermetallic insulating layer, the pad formed on the back side has an advantage that the substrate is a support layer and thus is not easily destroyed during probe testing or wire bonding. In addition, after the probe test, a process of forming a UBM layer on the pad surface and then forming a bump through plating may be further added. The multi-layer pad may be used to directly connect the two semiconductor devices by forming an uppermost layer of Au, Ni, or Cu, in which an oxide layer is not formed or easily removed, and bonding the bumps formed on other semiconductor devices during chip stacking.

In the above-described embodiments, only the case where the conductive plug and the rear input / output terminals are directly connected is illustrated, but the rear metal wiring may be added between the conductive plug and the rear input / output terminal for the connection between the conductive plugs or the position shift of the rear input / output terminals. Can be. 7A to 7D are cross-sectional views illustrating a method of adding a back metal wiring using a damascene process in the above-described embodiments.

Referring to FIG. 7A, this illustrates a process after FIG. 3A. A back insulation film 500 is formed on the backside of the semiconductor substrate 100 thinned similarly to FIG. 3C, and then a metal wiring region is formed on the back insulation film 500. A trench 600 is defined to expose the bottom surface 162 of the conductive plug 160. Here, the trench 600 may expose the lower surface 162 of the conductive plug 160 and may extend around to expose the lower surface of another conductive plug, although not shown.

Referring to FIGS. 7B and 7C, first, as shown in FIG. 7B, a wiring barrier layer 610 and a metal wiring layer 620 are sequentially formed on the lower surfaces of the inside of the trench 600 and the rear insulating layer 500. Landfill 600. Subsequently, when the metal wiring layer 620 and the wiring barrier layer 610 are removed until the back insulation layer 500 is exposed, the lower surface of the conductive plug 160 is connected to the inside of the trench 600 as shown in FIG. 7C. The back metal wiring 630 composed of the wiring barrier layer 610 'and the metal wiring layer 620' is completed. Although not shown, the bottom surface of the other conductive plugs may be connected by the rear metal wiring 630. The wiring barrier layer 610 may be formed of Ti, TiN, Ta, TaN, TaSiN, or a combination thereof. The metal wiring layer 620 is preferably made of W or Cu. Removal of the metal wiring layer 620 and the wiring barrier layer 610 for forming the back metal wiring 630 is preferably using a chemical mechanical polishing method.

Referring to FIG. 7D, an insulating film 640 is formed on the entire rear surface of the resultant, and then an intaglio structure 650 is formed to form a rear input / output terminal through a photo and etching process, thereby forming the rear metal wiring 630. Expose The rear metal interlayer insulating film 640 may be formed of a silicon oxide film, a silicon nitride film, a silicon carbide film, or a combination thereof, or may be made of a polymer such as BCB (BezoCycloButene). Subsequent processes are the same as those of FIGS. 4A, 5A, or 6A of the above-described embodiments and subsequent processes according to the type of the rear input / output terminal. In this case, the exposed back metallization 630 corresponds to the exposed conductive plug 160 in the above-described embodiments, and the back metallization insulating layer 640 corresponds to the back insulation layer 500.

The above-described method of forming the rear metal wiring is made by using a machining process, and it is possible to form the rear metal wiring by the etching method. 8A through 8C are cross-sectional views illustrating a method of adding a back metal wiring using an etching process in the above-described embodiments.

Referring to FIG. 8A, this represents a process after FIG. 3A. In the same manner as in FIG. 3C, the first intaglio structure 512 is formed on the back insulation layer 500 to expose the lower surface 162 of the conductive plug 160. Let's do it.

Referring to FIG. 8B, a wiring barrier layer 660 and a metal wiring layer 670 are sequentially formed on the inner surfaces of the first intaglio structure 512 and the lower surface of the back insulation layer 500, and a photoresist is formed in the region where the wiring is to be formed. Mask at (680). The wiring barrier layer 660 may be formed of Ti, TiN TiSiN, or a combination thereof. The metal wiring layer 670 is preferably made of Al or Al alloy.

Referring to FIG. 8C, when the metallization layer 670 and the wiring barrier layer 660 are etched using the photoresist 680 as a mask, and the photoresist 680 is removed, the bottom surface of the conductive plug 160 is removed. The back metal wiring 690 including the wiring barrier layer 660 'and the metal wiring layer 670' connected to each other is completed. Although not shown, the bottom surface of the other conductive plugs may be connected by the rear metal wiring 690. Subsequently, an insulating film 700 between the rear metal wires is formed on the entire rear surface of the resultant metal so as to surround the rear metal wires, and then a second intaglio structure 710 is formed to form a rear input / output terminal through a photo and etching process. The wiring 690 is exposed. The rear metal interlayer insulating film 700 may be formed of a silicon oxide film, a silicon nitride film, a silicon carbide film, or a combination thereof, or may be made of a polymer such as BCB. Subsequent processes are the same as those of FIGS. 2A, 3A, or 4A of the above-described embodiments and subsequent processes according to the type of the rear input / output terminal. In this case, the exposed back metallization 690 corresponds to the exposed conductive plug 160 in the above-described embodiments, and the back metallization insulating film 700 corresponds to the back insulation layer 500.

As described above, the present invention forms conductive studs or bumps on the rear surface of the substrate so that the semiconductor devices can be quickly flipped without the flip of the semiconductor devices when the semiconductor devices are connected for chip stacking and mounting. . In addition, the present invention can minimize the mechanical defects that may occur during the probe test and wire bonding by forming a pad on the back surface of the substrate, thereby making it possible to use a variety of intermetallic insulating material for the manufacture of semiconductor devices.

On the other hand, the present invention is not limited to the above-described embodiment, various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims to be described later.

Claims (57)

A semiconductor substrate having a hole formed to a predetermined depth therein; An internal insulating film formed on the inner wall of the hole; A conductive plug formed in the hole and recessed at an upper portion thereof; A capping insulating layer formed in the hole region in which the conductive plug is recessed; An interlayer insulating film formed on the semiconductor substrate and the capping insulating film; An intaglio pattern exposing the conductive plug upper surface through the interlayer insulating layer and the capping insulating layer; A metal wiring formed in the intaglio pattern and connected to an upper surface of the conductive plug; A back insulating layer formed on the thinned rear surface of the semiconductor substrate and having an intaglio structure exposing a bottom surface of the conductive plug protruding from the thinned rear surface; And And an input / output terminal formed under the back insulation layer and connected to a bottom surface of the conductive plug. The method of claim 1, And the internal insulating film is formed of a silicon oxide film, a silicon nitride film, a silicon carbide film, or a combination thereof. The method of claim 1, The conductive plug is a semiconductor device, characterized in that consisting of a liner and a metal body. The method of claim 3, wherein And the liner is made of Ti, TiN, TiSiN, Ta, TaN, TaSiN, WN, or a combination thereof. The method of claim 3, wherein The metal body is a semiconductor device, characterized in that made of W. The method of claim 1, And the capping insulating film is formed of a silicon oxide film, a silicon nitride film, a silicon carbide film, or a combination thereof. The method of claim 1, The engraved pattern is a semiconductor device, characterized in that the shape of the hole. The method of claim 1, The engraved pattern is a semiconductor device, characterized in that the form consisting of a hole in communication with the upper portion of the hole. The method of claim 1, And the metal wiring is connected to a transistor formed on the semiconductor substrate. The method of claim 1, And said back insulating film is made of a silicon oxide film, a silicon nitride film, a silicon carbide film, or a combination thereof. The method of claim 1, And said back insulating film is made of a polymer. The method of claim 1, At least one conductive plug bottom surface is connected to the input / output terminal. The method of claim 1, A semiconductor device further comprising a metal back surface formed between the lower surface of the conductive plug and the input / output terminal. The method of claim 1, And the input / output terminal comprises a barrier layer formed inside the engraved structure and a conductive stud formed on a surface of the barrier layer to fill the inside of the engraved structure. The method of claim 14, The barrier layer is made of Ta, TaN, TaSiN or a combination thereof. The method of claim 14, And the conductive stud is made of Cu. The method of claim 1, And the input / output terminal is formed of a UBM layer formed on the inside of the intaglio structure and a lower surface of the back insulating layer adjacent to the intaglio structure, and a bump formed on a surface of the UBM layer. The method of claim 1, And the input / output terminal is formed of a lower surface of the conductive plug in the recess structure and a UBM layer formed on a horizontal wall surface of the recess structure adjacent to the lower surface and a bump formed on a surface of the UBM layer. The method of claim 17 or 18, The UBM layer is made of Ti, Ta, Cr, Ni, Cu, Pd, Au, or a combination thereof. The method of claim 17 or 18, The bump is made of Au or Cu semiconductor device. The method of claim 17 or 18, The bump is a semiconductor device, characterized in that consisting of a solder bump. The method of claim 21, The solder bump is made of an alloy of metals selected from Pb, Sn, Sb, Cu, Ni, Ag, Bi, In, Zn. The method of claim 18, And the bump is not exposed to the outside of the intaglio structure. The method of claim 1, And the input / output terminal includes a barrier layer formed on the inside of the intaglio structure and a lower surface of the back insulating layer adjacent to the intaglio structure, and a pad formed on the surface of the barrier layer. The method of claim 1, And the input / output terminal comprises a barrier layer formed inside the engraved structure and a pad formed on the barrier layer surface. The method of claim 24 or 25, The barrier layer is made of Ti, TiN, Ta, TaN or a combination thereof. The method of claim 24 or 25, And the pad is made of Al or an Al alloy. The method of claim 24 or 25, The pad is a semiconductor device, characterized in that the multi-layer form consisting of a combination of Ni, Ti, Cr, Cu, Au. The method of claim 25, And the pad is not exposed to the outside of the intaglio structure. Forming a conductive plug to a predetermined depth inside the semiconductor substrate, wherein the conductive plug is separated by an internal insulating film and a capping insulating film; A second step of forming an interlayer insulating film on the semiconductor substrate and the capping insulating film, and then forming a metal wiring connected to the upper surface of the conductive plug through the interlayer insulating film and the capping insulating film; Thinning a rear surface of the semiconductor substrate to protrude a lower surface of the conductive plug with respect to a rear surface of the thinned semiconductor substrate, and then forming a rear insulating film on the thinned rear surface to cover the lower surface of the protruding conductive plug. Forming a concave structure on the rear insulating layer to expose a lower surface of the conductive plug; And And forming an input / output terminal connected to a lower surface of the exposed conductive plug on a rear surface of the semiconductor substrate. The method of claim 30, Forming and separating the conductive plug of the first step is Forming a hole to a predetermined depth inside the semiconductor substrate; Forming an internal insulating film on the inner wall of the hole and an upper surface of the semiconductor substrate; Forming a liner layer on the entire surface of the internal insulating film; Filling the hole by forming a conductive metal layer on the entire surface of the liner layer; Removing the conductive metal layer and the liner layer until the internal insulating layer is exposed to form a conductive plug in the hole, and removing a portion of the conductive plug filling the upper portion of the conductive plug so as to recess the conductive plug; Forming a capping insulating layer on the entire surface of the resultant product; And And sequentially removing the capping insulating film and the inner insulating film outside the hole region to separate the conductive plugs by the inner insulating film and the capping insulating film. The method of claim 31, wherein And forming a protective insulating film on the upper surface of the semiconductor substrate before forming the holes. The method of claim 32, And removing the protective insulating film after formation and separation of the conductive plug. The method of claim 32, And leaving the protective insulating layer after formation and separation of the conductive plug to use as a hard mask for forming a field oxide layer. The method of claim 31, wherein And the internal insulating film is formed by CVD or ALD. The method of claim 31, wherein Removing the conductive metal layer and the liner layer by a chemical mechanical polishing method. The method of claim 31, wherein And a recess of the conductive plug is made by an etch back. The method of claim 31, wherein And removing the capping insulating film and the internal insulating film by a chemical mechanical polishing method. The method of claim 30, And forming a transistor on the semiconductor substrate prior to forming the interlayer insulating film of the second step. The method of claim 30, The metal wiring forming step of the second step is Forming an intaglio pattern through the interlayer insulating layer and the capping insulating layer to expose the upper surface of the conductive plug; And And forming a metal wiring layer to fill the intaglio pattern. The method of claim 30, And backside thinning of the semiconductor substrate in the third step is performed by backgrinding, chemical mechanical polishing or etching. The method of claim 30, And the protrusion of the lower surface of the conductive plug on the back surface of the thinned semiconductor substrate in the third step is performed by over polishing. The method of claim 30, And the protrusion of the lower surface of the conductive plug on the back surface of the thinned semiconductor substrate in the third step is performed by etching. The method of claim 30, The input / output terminal formation of the fourth step is Forming a barrier layer in the intaglio structure and on a lower surface of the back insulation layer; Filling the intaglio structure by forming a conductive stud layer on the barrier layer surface; And Removing the conductive stud layer and the barrier layer until the back insulating layer is exposed to form a conductive stud filling the inside of the intaglio structure. The method of claim 44, Removing the conductive stud layer and the barrier layer by a chemical mechanical polishing method. The method of claim 44, And etching the back insulation layer so that the metal stud protrudes after removing the conductive stud layer and the barrier layer. The method of claim 30, The input / output terminal formation of the fourth step is Forming a UBM layer in the intaglio structure and on a lower surface of the back insulating layer; Masking the UBM layer formed on the inside of the intaglio structure and on the lower surface of the back insulation layer adjacent to the intaglio structure, and masking the remaining portion of the UBM layer as an insulator layer; Forming a bump material on the exposed UBM layer surface; And Removing the insulator layer and the UBM layer masked by the insulator layer to form bumps. The method of claim 30, The input / output terminal formation of the fourth step is Forming a UBM layer in the intaglio structure and on a lower surface of the back insulating layer; Masking the UBM layer covering the lower surface of the conductive plug and the horizontal wall surface of the intaglio structure adjacent to the lower surface of the UBM layer; Forming a bump material on the exposed UBM layer surface; And Removing the insulator layer and the UBM layer masked by the insulator layer to form bumps. 49. The method of claim 47 or 48, And the insulator layer is made of photoresist. 49. The method of claim 47 or 48, And wherein the bump material is formed by a plating method. The method of claim 30, The input / output terminal formation of the fourth step is Forming a barrier layer in the intaglio structure and on a lower surface of the back insulation layer; Forming a pad layer on the barrier layer surface; And Forming a pad by removing the pad layer and the barrier layer in the remaining region except for the lower surface area of the back insulating layer adjacent to the intaglio structure and the intaglio structure by a photolithography and an etching process. Manufacturing method. The method of claim 30, The input / output terminal formation of the fourth step is Forming a barrier layer in the intaglio structure and on a lower surface of the back insulation layer; Forming a pad layer on the barrier layer surface; And And selectively removing the pad layer and the barrier layer in regions other than the inside of the intaglio structure to form a pad. The method of claim 52, wherein And selectively removing the pad layer and the barrier layer by a chemical mechanical polishing method. The method of claim 52, wherein And selectively removing said pad layer and barrier layer by photoresist etch back or SOG etch back. Preparing a semiconductor substrate having a lower surface of the conductive plug protruding from the rear surface thereof; Forming a rear insulating film on a rear surface of the semiconductor substrate to cover the lower surface of the conductive plug; Exposing a bottom surface of the conductive plug by forming a trench defining a rear metal wiring region in the back insulating layer; Filling the trench by sequentially forming a wiring barrier layer and a metal wiring layer in the trench and lower surfaces of the back insulating layer; Removing the metal wiring layer and the wiring barrier layer until the back insulating layer is exposed to form a back metal wiring inside the trench; Forming a back metal interlayer insulating film on the entire back surface of the resultant material; And And forming an intaglio structure in the backside metal interlayer insulating film to expose the backside metal wiring. Preparing a semiconductor substrate having a lower surface of the conductive plug protruding from the rear surface thereof; Forming a rear insulating film on a rear surface of the semiconductor substrate to cover the lower surface of the conductive plug; Forming a first intaglio structure on the back insulating layer to expose a bottom surface of the conductive plug; Sequentially forming a wiring barrier layer and a metal wiring layer on the lower surfaces of the first intaglio structure and the bottom insulating layer; Patterning the metallization layer and the barrier layer to form a backside metallization; Forming a back metal interlayer insulating film on the entire back surface of the resultant material; And And forming a second intaglio structure in the backside metal interlayer insulating film to expose the backside metal wiring. The method of claim 55 or 56, wherein And connecting lower surfaces of the plurality of conductive plugs by the rear metal wiring.

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