JP2013206995A - Method of manufacturing multilayer wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a multilayer wiring board capable of inexpensively manufacturing high quality semiconductor element connection terminals, and thereby capable of enhancing the mounting reliability of the semiconductor element.SOLUTION: A first metal layer 13 is formed on the outermost layer, and after separating a multilayer wiring board 60 where the first metal layer 13 is the bonding surface of a semiconductor element from a temporary wiring board, a photosensitive resin layer 51 is formed on the outermost first metal layer 13, and apertures 52 are formed in the photosensitive resin layer 51 by patterning. Subsequently, conductive balls 53 are mounted on the apertures 52 and fused by heat treatment thus forming a second metal layer 54. Thereafter, the photosensitive resin layer 51 is removed. Finally, the first metal layer 13 is removed excepting that located directly under the second metal layer 54. Consequently, a multilayer wiring board 33 having semiconductor element connection terminals 55 is obtained. A plurality of steps carried out in the conventional manufacturing method become unnecessary.

Description

  The present invention relates to a method for manufacturing a multilayer wiring board used in a semiconductor package, and more particularly, to a manufacturing technique of a semiconductor element connection terminal for joining to an electrode of a semiconductor element.

Conventionally, as one method of manufacturing a multilayer wiring board on which a semiconductor element is mounted, after a required wiring layer and an insulating layer are alternately stacked on a temporary substrate in a separable state, the multilayer wiring layer is removed from the temporary substrate. There is a method of obtaining a multilayer wiring board by separating. Patent Document 1 is known as such a prior art.
The manufacturing method of the multilayer wiring board shown in patent document 1 is demonstrated with reference to FIGS. When manufacturing a multilayer wiring board, as shown in FIG. 6A, a base layer 72 is laminated in the wiring formation regions on both the front and back surfaces of the semi-cured prepreg 71, and the size is slightly larger than the base layer 72. After the metal foils 73 are overlaid, they are heated and pressurized. Thereby, the temporary substrate 90 shown in FIG. 6B is manufactured.

  Next, as shown in FIG. 6C and FIG. 7A, the required noble metal plating layer 74, the first wiring layer 75, the insulating layer 76, the via hole 77, the metal foil 73 necessary for the configuration of the wiring board, A wiring layer 78 is formed. In the same manner, a wiring layer composed of the insulating layer 76, the via hole 77, and the wiring layer 78 is laminated in multiple stages as shown in FIG. Then, by forming the solder resist layer 79, a multilayer wiring board 91 having a temporary substrate is formed.

  Next, as shown in FIG. 7C, the temporary substrate 91 is cut from the temporary substrate 91 from the position indicated by the broken line at the position inside the outer peripheral region where the prepreg 71 and the metal foil 73 are bonded. The multilayer wiring board 92 having the metal foil 73 in close contact with the outermost layer is separated (FIG. 8A). Next, as shown in FIG. 8B, the outermost metal foil 73 is entirely etched, and finally solder bumps 81 are formed on the noble metal plating layer 74 as shown in FIG. 8C. The solder bump 81 is a semiconductor element connection terminal for bonding to the electrode of the semiconductor element. Thereby, the multilayer wiring board 93 is completed.

JP 2009-32918 A

  However, in Patent Document 1 described above, as shown in FIGS. 8A and 8B, after separating the multilayer wiring board 92 having the metal foil 73, it is necessary to etch the entire surface of the outermost metal foil 73. There is. Therefore, it is necessary to form the noble metal plating layer 74 resistant to the etching solution at the interface between the metal foil 73 and the first wiring layer 75. This leads to an increase in cost due to an increase in processes. In addition, the connection strength between the first wiring layer 75 and the solder bump 81 may be reduced due to the influence of the noble metal plating layer 74.

In order to reduce such a possibility, a method in which the metal foil 73 is entirely etched without forming the noble metal plating layer 74 at the interface between the metal foil 73 and the first wiring layer 75 is also conceivable. However, with this method, the first wiring layer 75 may be etched simultaneously with the metal foil 73. Therefore, the variation in height from the outermost surface of the insulating layer 76 to the outermost surface of the first wiring layer 75 may increase due to etching variations. Further, when the above variation becomes large, the height of the solder bump 81 formed in the subsequent process varies, which may reduce the mounting reliability between the semiconductor element and the multilayer wiring board.
Therefore, the present invention was created to solve the above-described problems, and enables the semiconductor element connection terminals to be manufactured at low cost and high quality, and as a result, the reliability of mounting the semiconductor elements. An object of the present invention is to provide a method for manufacturing a multilayer wiring board capable of improving the performance.

  In order to achieve the above object, a method for manufacturing a multilayer wiring board according to the present invention is a method for manufacturing a multilayer wiring board in which a plurality of insulating layers and wiring layers are alternately stacked, and the wiring layer serving as the outermost layer Forming a first metal layer on the outer surface of the substrate, forming a photosensitive resin layer on the first metal layer, patterning the photosensitive resin layer, and wiring the outermost wiring layer A step of forming an opening having the first metal layer as a bottom surface at a position immediately above the pattern; a step of disposing a conductive ball in the opening; and melting the conductive ball by heat treatment to form a second metal layer Forming the second metal layer, removing the photosensitive resin layer after forming the second metal layer, and after removing the photosensitive resin, using the second metal layer as a mask, The first metal layer is removed by etching the metal layer. Forming a terminal portion composed of the genus layer and the second metal layer, characterized in that it comprises a.

In the method for manufacturing a multilayer wiring board, the thickness of the first metal layer may be 1 μm or more and 50 μm or less.
In the method for manufacturing a multilayer wiring board, the second metal layer may have a thickness of 1 μm or more and 50 μm or less.
In the method for manufacturing a multilayer wiring board, the total thickness of the first metal layer and the second metal layer may be 2 μm or more and 50 μm or less.

In the method for manufacturing a multilayer wiring board, the first metal layer may be made of a copper foil.
In the method for manufacturing a multilayer wiring board, the second metal layer may be made of tin or a tin alloy.
In the method for manufacturing a multilayer wiring board, the tin alloy may be any one of tin silver, tin silver copper, tin copper, tin bismuth, and tin lead.

According to the present invention, the entire etching process of the first metal layer and the noble metal plating process for protecting the wiring layer from the entire etching of the first metal layer, which are performed by the conventional manufacturing method, are not required. For this reason, a process can be reduced and, as a result, it becomes possible to reduce the manufacturing cost of a multilayer wiring board.
Further, according to the present invention, a semiconductor element connecting terminal can be constituted by the first metal layer and the second metal layer. There is no need to arrange a noble metal plating layer between the first metal layer and the second metal layer or between the first metal layer and the wiring layer. For this reason, the connection strength between the semiconductor element connection terminal and the wiring layer can be increased, and as a result, the mounting reliability between the semiconductor element and the multilayer wiring board can be improved.

The figure which shows the manufacturing method of the multilayer wiring board which concerns on embodiment of this invention in process order. The figure which shows the manufacturing method of the multilayer wiring board which concerns on embodiment of this invention in process order. The figure which shows the manufacturing method of the multilayer wiring board which concerns on embodiment of this invention in process order. The figure which shows the manufacturing method of the multilayer wiring board which concerns on embodiment of this invention in process order. The figure which shows the manufacturing method of the multilayer wiring board which concerns on embodiment of this invention in process order. The figure which shows the manufacturing method of the multilayer wiring board which concerns on a prior art example in order of a process. The figure which shows the manufacturing method of the multilayer wiring board which concerns on a prior art example in order of a process. The figure which shows the manufacturing method of the multilayer wiring board which concerns on a prior art example in order of a process.

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS.
(Embodiment)
1-5 is sectional drawing which shows the manufacturing method of the multilayer wiring board based on embodiment of this invention in order of a process. In this embodiment, as shown in FIG. 1A, first, a prepreg 11 formed by impregnating a glass cloth, a glass nonwoven fabric or the like with a resin such as a thermosetting resin is prepared. At that time, the prepreg 11 is in a semi-cured state. The thickness of the prepreg is preferably in the range of 400 to 1000 μm. Next, a metal foil 12 having a thickness of 5 to 100 μm and a first metal layer 13 having a thickness of 5 to 35 μm are prepared on both sides of the prepreg 11.

  In this case, the size of the metal foil 12 is the same size as the prepreg 11, but the size of the first metal layer 13 is slightly smaller than the prepreg 11 and the metal foil 12. The first metal layer 13 and the metal foil 12 are preferably the same type of metal. Among them, the first metal layer 13 functions as a semiconductor element connection terminal as will be described later, and thus is preferably a copper foil having excellent electrical conductivity.

  Next, the first metal layer 13 and the metal foil 12 are laminated in this order from the both sides of the prepreg 11. That is, the first metal layer 13 is stacked on the metal foil 12 and the outer peripheral portion thereof is laminated in contact with the prepreg 11. Pressing is performed at a temperature of 150 to 250 ° C. in a vacuum atmosphere from both sides in the state shown in FIG. As a result, when the thermosetting resin in the prepreg 11 is cured, the entire surfaces of the prepreg 11 and the metal foil 12 and the outer peripheral portions of the prepreg 11 and the first metal layer 13 are bonded to each other. That is, a temporary substrate 30 as shown in FIG. 1B is formed.

  Next, although not shown, a plating resist is formed on both surfaces of the temporary substrate 30. This plating resist has an opening for forming a first wiring layer at a required portion corresponding to a wiring pattern of the first wiring layer 15 described later. A liquid or dry film type resist is used as the plating resist. Thereafter, as shown in FIG. 1C, the first wiring layer 15 is formed by electrolytic plating using the first metal layer 13 as a power feeding layer for plating. In that case, as a material of the first wiring layer 15, electrolytic copper plating is desirable. The thickness of the first wiring layer is preferably 10 to 20 μm.

  Next, as shown in FIG. 2A, insulating layers 16 that cover the first wiring layer 15 are formed on both surfaces of the temporary substrate 30. As a material of the insulating layer 16, an epoxy resin, a polyimide resin, or the like is used. The insulating layer 16 is formed by laminating resin films on both surfaces of the temporary substrate 30 and then temporarily curing the resin film while pressing the resin film at a temperature of 80 to 130 ° C., followed by main curing in an oven at 160 to 200 ° C. Thus, the insulating layer 16 is obtained. The thickness of the insulating layer is desirably 10 to 50 μm.

Next, as shown in FIG. 2A as well, a via hole 17 as an opening is formed in the insulating layer 16 by laser processing or the like aiming at the first wiring layer 15 on the temporary substrate 30. As the type of the laser, a CO ₂ laser and a YAG laser are generally used. The diameter of the via hole 17 is preferably 30 to 100 μm. Thereby, the first wiring layer 15 is exposed on the bottom surface of the via hole 17. Thereafter, a wiring layer 18 made of vias and wiring patterns is formed as a metal layer covering the region including the bottom surface and wall surface of the via hole 17 by, for example, a semi-additive method.

  Similarly, as shown in FIG. 2B, the steps of laminating the insulating layer 16, forming the via hole 17, and forming the wiring layer 18 are repeated as many times as necessary to form a required multilayer wiring board. Then, a solder resist layer 19 as a dielectric layer is formed to cover the outermost layer (that is, the uppermost layer) insulating layer 16 and wiring layer 18 and patterned. The thickness of the solder resist layer 19 is preferably 10 to 30 μm. As a patterning method, for example, exposure is performed using a mask (not shown) having an opening at a position corresponding to the external connection pad 20 and development is performed, thereby removing the unexposed solder resist. . As a result, the opening 19a is formed so that the external connection pad 20 forming a part of the outermost wiring layer 18 is exposed. In this way, the multilayer wiring board 31 having the temporary board is formed.

Next, as shown in FIG. 3A, a portion corresponding to the periphery of the metal foil 12 of the multilayer wiring board 31 is cut along a broken line. Thereby, the multilayer wiring formation area | region where the metal foil 12 and the 1st metal layer 13 only contact is obtained, and the metal foil 12 and the 1st metal layer 13 can be isolate | separated easily. Thereby, multilayer wiring boards 32 each having the first metal layer 13 and the multilayer wiring layer formed thereon are obtained from both sides of the temporary board 30 as shown in FIG. 3B.
Thereafter, as shown in FIG. 4A, a photosensitive resin layer 51 is formed on the first metal layer 13 of the temporary substrate 30. The resist used at that time is a resist having plating resistance, and a liquid or dry film type resist is used. The thickness of the dry film resist is preferably 10 to 50 μm.

  Next, as shown in FIG. 4B, the photosensitive resin layer 51 is patterned to form openings 52. Here, the opening 52 is formed at a position of the photosensitive resin layer 51 corresponding to the wiring pattern of the first wiring layer 15 (wiring layer 18). As the patterning method, as described above, for example, the exposed portion of the photosensitive resin layer is exposed and developed using a mask (not shown) having an opening at a position corresponding to the opening 52. 51 is removed. Thereby, the opening 52 is formed so that the first metal layer 13 is exposed. The opening diameter of the opening 52 is preferably 50 to 150 μm.

  Next, as shown in FIG. 4C, the conductive balls 53 are mounted in the openings 52 by a conductive ball mounting machine. Thereafter, the conductive balls 53 are melted by heat treatment such as reflow to form the second metal layer 54. In this case, examples of the material of the conductive ball 53 include tin, or tin alloys such as tin silver, tin silver copper, tin copper, tin bismuth, and tin lead. The ball diameter of the conductive ball 53 is preferably 40 to 100 μm. Thereafter, as shown in FIG. 5A, the photosensitive resin layer 51 is removed.

  Finally, except for the first metal layer 13 located immediately below the second metal layer 54, the other first metal layer 13 is removed. As a method for selectively removing the first metal layer 13, there is a method in which the first metal layer 13 is wet-etched using an alkali etchant or the like using the second metal layer 54 as an etching mask. As a result, as shown in FIG. 5B, a semiconductor element connection terminal 55 composed of the first metal layer 13 and the second metal layer 54 is formed. Through the above steps, the multilayer wiring board 33 having the semiconductor element connection terminals 55 is completed.

  In the embodiment of the present invention, the thickness of the first metal layer 13 is preferably 1 to 50 μm. The reason is that if the thickness of the first metal layer 13 is 1 μm or less, it is very difficult to procure materials from the metal foil manufacturer, and it is very difficult to handle the metal foil when manufacturing the temporary substrate. It is. When the thickness of the first metal layer 13 exceeds 50 μm, the total thickness including the second metal layer 54 exceeds 50 μm. As a result, when a semiconductor element is mounted on a multilayer wiring board, the gap between the semiconductor element and the multilayer wiring board becomes large, so that underfill voids are likely to occur, resulting in a decrease in the reliability of mounting the semiconductor element. Because it will do.

  In the embodiment of the present invention, the thickness of the second metal layer 54 is preferably 1 to 50 μm. The reason is that when the thickness of the second metal layer 54 is 1 μm or less, the wettability between the electrode of the semiconductor element and the second metal layer 54 is lowered, and the connection between the electrode of the semiconductor element becomes unstable. As a result, the reliability of the mounting of the semiconductor element is lowered. When the thickness of the second metal layer 54 exceeds 50 μm, the total thickness including the first metal layer exceeds 50 μm. As a result, when a semiconductor element is mounted on a multilayer wiring board, the gap between the semiconductor element and the multilayer wiring board becomes large, so that underfill voids are likely to occur, resulting in a decrease in the reliability of mounting the semiconductor element. Because it will do.

  In the embodiment of the present invention, the total thickness of the first metal layer 13 and the second metal layer 54 is preferably 2 to 50 μm. The reason is that if the sum of the thicknesses of the first metal layer 13 and the second metal layer 54 is 2 μm or less, it is very difficult to procure materials from the metal foil manufacturer, and the metal foil is used in the production of the temporary substrate. This is because the handling becomes very difficult. In addition, the wettability between the electrode of the semiconductor element and the second metal layer 54 is reduced, the connection with the electrode of the semiconductor element becomes unstable, and as a result, the reliability of mounting of the semiconductor element is reduced. is there. If the sum of the thicknesses of the first metal layer 13 and the second metal layer 54 exceeds 50 μm, the gap between the semiconductor element and the multilayer wiring board becomes large when the semiconductor element is mounted on the multilayer wiring board. This is because fill voids are likely to occur, and as a result, the reliability of mounting the semiconductor element is lowered.

(Effect of embodiment)
According to the embodiment of the present invention, the entire etching process of the first metal layer and the noble metal plating process for protecting the wiring layer from the entire etching of the first metal layer, which are performed by the conventional manufacturing method, are not required. . For this reason, a process can be reduced and, as a result, it becomes possible to reduce the manufacturing cost of a multilayer wiring board.

  Further, according to the embodiment of the present invention, as shown in FIG. 5B, the first metal layer 13 and the second metal layer 54 can constitute the semiconductor element connection terminal 55. There is no need to dispose a noble metal plating layer between the first metal layer 13 and the second metal layer 54 or between the first metal layer 13 and the first wiring layer 15. For this reason, the connection strength between the semiconductor element connection terminal 55 and the first wiring layer 15 can be increased, and as a result, the mounting reliability between the semiconductor element and the multilayer wiring board can be greatly improved.

  Further, according to the embodiment of the present invention, it is possible to form the second metal layer 54 with less thickness variation by using the conductive ball 53 with a small volume variation in FIG. is there. As a result, it is possible to form the semiconductor element connection terminal 55 with a smaller variation in height, and finally it is possible to greatly improve the connection reliability between the semiconductor element and the multilayer wiring board.

  The multilayer wiring board of the present invention improves the connection reliability between the semiconductor element and the multilayer wiring board. The multilayer wiring board having such characteristics can be widely applied as a semiconductor package including, for example, an MPU, a chip set, a memory, and the like.

DESCRIPTION OF SYMBOLS 11 Prepreg 12 Metal foil 13 1st metal layer 14 Noble metal plating layer 15 1st wiring layer 16 Insulating layer 17 Via hole 18 Wiring layer 19 Solder resist layer 20 External connection pad 30 Temporary board 31 Multilayer wiring board 32 (with temporary board) Multilayer wiring board 33 (having a semiconductor element connecting terminal) (having a first metal layer after being separated from the temporary substrate) Multilayer wiring board 51 Photosensitive resin layer 52 Opening 53 Conductive ball 54 Second metal layer 55 Semiconductor Element connection terminal (terminal part)

Claims (7)

A method of manufacturing a multilayer wiring board in which a plurality of insulating layers and wiring layers are alternately laminated,
Forming a first metal layer on the outer surface of the wiring layer to be the outermost layer;
Forming a photosensitive resin layer on the first metal layer;
Patterning the photosensitive resin layer, and forming an opening having the first metal layer as a bottom surface at a position immediately above the wiring pattern of the outermost wiring layer;
Placing a conductive ball in the opening;
Melting the conductive ball by heat treatment to form a second metal layer;
Removing the photosensitive resin layer after forming the second metal layer;
After removing the photosensitive resin, the first metal layer and the second metal layer are removed by etching and removing the first metal layer using the second metal layer as a mask. And a step of forming the multilayer wiring board.   The method of manufacturing a multilayer wiring board according to claim 1, wherein the thickness of the first metal layer is 1 μm or more and 50 μm or less.   3. The method of manufacturing a multilayer wiring board according to claim 1, wherein a thickness of the second metal layer is 1 μm or more and 50 μm or less. 4.   4. The multilayer wiring board according to claim 1, wherein a total thickness of the first metal layer and the second metal layer is 2 μm or more and 50 μm or less. 5. Method.   The said 1st metal layer consists of copper foil, The manufacturing method of the multilayer wiring board as described in any one of Claims 1-4 characterized by the above-mentioned.   6. The method for manufacturing a multilayer wiring board according to claim 1, wherein the second metal layer is made of tin or a tin alloy. The method for manufacturing a multilayer wiring board according to claim 6, wherein the tin alloy is made of any one of tin silver, tin silver copper, tin copper, tin bismuth, and tin lead.

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