JP2012114110A - Method for manufacturing multilayer wiring board - Google Patents

Method for manufacturing multilayer wiring board Download PDF

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Publication number
JP2012114110A
JP2012114110A JP2010259184A JP2010259184A JP2012114110A JP 2012114110 A JP2012114110 A JP 2012114110A JP 2010259184 A JP2010259184 A JP 2010259184A JP 2010259184 A JP2010259184 A JP 2010259184A JP 2012114110 A JP2012114110 A JP 2012114110A
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metal layer
layer
wiring board
semiconductor element
multilayer wiring
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JP2010259184A
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Japanese (ja)
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Eiji Yabuta
英二 藪田
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Toppan Printing Co Ltd
凸版印刷株式会社
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Priority to JP2010259184A priority Critical patent/JP2012114110A/en
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Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a multilayer wiring board, capable of manufacturing semiconductor element connection terminals to be jointed to electrodes of a semiconductor element at low cost and with high quality, and improving reliability in mounting the semiconductor element.SOLUTION: A method for manufacturing a multilayer wiring board 61 having semiconductor element connection terminals 54, comprises: separating from a temporary base plate a multilayer wiring board 60 having a first metal layer 13 formed on its outermost layer as a joint surface of a semiconductor element; then forming a photosensitive resin layer 51 on the first metal layer 13 of the outermost layer; then forming connection terminal openings 52 of the semiconductor element in the photosensitive resin layer 51 by patterning so as to correspond to a wiring pattern of the first wiring layer 15; then forming a second metal layer 53 in the openings 52 by electroplating, using the first metal layer 13 as a power-supply layer; and then removing the photosensitive resin layer 51, and finally removing the first metal layer 13 other than the first metal layer 13 located directly under the second metal layer 53 to form the semiconductor element connection terminals 54.

Description

  The present invention relates to a method for manufacturing a multilayer wiring board used in a semiconductor package. More specifically, the present invention relates to a method for manufacturing a connection terminal for a semiconductor element for joining with an electrode of the semiconductor element.

  Conventionally, as a method of manufacturing a multilayer wiring board on which a semiconductor element is mounted, a required wiring layer and an insulating layer are alternately stacked on a temporary substrate in a state where they can be separated, and then the multilayer wiring layer is separated from the temporary substrate. Thus, there is a method for obtaining a multilayer wiring board. Patent Document 1 is known as such a prior art.

The manufacturing method of the multilayer wiring board shown in patent document 1 is demonstrated with reference to FIGS.
When manufacturing a multilayer wiring board, as shown in FIG. 1A, a base layer 72 is laminated in the wiring formation regions on both the front and back surfaces of the semi-cured prepreg 71, and the size is slightly larger than the base layer 72. After the metal foils 73 are overlaid, the temporary substrates 90 shown in FIG. 1B are manufactured by heating and pressing them. Next, as shown in FIGS. 1C and 1D, the required noble metal plating layer 74, the first wiring layer 75, the insulating layer 76, the via hole 77, and the wiring layer necessary for the configuration of the wiring board are formed on the metal foil 73. 78 is formed. In the same manner, wiring layers including insulating layers 76, via holes 77, and wiring layers 78 are laminated in multiple stages as shown in FIG. Then, a multilayer wiring board is formed by forming a solder resist layer 79. Next, as shown in FIG. 2 (f), the inner side of the outer peripheral region where the prepreg 71 and the metal foil 73 are bonded is cut from the position indicated by the broken line, so that the metal is transferred from the temporary substrate 90 to the outermost layer. The multilayer wiring board 91 to which the foil 73 is in close contact is separated as shown in FIG. Next, as shown in FIG. 3 (h), the outermost metal foil 73 is entirely etched, and finally, as shown in FIG. 3 (i), solder bumps 81 are formed on the semiconductor element connection pads 88, thereby providing a multilayer wiring board. 92 is manufactured.

JP2009-32918

  However, in Patent Document 1 described above, it is necessary to etch the entire surface of the outermost metal foil 73 after separating the multilayer wiring board 91 having the metal foil 73. Therefore, it is necessary to form a noble metal plating layer 74 resistant to the etching solution at the interface between the metal foil 73 and the first wiring layer, which leads to an increase in cost due to an increase in the number of steps. As another manufacturing method, a method of performing etching without forming the noble metal plating layer 74 at the interface between the metal foil 73 and the first wiring layer 75 is conceivable. In this case, however, the first wiring layer 75 is also simultaneously formed. It will be etched. For this reason, it is difficult to control the height from the outermost surface of the insulating layer 76 to the outermost surface of the first wiring layer due to etching variations. As a result, the height of the solder bumps for joining with the electrodes of the semiconductor element, which will be the subsequent process, varies, and the mounting reliability of the semiconductor element is reduced.

  The present invention has been created to solve the above-described problems. After a required wiring layer and an insulating layer are laminated on a temporary substrate in a state where they can be separated, the multilayer wiring layer is formed on the temporary substrate. In a manufacturing method for obtaining a multilayer wiring board separated from a semiconductor device, it is possible to manufacture a semiconductor device connection terminal to be bonded to an electrode of a semiconductor device at low cost and high quality, and as a result, improve the reliability of mounting of the semiconductor device. It is an object of the present invention to provide a method for manufacturing a multilayer wiring board that can be made to operate.

  In order to achieve the above object, a manufacturing method of a multilayer wiring board according to the present invention includes a multi-layered wiring board in which a plurality of insulating layers and wiring layers are alternately stacked, and the wiring layers are connected via via holes. Forming a photosensitive resin layer on the first metal layer in a multilayer wiring board in which a first metal layer is formed on an outer layer, and the first metal layer is a bonding surface of a semiconductor element; and the photosensitive resin Forming a connection terminal opening of the semiconductor element in the layer corresponding to the wiring pattern of the wiring layer, and using the first metal layer as a power feeding layer, the second metal layer by electrolytic plating in the connection terminal opening And the semiconductor resin connection terminal by removing the photosensitive resin layer and removing the other first metal layer except for the first metal layer located immediately below the second metal layer. And a step of forming .

  According to a second aspect of the present invention, in the method for manufacturing a multilayer wiring board according to the first aspect, the thickness of the first metal layer is 1 to 50 μm.

  According to a third aspect of the present invention, in the method for manufacturing a multilayer wiring board according to the first or second aspect, the thickness of the second metal layer is 1 to 50 μm.

  According to a fourth aspect of the present invention, in the method for manufacturing a multilayer wiring board according to any one of the first to third aspects, the total thickness of the first metal layer and the second metal layer is 2 to 50 μm. Features.

  The invention according to claim 5 is the method for producing a multilayer wiring board according to any one of claims 1 to 4, wherein the second metal layer is tin, tin silver, tin silver copper, tin copper, tin bismuth, tin lead. It consists of any of these.

  As described above, according to the method for manufacturing a multilayer wiring board according to the present invention, the first metal in the outermost layer of the multilayer wiring board, which is required in the conventional manufacturing method for forming a multilayer wiring board on a temporary substrate, is provided. Since the entire surface etching process of the layer and the precious metal plating process on the first metal layer necessary for protecting the first wiring layer from the etching of the first metal layer are not required, the process can be reduced, resulting in cost reduction. Will be connected.

In addition, according to the present invention, the first metal layer can be used as it is as a part of a connection terminal for a semiconductor element that connects the semiconductor element and the electrode as it is, so that the first metal layer is often applied to a conventional multilayer wiring board. The strength of the connection terminal for the semiconductor element is increased as compared with the connection terminal for the semiconductor element using only solder, and as a result, the reliability of mounting the semiconductor element is greatly improved.
According to the present invention, the second metal layer having a low melting point and high fluidity and wettability can be formed by using a tin-based alloy. As a result, the connection reliability with the electrode of the semiconductor element is improved, and the mounting reliability with the semiconductor element can be improved.

(A)-(d) is sectional drawing for description which shows the process sequence by the manufacturing method of the multilayer wiring board using the conventional temporary board | substrate. (E)-(g) is sectional drawing for description which shows the process procedure by the manufacturing method of the multilayer wiring board using the conventional temporary board | substrate. (H), (i) is sectional drawing for description which shows the process procedure by the manufacturing method of the multilayer wiring board using the conventional temporary board | substrate. (A)-(d) is sectional drawing for description which shows the process sequence by the manufacturing method of the multilayer wiring board using the temporary board | substrate of this invention. (E)-(g) is sectional drawing for description which shows the process procedure by the manufacturing method of the multilayer wiring board using the temporary board | substrate of this invention. (A)-(c) is sectional drawing for description which shows the process sequence by the manufacturing method of the multilayer wiring board using the temporary board | substrate of this invention. (D), (e) is sectional drawing for description which shows the process sequence by the manufacturing method of the multilayer wiring board using the temporary board | substrate of this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS.

  In the method for manufacturing a multilayer wiring board shown in the present embodiment, as shown in FIG. 4A, first, a prepreg formed by impregnating a glass cloth, a glass nonwoven fabric, or the like with a resin such as a thermosetting resin. 11 is prepared. At that time, the prepreg 11 is in a semi-cured state. Next, a metal foil 12 having a thickness of 5 to 100 μm and a first metal layer 13 having a thickness of 5 to 35 μm are prepared on both sides of the prepreg 11. In this case, the size of the metal foil 12 is the same size as the prepreg 11, but the size of the first metal layer 13 is slightly smaller than the prepreg 11 and the metal foil 12.

  Next, the first metal layer 13 and the metal foil 12 are laminated in this order from the both sides of the prepreg 11. That is, the first metal layer 13 is stacked on the metal foil 12 and the outer peripheral portion thereof is laminated in contact with the prepreg 11. In the state shown in FIG. 4A, pressing is performed at a temperature of 150 to 250 ° C. in a vacuum atmosphere from both sides. As a result, when the thermosetting resin in the prepreg 11 is cured, the entire surfaces of the prepreg 11 and the metal foil 12 and the outer peripheral portions of the prepreg 11 and the first metal layer 13 are bonded to each other. That is, a temporary substrate 30 as shown in FIG. 4B is formed. The first metal layer 13 functions as a semiconductor element connection terminal 54 as shown in FIG.

  Next, although not shown in the drawing, a plating resist in which openings for forming a first wiring layer are provided in required portions corresponding to a wiring pattern of the first wiring layer 15 described later is formed on both surfaces of the temporary substrate 30. . The resist used at this time is a liquid or dry film type resist. Thereafter, as shown in FIG. 4C, the first wiring layer 15 is formed by electrolytic plating using the first metal layer 13 as a power feeding layer for plating. In that case, as a material of the first wiring layer 15, electrolytic Cu plating is desirable.

  Next, as illustrated in FIG. 4D, insulating layers 16 that cover the first wiring layer 15 and the first metal layer 15 are formed on both surfaces of the temporary substrate 30. As a material of the insulating layer 16, an epoxy resin, a polyimide resin, or the like is used. The insulating layer 16 is formed by laminating resin films on both surfaces of the temporary substrate 30 and then temporarily curing the resin film while pressing the resin film at a temperature of 80 to 130 ° C., followed by main curing in an oven at 160 to 200 ° C. Thus, the insulating layer 16 is obtained.

  Next, as shown in FIG. 4D, via holes 17 as openings are formed in the insulating layer 16 by laser processing or the like aiming at the first wiring layer 13 on the temporary substrate 30. Thereby, the first wiring layer 15 is exposed on the bottom surface of the via hole 17. Thereafter, for example, a wiring layer 18 made of a via and a wiring pattern is formed as a metal layer covering a region including the bottom surface and the wall surface of the via hole 17 by a semi-additive method or the like.

  Similarly, as shown in FIG. 5E, the steps of laminating the insulating layer 16, forming the via hole 17, and forming the wiring layer 18 are repeated as many times as necessary to form a required multilayer wiring board. Form. Then, a solder resist layer 19 as a dielectric layer is formed so as to cover the uppermost insulating layer 16 and wiring layer 18 and patterned. As a patterning method, for example, by exposing and developing using a mask (not shown) having an opening at a position corresponding to the external connection terminal pad 20, the solder resist in an unexposed portion is removed. The opening 19a is formed so that the external connection terminal pad 20 of the uppermost wiring layer 18 is exposed.

  Next, as shown in FIG. 5F, cutting is performed along the broken line at a portion corresponding to the peripheral edge of the metal foil 12 of the temporary substrate 30 in FIG. Thereby, the multilayer wiring formation area | region where the metal foil 12 and the 1st metal layer 13 only contact is obtained, and the metal foil 12 and the 1st metal layer 13 can be isolate | separated easily. As a result, as shown in FIG. 5G, multilayer wiring boards 60 each having a metal layer composed of the first metal layer 13 and the multilayer wiring layer formed thereon are obtained from both sides of the temporary board 30, respectively. .

  Thereafter, as shown in FIG. 6A, a photosensitive resin 51 is formed on the first metal layer 13 of the temporary substrate 30. The resist used at that time is a resist having plating resistance, and a liquid or dry film type resist is used.

  Next, as shown in FIG. 6B, the connection terminal opening 52 of the semiconductor element is patterned in the photosensitive resin 51 corresponding to the wiring pattern of the first wiring layer 15 (wiring layer 18). As the patterning method, as described above, for example, the exposed portion of the photosensitive resin 51 is exposed and developed using a mask (not shown) having an opening at a position corresponding to the opening 52. And an opening 52 is formed so that the first metal layer 13 is exposed.

  Next, as shown in FIG. 6C, electrolytic plating is performed on the opening pattern 52 using the first metal layer 13 as a power feeding layer to form a second metal layer 53. In this case, examples of the material of the second metal layer 53 include tin, tin silver, tin silver copper, tin copper, tin bismuth, and tin lead. Thereafter, as shown in FIG. 7D, the photosensitive resin layer 51 is removed.

  Finally, as shown in FIG. 7 (d), the photosensitive resin layer 51 is removed, and the first metal layer 13 other than the first metal layer 13 located immediately below the second metal layer 53 is removed. Remove. As a method for selectively removing the first metal layer 13, the first metal at a position located immediately below the second metal layer 53 is obtained by wet etching using an alkaline etchant liquid or the like using the second metal layer 53 as an etching mask. The first metal layer 13 other than the layer 13 is removed. As a result, as shown in FIG. 7E, a semiconductor element connection terminal 54 composed of the first metal layer 13 and the second metal layer 53 is formed. Thus, the multilayer wiring board 61 having the semiconductor element connection terminals 54 is manufactured.

  In this Embodiment, it is preferable that the thickness of the 1st metal layer 13 is 1-50 micrometers. In this case, if the thickness of the first metal layer 13 is 1 μm or less, it is very difficult to procure materials from the metal foil manufacturer, and it is very difficult to handle the metal foil when manufacturing the temporary substrate. When the thickness of the first metal layer 13 exceeds 50 μm, the total thickness including the second metal layer 53 exceeds 50 μm. As a result, when a semiconductor element is mounted on a multilayer wiring board, the gap between the semiconductor element and the multilayer wiring board becomes large, so that underfill voids are likely to occur, resulting in a decrease in the reliability of mounting the semiconductor element. Will be.

  Moreover, in this Embodiment, it is preferable that the thickness of the 2nd metal layer 53 is 1-50 micrometers. In this case, if the thickness of the second metal layer 53 is 1 μm or less, the wettability between the electrode of the semiconductor element and the second metal layer 53 decreases, and the connection between the electrode of the semiconductor element becomes unstable. As a result, the reliability of mounting the semiconductor element is lowered. When the thickness of the second metal layer 53 exceeds 50 μm, the total thickness including the first metal layer exceeds 50 μm. As a result, when a semiconductor element is mounted on a multilayer wiring board, the gap between the semiconductor element and the multilayer wiring board becomes large, so that underfill voids are likely to occur, resulting in a decrease in the reliability of mounting the semiconductor element. Will be.

  In the present embodiment, the total thickness of the first metal layer 13 and the second metal layer 53 is preferably 2 to 50 μm. In this case, if the sum of the thicknesses of the first metal layer 13 and the second metal layer 53 is 2 μm or less, it is very difficult to procure materials from the metal foil manufacturer, and the metal foil of the temporary substrate is manufactured when the temporary substrate is manufactured. Handling becomes very difficult. In addition, the wettability between the electrode of the semiconductor element and the second metal layer 53 is lowered, the connection between the electrode of the semiconductor element becomes unstable, and as a result, the reliability of mounting the semiconductor element is lowered. If the sum of the thicknesses of the first metal layer 13 and the second metal layer 53 exceeds 50 μm, the gap between the semiconductor element and the multilayer wiring board becomes large when the semiconductor element is mounted on the multilayer wiring board. Fill voids are likely to occur, and as a result, the reliability of mounting the semiconductor element is lowered.

  As described above, according to the present invention, the entire surface of the outermost first metal layer of the multilayer wiring substrate is etched, and the first metal necessary for protecting the first wiring layer from the etching of the first metal layer. Since the noble metal plating step on the layer is not necessary, the number of steps can be reduced, resulting in cost reduction. In addition, since the first metal layer can be used as part of a connection terminal for a semiconductor element that connects the semiconductor element and the electrode as it is, for a solder-only semiconductor element that is often applied to conventional multilayer wiring boards. Compared with the connection terminal, the strength of the connection terminal for the semiconductor element is increased, and the reliability of mounting the semiconductor element is greatly improved. In addition to this, quality can be improved and the multilayer wiring board having such characteristics can be widely applied as, for example, a semiconductor package including an MPU, a chip set, a memory, or a coreless package.

DESCRIPTION OF SYMBOLS 11 ... Prepreg 12 ... Metal foil 13 ... 1st metal layer 15 ... 1st wiring layer 16 ... Insulating layer 17 ... Via hole 18 ... Wiring layer 19 ... Solder resist layer 20 ... External connection terminal pad 30 ... Temporary substrate 51 ... Photosensitivity Resin layer 52 ... Opening 53 ... Second metal layer 54 ... Connection terminal for semiconductor element 60 ... Multi-layer wiring board 61 ... Multi-layer wiring board having metal layer

Claims (5)

  1. A plurality of insulating layers and wiring layers are alternately stacked, and a first metal layer is formed on the outermost layer of a multilayer wiring board in which each wiring layer is connected via a via hole, and the first metal layer is formed of a semiconductor element. In the multilayer wiring board that becomes the bonding surface,
    Forming a photosensitive resin layer on the first metal layer;
    Forming a connection terminal opening of the semiconductor element in the photosensitive resin layer corresponding to the wiring pattern of the wiring layer;
    Forming the second metal layer by electrolytic plating in the connection terminal opening using the first metal layer as a power feeding layer;
    Removing the photosensitive resin layer, removing the first metal layer other than the first metal layer located immediately below the second metal layer to form a semiconductor element connection terminal;
    A method for producing a multilayer wiring board, comprising:
  2.   2. The method of manufacturing a multilayer wiring board according to claim 1, wherein the first metal layer has a thickness of 1 to 50 [mu] m.
  3.   3. The method for manufacturing a multilayer wiring board according to claim 1, wherein the thickness of the second metal layer is 1 to 50 [mu] m.
  4.   4. The method of manufacturing a multilayer wiring board according to claim 1, wherein a total thickness of the first metal layer and the second metal layer is 2 to 50 μm. 5.
  5.   5. The method of manufacturing a multilayer wiring board according to claim 1, wherein the second metal layer is made of any one of tin, tin silver, tin silver copper, tin copper, tin bismuth, and tin lead. .
JP2010259184A 2010-11-19 2010-11-19 Method for manufacturing multilayer wiring board Pending JP2012114110A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018194367A1 (en) * 2017-04-18 2018-10-25 (주)잉크테크 Method for manufacturing printed circuit board

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006019591A (en) * 2004-07-02 2006-01-19 Ngk Spark Plug Co Ltd Method for manufacturing wiring board and wiring board
JP2009032918A (en) * 2007-07-27 2009-02-12 Shinko Electric Ind Co Ltd Wiring substrate, manufacturing method thereof, electronic component device, and manufacturing method thereof
JP2010226075A (en) * 2009-03-23 2010-10-07 Ibiden Co Ltd Wiring board and method for manufacturing the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006019591A (en) * 2004-07-02 2006-01-19 Ngk Spark Plug Co Ltd Method for manufacturing wiring board and wiring board
JP2009032918A (en) * 2007-07-27 2009-02-12 Shinko Electric Ind Co Ltd Wiring substrate, manufacturing method thereof, electronic component device, and manufacturing method thereof
JP2010226075A (en) * 2009-03-23 2010-10-07 Ibiden Co Ltd Wiring board and method for manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018194367A1 (en) * 2017-04-18 2018-10-25 (주)잉크테크 Method for manufacturing printed circuit board

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