JP2007096028A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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JP2007096028A
JP2007096028A JP2005283956A JP2005283956A JP2007096028A JP 2007096028 A JP2007096028 A JP 2007096028A JP 2005283956 A JP2005283956 A JP 2005283956A JP 2005283956 A JP2005283956 A JP 2005283956A JP 2007096028 A JP2007096028 A JP 2007096028A
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thin film
resin substrate
semiconductor device
semiconductor chip
film resin
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Miho Inata
美保 生稲
Koichi Watabe
浩一 渡部
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Toppan Inc
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Toppan Printing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of preventing a thin film resin substrate from being warped when underfill resin is hardened, and to provide its manufacturing method. <P>SOLUTION: The semiconductor device is equipped with the thin film resin substrate, a semiconductor chip mounted on the thin film resin substrate through a conductive joint, and a support plate that is bonded to the semiconductor chip through a first adhesive joint and bonded to the thin film resin substrate through a second adhesive joint, and the conductive joint is sealed with the underfill resin. The support plate of the semiconductor device has a through-hole filled with the underfill resin. The method of manufacturing the semiconductor device is provided. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明はコアを有さない薄膜樹脂基板上に半導体チップを実装し、実装部分をアンダーフィル樹脂で封止して構成される半導体装置に関し、特に、アンダーフィル樹脂の硬化による基板の変形を防止した半導体装置に関するものである。   The present invention relates to a semiconductor device configured by mounting a semiconductor chip on a thin film resin substrate having no core and sealing the mounting portion with an underfill resin, and in particular, prevents deformation of the substrate due to curing of the underfill resin. The present invention relates to a semiconductor device.

それぞれの表面に半田バンプが形成された薄膜樹脂基板４と半導体チップ１をフェースダウンにより搭載、溶融接続されることで形成される半導体装置が知られている。   2. Description of the Related Art There is known a semiconductor device formed by mounting a thin film resin substrate 4 having a solder bump formed on each surface and a semiconductor chip 1 by face-down and being melt-connected.

例えば図８の様な半導体装置８で用いられる薄膜樹脂基板４のチップ搭載部には、図９の様なはんだバンプなどの電気的導通部２が形成されている。なお、薄膜樹脂基板４の外縁部にはスティフナ３と呼ばれる補強材が貼り合わされているものが多い。   For example, an electrically conductive portion 2 such as a solder bump as shown in FIG. 9 is formed on the chip mounting portion of the thin film resin substrate 4 used in the semiconductor device 8 as shown in FIG. In many cases, a reinforcing material called a stiffener 3 is bonded to the outer edge of the thin film resin substrate 4.

通常この状態で薄膜樹脂基板４に半導体チップ１が搭載され、その後半導体装置８の電気的導通部２には補強のためアンダーフィル樹脂５が図１０の様に注入される。アンダーフィル樹脂５注入後、半導体チップ１とスティフナ３の上部に導電性の接着剤を塗布して接着部７ａ、７ｂを設け、半導体チップ１とスティフナ３の上部にリッド（蓋）と呼ばれる支持板６を配置し硬化させ、固着され半導体装置が得られる。   Normally, the semiconductor chip 1 is mounted on the thin film resin substrate 4 in this state, and then the underfill resin 5 is injected into the electrically conductive portion 2 of the semiconductor device 8 for reinforcement as shown in FIG. After injecting the underfill resin 5, a conductive adhesive is applied to the top of the semiconductor chip 1 and the stiffener 3 to provide adhesive portions 7 a and 7 b, and a support plate called a lid (lid) is provided on the top of the semiconductor chip 1 and the stiffener 3. The semiconductor device is obtained by arranging and curing 6 and fixing.

なお、支持板６を取りつけた後、薄膜樹脂基板４の半導体チップ１が搭載されていない面にある電極パッド上に半田ボール９を搭載させる場合もある。このような半導体装置は半田ボール９が搭載されている面を親基板側にして、親基板に実装される。   In addition, after attaching the support plate 6, the solder ball 9 may be mounted on the electrode pad on the surface of the thin film resin substrate 4 where the semiconductor chip 1 is not mounted. Such a semiconductor device is mounted on the parent substrate with the surface on which the solder balls 9 are mounted facing the parent substrate.

しかし、これではアンダーフィル樹脂５が硬化する際、半導体チップ１と薄膜樹脂基板４には熱膨張係数の違いによる応力がかかり、薄膜樹脂基板４が大きく変形しまうことがある。   However, in this case, when the underfill resin 5 is cured, stress is applied to the semiconductor chip 1 and the thin film resin substrate 4 due to a difference in thermal expansion coefficient, and the thin film resin substrate 4 may be greatly deformed.

薄膜樹脂基板に変形があると、半導体装置の親基板への実装が困難になる場合がある。また、変形の大きい部分では、薄膜樹脂基板内のビアやはんだバンプ応力がかかっており、温度サイクル試験等の信頼性試験で断線の原因となってしまう。   If the thin film resin substrate is deformed, it may be difficult to mount the semiconductor device on the parent substrate. Moreover, in the part with large deformation, vias and solder bump stress in the thin film resin substrate are applied, which may cause disconnection in a reliability test such as a temperature cycle test.

特許文献は以下の通り。
特開２０００−３１３４５号公報 The patent literature is as follows.
JP 2000-31345 A

本発明は、上記問題点に鑑み考案されたもので、薄膜樹脂基板へアンダーフィル塗布後に発生する薄膜樹脂基板の変形を抑えることで、親基板への実装性を向上させ、さらに、薄膜樹脂基板の変形によるビアや半田に掛かる応力を緩和させることで、接続信頼性を向上させることを目的としている。   The present invention was devised in view of the above problems, and by suppressing the deformation of the thin film resin substrate that occurs after the underfill application to the thin film resin substrate, the mountability to the parent substrate is improved, and further, the thin film resin substrate The purpose is to improve the connection reliability by alleviating the stress applied to the via and solder due to the deformation.

第１の請求項に係る本発明は、薄膜樹脂基板と、
当該薄膜樹脂基板上に導電性接続部を介して実装されている半導体チップと、
当該半導体チップとは第一の接着部を介して、当該薄膜樹脂基板とは第二の接着部を介して接着されている支持板を具備し、
前記導電性接続部はアンダーフィル樹脂で封止されている半導体装置であって、
前記支持板がアンダーフィル樹脂充填用貫通孔を有することを特徴とする半導体装置を提供するものである。 The present invention according to the first claim comprises a thin film resin substrate,
A semiconductor chip mounted on the thin film resin substrate via a conductive connection part;
The semiconductor chip includes a support plate that is bonded via a first bonding portion, and the thin film resin substrate is bonded via a second bonding portion;
The conductive connection part is a semiconductor device sealed with an underfill resin,
The support plate has a through-hole for filling an underfill resin, and a semiconductor device is provided.

また、第２の請求項に係る本発明は、前記薄膜樹脂基板の厚さは０．０５ｍｍ以上０．３ｍｍ以下であることを特徴とする請求項１記載の半導体装置を提供するものである。   According to a second aspect of the present invention, there is provided the semiconductor device according to the first aspect, wherein the thickness of the thin film resin substrate is 0.05 mm or more and 0.3 mm or less.

さらに、第３の請求項に係る本発明は、薄膜樹脂基板と、
当該薄膜樹脂基板上に導電性接続部を介して実装されている半導体チップと、
当該半導体チップとは第一の接着部を介して、当該薄膜樹脂基板とは第二の接着部を介して接着されている支持板を具備し、
前記導電性接続部はアンダーフィル樹脂で封止されている半導体装置の製造方法であって、
前記半導体チップの実装と、第一の接着部及び第二の接着部の硬化後に前記アンダーフィル樹脂の硬化を行うことを特徴とする半導体装置の製造方法を提供するものである。 Furthermore, the present invention according to the third claim comprises a thin film resin substrate,
A semiconductor chip mounted on the thin film resin substrate via a conductive connection part;
The semiconductor chip includes a support plate that is bonded via a first bonding portion, and the thin film resin substrate is bonded via a second bonding portion;
The conductive connection part is a manufacturing method of a semiconductor device sealed with an underfill resin,
The present invention provides a method for manufacturing a semiconductor device, wherein the underfill resin is cured after the semiconductor chip is mounted and the first adhesive portion and the second adhesive portion are cured.

最後に、第４の請求項に係る本発明は、前記支持板はアンダーフィル樹脂充填用貫通孔を具備し、
前記半導体チップの実装と、第一の接着部及び第二の接着部の硬化後に当該アンダーフィル樹脂充填用貫通孔からアンダーフィル樹脂を前記導電性接続部に充填し、硬化を行うことを特徴とする請求項３記載の半導体装置の製造方法を提供するものである。 Finally, according to the fourth aspect of the present invention, the support plate includes a through-hole for filling an underfill resin,
After the mounting of the semiconductor chip and the first adhesive part and the second adhesive part are cured, the conductive film is filled with the underfill resin from the underfill resin filling through-hole and cured. A method of manufacturing a semiconductor device according to claim 3 is provided.

支持板を搭載、硬化することで、薄膜樹脂基板にテンションをかけても薄膜樹脂基板の変形が支持板との接着で制限され、薄膜樹脂基板の変形圧力に耐えることが可能になったために、この状態でアンダーフィルを塗布、硬化することで、アンダーフィル硬化時の薄膜樹脂基板の反りを防ぐことが可能になる。   By mounting and curing the support plate, deformation of the thin film resin substrate is limited by adhesion with the support plate even when tension is applied to the thin film resin substrate, and it is possible to withstand the deformation pressure of the thin film resin substrate. By applying and curing the underfill in this state, it becomes possible to prevent the thin film resin substrate from warping during the underfill curing.

薄膜樹脂基板の反りを防止することで、親基板への実装性を向上させ、また、変形によるビアへ掛かる応力を緩和し、信頼性を向上させることが可能となる。   By preventing warping of the thin film resin substrate, it is possible to improve the mountability to the parent substrate, to relieve stress applied to the via due to deformation, and to improve the reliability.

まず、本発明の半導体装置を図１を用いてその実施の形態を以て以下説明する。   First, a semiconductor device of the present invention will be described below with reference to an embodiment thereof with reference to FIG.

半導体装置８の構造としては、薄膜樹脂基板４と、薄膜樹脂基板４上に導電性接続部２を介して実装されている半導体チップ１と、半導体チップ１とは第一の接着部７ａを介して、薄膜樹脂基板４とはステフィナ３を介して第二の接着部７ｂで接着されている支持板６を具備し、前記導電性接続部２はアンダーフィル樹脂５で封止されている。また、前記支持板がアンダーフィル樹脂充填用貫通孔Ａを有する。   The structure of the semiconductor device 8 is as follows: the thin film resin substrate 4, the semiconductor chip 1 mounted on the thin film resin substrate 4 via the conductive connection portion 2, and the semiconductor chip 1 via the first bonding portion 7a. The support plate 6 is bonded to the thin film resin substrate 4 through the stepfina 3 with the second bonding portion 7b, and the conductive connection portion 2 is sealed with the underfill resin 5. Moreover, the said support plate has the through-hole A for underfill resin filling.

この場合の薄膜樹脂基板とは、例えばポリイミド等のフィルム状絶縁樹脂からなる絶縁層と例えば銅などの導電性薄膜からなる配線層を積層したプリント配線板であって、いわゆるコアを有さず、可とう性のあるプリント配線板である。その厚みは０．０５ｍｍ以上０．３ｍｍ以下が好ましい。この厚みが０．０５ｍｍ以上が好ましいのは、基板として機能する最小厚さが０．０５ｍｍだからであり、０．３ｍｍ以下が好ましいのは、これより大きいと基板の反り変形が小さいから支持板の必要がないからである。   The thin film resin substrate in this case is a printed wiring board in which an insulating layer made of a film-like insulating resin such as polyimide and a wiring layer made of a conductive thin film such as copper are laminated, and does not have a so-called core, It is a flexible printed wiring board. The thickness is preferably 0.05 mm or more and 0.3 mm or less. The thickness of 0.05 mm or more is preferable because the minimum thickness that functions as a substrate is 0.05 mm. The thickness of 0.3 mm or less is preferable because the warpage deformation of the substrate is small when the thickness is larger than this. It is not necessary.

また、少なくとも一方の面上にはＢＧＡなどのフリップチップ接続により半導体チップが実装されて用いられるインターポーザー、子基板と呼ばれるプリント配線板の一種である。   Further, it is a kind of printed wiring board called an interposer or a sub board that is used by mounting a semiconductor chip by flip chip connection such as BGA on at least one surface.

薄膜樹脂基板はコアを有さないため薄く曲がりやすい。従って、層の数が少ない程取り扱いが困難である。そのため、半導体チップ実装部を除いた部分、好ましくは基板の周囲に枠状の支持体（以後スティフナと呼ぶ）を例えば耐熱性樹脂を用いて接着することもできる。スティフナは薄膜樹脂基板をが撓むのを防ぎ、半導体チップの実装を容易にする。例えば金属やガラスクロス含浸樹脂等を用いることができる。   A thin film resin substrate does not have a core and is easy to bend thinly. Therefore, the smaller the number of layers, the harder it is to handle. Therefore, a frame-like support (hereinafter referred to as a stiffener) can be bonded to a portion excluding the semiconductor chip mounting portion, preferably around the substrate, using, for example, a heat resistant resin. The stiffener prevents the thin film resin substrate from being bent and facilitates mounting of the semiconductor chip. For example, a metal or glass cloth impregnated resin can be used.

支持板は第二の接着部を介して薄膜樹脂基板と接着されている。前述のスティフナを貼付した場合、第二の接着部はスティフナと支持板を接着することになるが、この場合も薄膜樹脂基板と支持板とを固定する機能において変わりはないので、第二の樹脂を介して接着する概念に含むものとする。   The support plate is bonded to the thin film resin substrate through the second bonding portion. When the above-mentioned stiffener is pasted, the second adhesive part bonds the stiffener and the support plate, but in this case as well, there is no change in the function of fixing the thin film resin substrate and the support plate. It shall be included in the concept of bonding via

本発明で用いる支持板は第一の接着部を介して半導体チップと、第二の接着部を介して薄膜樹脂基板と接着されている。薄膜樹脂基板はコアを有する厚いプリント配線板に比べて線膨張係数が大きく（１６ｐｐｍ／℃以上）、半導体チップ（線膨張係数：３ｐｐｍ／℃程度）に対して線膨張係数が大きくなっている。   The support plate used in the present invention is bonded to the semiconductor chip via the first bonding portion and to the thin film resin substrate via the second bonding portion. The thin film resin substrate has a larger linear expansion coefficient (16 ppm / ° C. or higher) than that of a thick printed wiring board having a core, and has a larger linear expansion coefficient than that of a semiconductor chip (linear expansion coefficient: about 3 ppm / ° C.).

このため、半導体チップを薄膜樹脂基板にフリップチップ実装することにより形成された半導体装置では、半導体チップの素材であるシリコンと半導体チップが実装される薄膜樹脂基板の材質との熱膨張率の差に起因して、実装後に樹脂基板が変形したり、半導体チップのハンダ接続部が剥がれたりしてしまうといった問題が生じることがある。   For this reason, in a semiconductor device formed by flip-chip mounting a semiconductor chip on a thin film resin substrate, the difference in thermal expansion coefficient between the silicon that is the material of the semiconductor chip and the material of the thin film resin substrate on which the semiconductor chip is mounted As a result, there may be a problem that the resin substrate is deformed after mounting or the solder connection portion of the semiconductor chip is peeled off.

また、導電性（ハンダ）接続部を封止するために半導体チップと薄膜樹脂基板との空隙にアンダーフィル樹脂を注入し、硬化させるが、アンダーフィル樹脂の硬化に伴う収縮により薄膜樹脂基板がゆがんでしまうという問題がある。   In addition, in order to seal the conductive (solder) connection portion, an underfill resin is injected into the gap between the semiconductor chip and the thin film resin substrate and cured, but the thin film resin substrate is distorted due to shrinkage accompanying the curing of the underfill resin. There is a problem that it ends up.

本発明で用いる支持板はアンダーフィル樹脂の硬化前に半導体チップ及び薄膜樹脂基板を固定し、ゆがみを矯正することで、アンダーフィル樹脂硬化時の薄膜樹脂基板の変形を防止するとともに半導体装置をプリント配線板（親基板）に実装する際の信頼性を向上させることができるものである。   The support plate used in the present invention fixes the semiconductor chip and the thin film resin substrate before curing the underfill resin, and corrects the distortion, thereby preventing the deformation of the thin film resin substrate when the underfill resin is cured and printing the semiconductor device. The reliability at the time of mounting on a wiring board (parent substrate) can be improved.

支持板としては、以上述べたように薄膜樹脂基板の変形を防止できるだけの強度と、かつ第一の接着剤、第二の接着剤、アンダーフィル樹脂の硬化に必要な温度に対する耐性を有する材料であれば好ましく用いることができる。特に、第一の接着剤として熱伝導性に優れた例えば導電性ペースト等を用い、支持板として熱伝導性に優れた金属等の材料を選択することで、半導体チップや薄膜樹脂基板から発生する熱を効率よく排出できる放熱板としての役割も果たすことができる。   As described above, the support plate is made of a material having strength sufficient to prevent deformation of the thin film resin substrate and resistance to temperatures necessary for curing the first adhesive, the second adhesive, and the underfill resin. If there is, it can be preferably used. In particular, by using, for example, a conductive paste having excellent thermal conductivity as the first adhesive, and selecting a material such as metal having excellent thermal conductivity as the support plate, it is generated from a semiconductor chip or a thin film resin substrate. It can also serve as a heat sink that can efficiently discharge heat.

また、第二の接着剤としては接着強度と耐熱性があればよく、例えば既述のスティフナを固定するのに用いたシート状エポキシ系接着剤や、第一の接着剤と同じ導電性ペースト等を用いることができる。   The second adhesive only needs to have adhesive strength and heat resistance. For example, the sheet-like epoxy adhesive used to fix the stiffener described above, the same conductive paste as the first adhesive, etc. Can be used.

アンダーフィル樹脂としては例えばエポキシ樹脂である（株）ナミックス製Ｕ８４３７−２（商品名）を用いることができる。アンダーフィル樹脂はディスペンサーを用いて半導体チップの外形をなぞるように配置されると、毛細管現象によって半導体チップと薄膜樹脂基板との間隙を満たし、例えばハンダボール等からなる導電性接続部を包んで封止する。   As the underfill resin, for example, U8437-2 (trade name) manufactured by Namics Co., Ltd., which is an epoxy resin, can be used. When the underfill resin is disposed so as to trace the outer shape of the semiconductor chip using a dispenser, the gap between the semiconductor chip and the thin film resin substrate is filled by capillarity, and the conductive connection part made of, for example, a solder ball is wrapped and sealed. Stop.

支持板を半導体装置に固定後にアンダーフィル樹脂を充填・硬化させる必要から、本発明で用いる支持板の特徴として、アンダーフィル樹脂充填用貫通孔（以下、貫通孔と呼ぶ）が設けられている。貫通孔は薄膜樹脂基板を支持する機能を損なうことなく、アンダー
フィル樹脂を充填可能であればよく、例えば半導体チップの外形に沿ってI型やL型の形状をとることができる。 Since it is necessary to fill and harden the underfill resin after fixing the support plate to the semiconductor device, the support plate used in the present invention is provided with a through hole for filling the underfill resin (hereinafter referred to as a through hole). The through hole only needs to be able to be filled with an underfill resin without impairing the function of supporting the thin film resin substrate. For example, the through hole can have an I shape or an L shape along the outer shape of the semiconductor chip.

この様な構造をとることにより、半導体チップの実装と、第一の接着部及び第二の接着部の硬化後にアンダーフィル樹脂の硬化を行う半導体装置の製造方法をとることができる。   By adopting such a structure, it is possible to adopt a semiconductor device manufacturing method in which the semiconductor chip is mounted and the underfill resin is cured after the first adhesive portion and the second adhesive portion are cured.

特に、半導体チップの実装と、第一の接着部及び第二の接着部の硬化後にアンダーフィル樹脂充填用貫通孔からアンダーフィル樹脂を導電性接続部に充填し、硬化を行うことにより、ひずみなどが生じにくい状態で硬化させることが可能になる。   In particular, by mounting the semiconductor chip and filling the conductive connection portion with the underfill resin from the through-hole for filling the underfill resin after the first adhesive portion and the second adhesive portion are cured, the strain, etc. It is possible to cure in a state where it is difficult to cause.

この場合、第一の接着部及び第二の接着部は順次行うのも可能であるが、同一の接着剤を用いる場合は一括しておこなうのが簡便である。   In this case, the first adhesive portion and the second adhesive portion can be sequentially performed. However, when the same adhesive is used, it is easy to perform them collectively.

以下実施例により本発明を詳細に説明する。
＜実施例１＞
以下のようにして半導体装置を１０個作製した。 Hereinafter, the present invention will be described in detail by way of examples.
<Example 1>
Ten semiconductor devices were manufactured as follows.

半導体チップ１は、チップサイズが１５ｍｍ×１５ｍｍであり、厚さが５００μｍであり、Ａｌ（アルミニウム）のパッドが表面に２５０μｍピッチにて外周部に４列で配置され、このパッド各々に半田ボールが設けられている。半田ボールはパッドに電気的に接続されており、電気的導通部２を形成する。この半田ボールの材質は質量比において、Ｐｂ（鉛）が９５％，Ｓｎ（スズ）が５％である。   The semiconductor chip 1 has a chip size of 15 mm × 15 mm, a thickness of 500 μm, and Al (aluminum) pads are arranged in four rows on the outer periphery at a pitch of 250 μm on the surface, and solder balls are placed on each of these pads. Is provided. The solder balls are electrically connected to the pads and form the electrically conductive portion 2. The solder balls are composed of 95% Pb (lead) and 5% Sn (tin) in mass ratio.

薄膜樹脂基板４の表面には、上記パッドがフェイスダウンにて対向したとき、このパッドに対して位置的に対応してパッドが設けられている。薄膜樹脂基板４は、４０ｍｍ×４０ｍｍのサイズで、厚さ２００μｍである。   A pad is provided on the surface of the thin film resin substrate 4 in a position corresponding to the pad when the pad faces face down. The thin film resin substrate 4 has a size of 40 mm × 40 mm and a thickness of 200 μm.

薄膜樹脂基板４の半導体チップ１実装面の周囲には、５ｍｍ幅の金属製で枠状のスティフナ３（支持体）が設けられている。このスティフナ３は、加熱硬化タイプの接着フィルムをラミネートして形成した接着層を介して下方の面が薄膜樹脂基板４に貼着されている。この高さは後述の半導体チップ１固定後の高さと同じになる様に設計されている。   Around the semiconductor chip 1 mounting surface of the thin film resin substrate 4, a metal-made frame-shaped stiffener 3 (support) is provided. The lower surface of the stiffener 3 is attached to the thin film resin substrate 4 through an adhesive layer formed by laminating a heat-curing type adhesive film. This height is designed to be the same as the height after fixing the semiconductor chip 1 described later.

パッド上には、あらかじめ、例えば約２０μｍの厚さにて、錫−鉛共晶はんだにより予備はんだ層が形成されている。   On the pad, a preliminary solder layer is formed in advance with a tin-lead eutectic solder, for example, with a thickness of about 20 μm.

そして、半導体チップ１は、フェイスダウン状態により、薄膜樹脂基板４に対して、対応するパッド同士が対向するように位置合わせ（アライメント）され、電気的導通部２を介して配置される。   Then, the semiconductor chip 1 is aligned (aligned) so that corresponding pads face each other with respect to the thin film resin substrate 4 in a face-down state, and the semiconductor chip 1 is disposed via the electrically conductive portion 2.

このとき、電気的導通部２の半田ボール表面にはフラックスが添加されており、配置後に所定の温度により、リフローの処理を行うことにより、上記予備はんだが溶融され、半田ボールとパッドとが電気的に接続（はんだ接合）される。この結果、パッドとパッドとは電気的導通部２を介して電気的に接続され、図２の様な１次実装を終えた。   At this time, a flux is added to the surface of the solder ball of the electrically conductive portion 2, and the preliminary solder is melted by performing a reflow process at a predetermined temperature after the placement, and the solder ball and the pad are electrically connected. Connected (soldered). As a result, the pad and the pad were electrically connected through the electrical conduction part 2 and the primary mounting as shown in FIG. 2 was completed.

その後、スティフナ３と半導体チップ１に対して、Ｃｕを材質とし、半導体チップ１の隣り合う２辺に沿って半導体チップ１の外周から１ｍｍ外側に対応するようにチップサイズが１０ｍｍ×１０ｍｍの場合、幅３ｍｍ×長さ１４ｍｍのＬ字型の貫通孔Ａを設けた支持板６が、第一の接着部７ａ、第二の接着部７ｂにて接着剤より貼着された。このとき用
いる接着剤としては、第一の接着部７ａに対してはエイブルステック（株）製絶縁性ペースト エイブルボンド３００３（商品名）、第二の接着部７ｂ対しては例えばエイブルステック（株）製 エイブルボンド３１８５（商品名）等である。なお、この場合、導電ペーストでも構わない。 Thereafter, when the stiffener 3 and the semiconductor chip 1 are made of Cu and the chip size is 10 mm × 10 mm so as to correspond to 1 mm outside from the outer periphery of the semiconductor chip 1 along two adjacent sides of the semiconductor chip 1, A support plate 6 provided with an L-shaped through-hole A having a width of 3 mm and a length of 14 mm was adhered from an adhesive at the first adhesive portion 7a and the second adhesive portion 7b. As an adhesive used at this time, an insulating paste Able Bond 3003 (trade name) manufactured by Able Tech Co., Ltd. is used for the first adhesive portion 7a, and, for example, Able Tech Co., Ltd. is used for the second adhesive portion 7b. Manufactured by Able Bond 3185 (trade name). In this case, a conductive paste may be used.

上記第一の接着部７ａ、第二の接着部７ｂを、１２５℃の１時間の熱処理を行ない硬化させ、図３の様にした。   The first adhesive portion 7a and the second adhesive portion 7b were cured by performing a heat treatment at 125 ° C. for 1 hour, as shown in FIG.

そして、薄膜樹脂基板４と半導体チップ１との間隙（電気的導通部２となる半田ボールの径による所定の距離）に残留しているフラックスを洗浄により除去し、支持板６の貫通孔Ａからディスペンサーを差し込み、半導体チップの１辺に沿ってアンダーフィル樹脂を薄膜樹脂基板表面に出すことで、近くの電気的導通部２における毛細管現象を利用して上記間隙にアンダーフィル樹脂５を図４の様に充填した。   Then, the flux remaining in the gap between the thin film resin substrate 4 and the semiconductor chip 1 (a predetermined distance depending on the diameter of the solder ball serving as the electrical conduction portion 2) is removed by washing, and the through hole A of the support plate 6 is removed. A dispenser is inserted, and underfill resin is put out on the surface of the thin film resin substrate along one side of the semiconductor chip, so that the underfill resin 5 is inserted into the gap using the capillary phenomenon in the nearby electrically conductive portion 2 as shown in FIG. Filled in like manner.

このようにして図１の様な半導体装置を１０個作成し、上述した構造の半導体装置の図１２で示した様なうねりの最も高いところと低いところの差を測定したところ、３０〜４０μｍの範囲であった。測定にはレーザー変位計を用い、半導体チップ搭載面とは反対面を測定した。   In this way, ten semiconductor devices as shown in FIG. 1 were prepared, and the difference between the highest and lowest waviness as shown in FIG. 12 of the semiconductor device having the structure described above was measured. It was in range. A laser displacement meter was used for measurement, and the surface opposite to the semiconductor chip mounting surface was measured.

半導体チップ１が実装されている面を上面とすると、上記薄膜樹脂基板４の裏面には１ｍｍピッチのパッドが設けられている。このパッドに直径０．７ｍｍの半田ボール９を配設し、リフロー処理を行い、パッドと半田ボール９とが電気的に接続され、半田ボール９の搭載された薄膜樹脂基板４が形成されている。   Assuming that the surface on which the semiconductor chip 1 is mounted is the upper surface, pads having a pitch of 1 mm are provided on the back surface of the thin film resin substrate 4. Solder balls 9 having a diameter of 0.7 mm are disposed on the pads, reflow processing is performed, the pads and the solder balls 9 are electrically connected, and the thin film resin substrate 4 on which the solder balls 9 are mounted is formed. .

また、親基板の表面には、薄膜樹脂基板の具備するパッドがフェイスダウンにて対向したとき、このパッドに対応した位置にパッドが設けられている。   Further, on the surface of the parent substrate, when a pad provided on the thin film resin substrate faces face down, a pad is provided at a position corresponding to the pad.

このパッド上には、あらかじめ、はんだペーストが印刷されており、薄膜樹脂基板４を、親基板に対して、対応するパッド同士が対向するように位置合わせ（アライメント）し、半田ボール９を介して配置する。   Solder paste is printed on the pads in advance, and the thin film resin substrate 4 is aligned (aligned) with the parent substrate so that the corresponding pads face each other. Deploy.

このとき、はんだペースト中にはフラックスが添加されており、配置後に所定の温度により、リフローの処理を行うことにより、上記はんだペーストが溶融され、半田ボール９とパッドとが電気的に接続される。この結果、薄膜樹脂基板４のパッドと親基板のパッドとは半田ボール９を介して電気的に接続され、図５の様に２次実装できた。   At this time, flux is added to the solder paste, and the solder paste is melted by performing a reflow process at a predetermined temperature after the placement, and the solder balls 9 and the pads are electrically connected. . As a result, the pads of the thin film resin substrate 4 and the pads of the parent substrate were electrically connected via the solder balls 9, and secondary mounting was possible as shown in FIG.

上述した構造の半導体装置の２次実装における電気的接続の信頼性の評価を行った結果、半導体装置の親基板との実装不良は発生していなかった。   As a result of evaluating the reliability of the electrical connection in the secondary mounting of the semiconductor device having the above-described structure, no mounting failure with the parent substrate of the semiconductor device occurred.

また、二次実装後、−４５℃から１２５℃の範囲の温度サイクル試験（１０００回）に投入して、電気的接続の信頼性の評価を行った結果、ビアや電気的接続部の断線、破壊は発生しなかった。
＜実施例２＞
支持板６として半導体チップ１の１辺に沿って半導体チップ１の外周から１ｍｍ内側に対応するようにＩ字型の貫通孔Ｂを設けた支持板を用いたほかは実施例１と同様にして半導体装置を１０個作製し、実施例１と同様に評価を行ったところ、実施例１と同様良好な結果が得られた。
＜比較例＞
実施例１と同様のスティフナを具備する薄膜樹脂基板に半導体チップを実装した後、アンダーフィル樹脂を半導体チップに沿って配置、充填し硬化を行った。その後、実施例１
と同様に第一の接着部及び第二の接着部を介して、それぞれ半導体チップとスティフナとに実施例１と同様のＬ字型の貫通孔を有する支持板を接着、固定した。 In addition, after secondary mounting, it was put into a temperature cycle test (1000 times) in a range of −45 ° C. to 125 ° C., and the reliability of electrical connection was evaluated. As a result, disconnection of vias and electrical connection parts, No destruction occurred.
<Example 2>
The support plate 6 is the same as the first embodiment except that a support plate provided with an I-shaped through hole B so as to correspond to the inner side of the outer periphery of the semiconductor chip 1 along one side of the semiconductor chip 1 is used. Ten semiconductor devices were manufactured and evaluated in the same manner as in Example 1. As a result, good results were obtained as in Example 1.
<Comparative example>
After mounting a semiconductor chip on a thin film resin substrate having the same stiffener as in Example 1, an underfill resin was placed along the semiconductor chip, filled, and cured. Thereafter, Example 1
Similarly, a support plate having an L-shaped through hole similar to that in Example 1 was bonded and fixed to the semiconductor chip and the stiffener through the first bonding portion and the second bonding portion, respectively.

このようにして半導体装置を１０個作成し、上述した構造の半導体装置の親基板に向かう面の変形量を測定したところ、１００から１５０μｍの範囲であった。また実施例１と同様に親基板への二次実装を行ったところ、１０個中５個がうまく実装できなかった（ＮＧ）。   In this way, ten semiconductor devices were prepared, and the amount of deformation of the surface of the semiconductor device having the above-described structure toward the parent substrate was measured and found to be in the range of 100 to 150 μm. Further, when secondary mounting was performed on the parent substrate in the same manner as in Example 1, 5 out of 10 packages could not be mounted successfully (NG).

実装できた半導体装置を実施例１と同様の温度サイクル試験に投入したところ、５個中３個の半導体装置にビア（図示せず）での断線が発生していた。   When the mounted semiconductor device was put into a temperature cycle test similar to that of Example 1, disconnection by vias (not shown) occurred in three of the five semiconductor devices.

本発明に係る半導体装置の製造工程を説明する半導体装置完成後の断面図である。It is sectional drawing after the completion of the semiconductor device explaining the manufacturing process of the semiconductor device which concerns on this invention. 本発明に係る半導体装置の製造工程を説明する支持板接着前の状態の断面図である。It is sectional drawing of the state before support plate adhesion | attachment explaining the manufacturing process of the semiconductor device which concerns on this invention. 本発明に係る半導体装置の製造工程を説明する支持板接着後の状態の断面図である。It is sectional drawing of the state after support plate adhesion explaining the manufacturing process of the semiconductor device which concerns on this invention. 本発明に係る半導体装置の製造工程を説明するアンダーフィル樹脂充填中の状態の断面図である。It is sectional drawing of the state in underfill resin filling explaining the manufacturing process of the semiconductor device which concerns on this invention. 本発明に係る半導体装置の利用状態を説明する断面図である。It is sectional drawing explaining the utilization condition of the semiconductor device which concerns on this invention. 本発明に用いる支持板の一実施例を示す平面図である。It is a top view which shows one Example of the support plate used for this invention. 図６とは異なる本発明に用いる支持板の一実施例を示す平面図である。It is a top view which shows one Example of the support plate used for this invention different from FIG. 従来の半導体装置の製造工程を説明する半導体装置完成後の断面図である。It is sectional drawing after the completion of the semiconductor device explaining the manufacturing process of the conventional semiconductor device. 従来の半導体装置の製造工程を説明するアンダーフィル樹脂を設ける前の状態の断面図である。It is sectional drawing of the state before providing the underfill resin explaining the manufacturing process of the conventional semiconductor device. 従来の半導体装置の製造工程を説明する支持板接着前の状態の断面図である。It is sectional drawing of the state before support plate adhesion explaining the manufacturing process of the conventional semiconductor device. 図８とは異なる従来の半導体装置の一実施例を示す断面図である。FIG. 9 is a cross-sectional view showing an example of a conventional semiconductor device different from FIG. 8. 半導体装置のうねり測定の説明側面図である。It is a description side view of the waviness measurement of a semiconductor device.

符号の説明Explanation of symbols

１ 半導体チップ
２ 電気的導通部
３ スティフナ
４ 薄膜樹脂基板
５ アンダーフィル樹脂
６ 支持板
７ａ 第一の接着部
７ｂ 第二の接着部
８ 半導体装置
９ 半田ボール
Ａ、Ｂ 貫通孔
１０ ディスペンサー
１１ 変形量
１２ 親基板
１３ 半導体チップ搭載領域 DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Electrically conductive part 3 Stiffener 4 Thin film resin substrate 5 Underfill resin 6 Support plate 7a First adhesive part 7b Second adhesive part 8 Semiconductor device 9 Solder balls A and B Through-hole 10 Dispenser 11 Deformation amount 12 Parent substrate 13 Semiconductor chip mounting area

Claims (4)

薄膜樹脂基板と、
当該薄膜樹脂基板上に導電性接続部を介して実装されている半導体チップと、
当該半導体チップとは第一の接着部を介して、当該薄膜樹脂基板とは第二の接着部を介して接着されている支持板を具備し、
前記導電性接続部はアンダーフィル樹脂で封止されている半導体装置であって、
前記支持板がアンダーフィル樹脂充填用貫通孔を有することを特徴とする半導体装置。 A thin film resin substrate;
A semiconductor chip mounted on the thin film resin substrate via a conductive connection part;
The semiconductor chip includes a support plate that is bonded via a first bonding portion, and the thin film resin substrate is bonded via a second bonding portion;
The conductive connection part is a semiconductor device sealed with an underfill resin,
The semiconductor device, wherein the support plate has a through-hole for filling an underfill resin. 前記薄膜樹脂基板の厚さは０．０５ｍｍ以上０．３ｍｍ以下であることを特徴とする請求項１記載の半導体装置。   2. The semiconductor device according to claim 1, wherein the thickness of the thin film resin substrate is 0.05 mm or more and 0.3 mm or less. 薄膜樹脂基板と、
当該薄膜樹脂基板上に導電性接続部を介して実装されている半導体チップと、
当該半導体チップとは第一の接着部を介して、当該薄膜樹脂基板とは第二の接着部を介して接着されている支持板を具備し、
前記導電性接続部はアンダーフィル樹脂で封止されている半導体装置の製造方法であって、
前記半導体チップの実装と、第一の接着部及び第二の接着部の硬化後に前記アンダーフィル樹脂の硬化を行うことを特徴とする半導体装置の製造方法。 A thin film resin substrate;
A semiconductor chip mounted on the thin film resin substrate via a conductive connection part;
The semiconductor chip includes a support plate that is bonded via a first bonding portion, and the thin film resin substrate is bonded via a second bonding portion;
The conductive connection part is a manufacturing method of a semiconductor device sealed with an underfill resin,
A method of manufacturing a semiconductor device, comprising: curing the underfill resin after mounting the semiconductor chip and curing the first adhesive portion and the second adhesive portion. 前記支持板はアンダーフィル樹脂充填用貫通孔を具備し、
前記半導体チップの実装と、第一の接着部及び第二の接着部の硬化後に当該アンダーフィル樹脂充填用貫通孔からアンダーフィル樹脂を前記導電性接続部に充填し、硬化を行うことを特徴とする請求項３記載の半導体装置の製造方法。 The support plate includes a through-hole for filling an underfill resin,
After the mounting of the semiconductor chip and the first adhesive part and the second adhesive part are cured, the conductive film is filled with the underfill resin from the underfill resin filling through-hole and cured. A method of manufacturing a semiconductor device according to claim 3.
JP2005283956A 2005-09-29 2005-09-29 Semiconductor device and its manufacturing method Pending JP2007096028A (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06310562A (en) * 1993-04-23 1994-11-04 Toshiba Corp Resin-sealed semiconductor device
JPH11111895A (en) * 1997-10-01 1999-04-23 Toshiba Chem Corp Resin sealed type semiconductor device and its manufacture

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06310562A (en) * 1993-04-23 1994-11-04 Toshiba Corp Resin-sealed semiconductor device
JPH11111895A (en) * 1997-10-01 1999-04-23 Toshiba Chem Corp Resin sealed type semiconductor device and its manufacture

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