JP2001007257A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JP2001007257A JP2001007257A JP11177933A JP17793399A JP2001007257A JP 2001007257 A JP2001007257 A JP 2001007257A JP 11177933 A JP11177933 A JP 11177933A JP 17793399 A JP17793399 A JP 17793399A JP 2001007257 A JP2001007257 A JP 2001007257A
- Authority
- JP
- Japan
- Prior art keywords
- carrier substrate
- semiconductor element
- conductive
- conductive film
- ground electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、情報通信機器、事
務用電子機器、医療用電子機器等の産業用電子機器分野
および家庭用電子機器に使用される半導体装置、特にフ
リップチップ実装された半導体装置およびその製造方法
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device used in the field of industrial electronic equipment such as information and communication equipment, office electronic equipment, medical electronic equipment and home electronic equipment, and more particularly to a semiconductor device mounted on a flip chip. The present invention relates to an apparatus and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】近年、産業用電子機器、家庭用電子機器
のいずれを問わず小型化、薄型化、軽量化および高機能
化が進展してゆく中でこれら電子機器に用いられる半導
体装置を始めとする各種電子部品も小型化、薄型化が必
須の要件となっている。2. Description of the Related Art In recent years, semiconductor devices used for these electronic devices have been developed as miniaturization, thinning, weight reduction, and enhancement of functions have progressed regardless of whether they are industrial electronic devices or home electronic devices. It is also an essential requirement that various electronic components be miniaturized and thinned.
【０００３】特に半導体装置の分野においてはその半導
体素子のパッケージ技術に格段の進歩が見られる。従来
多ピン半導体パッケージの主流であったプラスチックＱ
ＦＰ（クワッドフラットパッケージ）も電子機器の多機
能化、高性能化に応じてＬＳＩの大規模化が進行するに
伴って大型化し、上記電子機器の小型化、薄型化の要望
に対応できなくなってきた。またプラスチックＱＦＰの
側面から引き出された入出力リード線の回路基板への接
続信頼性や長いリードピンの固有抵抗に起因する伝送信
号の遅れなども課題となっていた。In particular, in the field of semiconductor devices, a remarkable progress has been made in the packaging technology of semiconductor elements. Plastic Q, which has been the mainstream of conventional multi-pin semiconductor packages
FPs (quad flat packages) have also become larger as the scale of LSIs has increased in accordance with the increasing functionality and performance of electronic devices, and it has become impossible to respond to the demand for smaller and thinner electronic devices. Was. Also, there have been problems in connection reliability of an input / output lead wire drawn out from a side surface of the plastic QFP to a circuit board, a delay of a transmission signal due to a specific resistance of a long lead pin, and the like.
【０００４】このようなプラスチックＱＦＰの抱える多
くの課題を解決するために、ＱＦＰに代わって半導体パ
ッケージの裏面に半球状の接続端子を２次元のアレイ状
に配置したＢＧＡ（ball grid array）や同じくパッケ
ージの裏面に多数の平らな電極パッド群をアレイ状に配
置してソケットに挿入して実装するＬＧＡ（land grid
array）と呼ばれるいずれもＱＦＰのようなリードピン
を持たない、いわゆるＣＳＰ（chip size package）と
呼ばれる半導体装置が用いられるようになってきた。In order to solve many problems of such a plastic QFP, a ball grid array (BGA) in which hemispherical connection terminals are arranged in a two-dimensional array on the back surface of a semiconductor package instead of the QFP or the like. An LGA (land grid) in which a number of flat electrode pads are arranged in an array on the back of the package and inserted into a socket for mounting
A semiconductor device called a so-called CSP (chip size package), which does not have a lead pin like a QFP, has been used.
【０００５】これらのＣＳＰ半導体はいずれも半導体素
子がフェースダウンボンディングによりキャリア基板に
接続されているものである。[0005] All of these CSP semiconductors have a semiconductor element connected to a carrier substrate by face-down bonding.
【０００６】以下、従来の半導体装置について図面を参
照しながら説明する。図７は従来の半導体装置の断面
図、図８はその平面図であり、図７は図８におけるＣ−
Ｃ’線部分の断面を示している。Hereinafter, a conventional semiconductor device will be described with reference to the drawings. FIG. 7 is a cross-sectional view of a conventional semiconductor device, FIG. 8 is a plan view thereof, and FIG.
The cross section taken along the line C ′ is shown.
【０００７】表面のパッド電極（図示せず）に、Ａｕバ
ンプ１よりなる突起電極が形成されている半導体素子２
が、その回路形成面側を下にしてセラミックを絶縁基体
とした多層回路基板であるキャリア基板３に接合されて
いる。キャリア基板３の上面には半導体素子２との電気
的接続のための複数のランド電極４が形成されており、
このランド電極４と半導体素子２上に形成されたＡｕバ
ンプ１とは、あらかじめＡｕバンプ１上に塗布された導
電性接着剤５により接合されている。また半導体素子２
とキャリア基板３との接続部および半導体素子２の周辺
部には封止樹脂６が充填されている。[0007] A semiconductor element 2 in which a protruding electrode made of an Au bump 1 is formed on a pad electrode (not shown) on the surface.
Is bonded to a carrier substrate 3 which is a multilayer circuit substrate using ceramic as an insulating base with its circuit forming surface side down. A plurality of land electrodes 4 for electrical connection with the semiconductor element 2 are formed on the upper surface of the carrier substrate 3.
The land electrode 4 and the Au bump 1 formed on the semiconductor element 2 are joined by a conductive adhesive 5 applied on the Au bump 1 in advance. Semiconductor element 2
A sealing resin 6 is filled in a connection portion between the semiconductor element 2 and the peripheral portion of the semiconductor element 2.
【０００８】さらに、半導体素子２の裏面には導電性被
膜７が形成され、この導電性被膜７とキャリア基板３上
の接地電極８とが導電層９により、電気的に接続されて
いる。Further, a conductive film 7 is formed on the back surface of the semiconductor element 2, and the conductive film 7 and a ground electrode 8 on the carrier substrate 3 are electrically connected by a conductive layer 9.
【０００９】[0009]
【発明が解決しようとする課題】しかしながら、上記従
来の半導体装置では、半導体素子２の裏面上に形成され
ている導電性被膜７とキャリア基板３上の接地電極８と
を電気的に接続している導電層９が空気中に露出してい
るため、急激な温度変化や導電層９のガラス転移点以上
の高温度環境下において導電層９の接着強度の低下やク
ラック等が発生し易く、半導体素子２の裏面上の導電性
被膜７とキャリア基板３上の接地電極との電気的接続を
安定して得ることができない。However, in the above conventional semiconductor device, the conductive film 7 formed on the back surface of the semiconductor element 2 and the ground electrode 8 on the carrier substrate 3 are electrically connected. Since the conductive layer 9 is exposed to the air, the adhesive strength of the conductive layer 9 is likely to be reduced or cracks are likely to occur in a rapid temperature change or in a high temperature environment equal to or higher than the glass transition point of the conductive layer 9. The electrical connection between the conductive coating 7 on the back surface of the element 2 and the ground electrode on the carrier substrate 3 cannot be stably obtained.
【００１０】また図８に示すように、半導体素子２とキ
ャリア基板３との接続部に充填された封止樹脂６は半導
体素子２の周辺に幅Ｄを有する均一な範囲で広がり、し
かも図７の断面に示すように半導体素子２に対して急峻
な角度で形成されている。したがって導電層９を塗布し
たとき、半導体素子２の角部Ｅにおける導電層９の厚み
は薄く形成され、急激な温度変化や機械的衝撃を受けた
とき角部Ｅにおいて導電層９にクラックが発生しやすい
構造となっている。[0010] As shown in FIG. 8, the sealing resin 6 filled in the connection portion between the semiconductor element 2 and the carrier substrate 3 spreads around the semiconductor element 2 in a uniform range having a width D. Are formed at a steep angle with respect to the semiconductor element 2. Therefore, when the conductive layer 9 is applied, the thickness of the conductive layer 9 at the corner E of the semiconductor element 2 is formed to be thin, and cracks occur in the conductive layer 9 at the corner E when subjected to a sudden temperature change or mechanical shock. It has a structure that is easy to do.
【００１１】本発明は、上記従来の課題を解決するもの
であり、半導体素子の裏面に設けられた導電性被膜とキ
ャリア基板３上の接地電極との電気的接続を容易に行
い、優れた接続信頼性を得ることができる半導体装置を
提供することを目的とする。An object of the present invention is to solve the above-mentioned conventional problems, and to easily perform an electrical connection between a conductive film provided on the back surface of a semiconductor element and a ground electrode on a carrier substrate 3 to obtain an excellent connection. It is an object to provide a semiconductor device which can obtain reliability.
【００１２】[0012]
【課題を解決するための手段】本発明は上記目的を達成
するために、裏面に導電性被膜を有する半導体素子を接
地電極が設けられているキャリア基板にフリップチップ
接続したのち、キャリア基板と半導体素子との接続部お
よび半導体素子の周辺部に封止樹脂を充填することによ
り、導電性被膜の表面と同一面、またはその表面の一辺
を覆うように導電性被膜の上面の一辺からキャリア基板
上の接地電極の付近まで段差のない連続した緩やかな勾
配を有するフィレットを形成することによって導電性被
膜の上面とフィレットの上面を段差や角部の無い平滑な
表面とし、導電性被膜の表面の一部からフィレットの上
面およびキャリア基板上の接地電極の上面まで導電層を
塗布したのち、さらに導電性被膜と導電層の全面に絶縁
樹脂よりなる保護層を被覆して半導体装置を得るもので
ある。According to the present invention, in order to achieve the above object, a semiconductor device having a conductive film on the back surface is flip-chip connected to a carrier substrate provided with a ground electrode, and then the carrier substrate is connected to the semiconductor substrate. By filling a sealing resin in a connection portion with the element and a peripheral portion of the semiconductor element, the carrier substrate is flush with the surface of the conductive film or from one side of the upper surface of the conductive film so as to cover one side of the surface. The upper surface of the conductive coating and the upper surface of the fillet are made smooth without any steps or corners by forming a fillet having a continuous and gentle gradient without any steps up to the vicinity of the ground electrode. After applying a conductive layer from the part to the upper surface of the fillet and the upper surface of the ground electrode on the carrier substrate, further protect the conductive film and the entire conductive layer with insulating resin Covering the one in which obtaining a semiconductor device.
【００１３】[0013]
【発明の実施形態】本発明の請求項１に記載の発明は、
表面の一部に接地電極が設けられているキャリア基板
と、そのキャリア基板にフリップチップ接続された半導
体素子と、キャリア基板と半導体素子との接続部および
半導体素子の周辺部に充填された封止樹脂と、半導体素
子の裏面上に形成された導電性被膜と、その導電性被膜
とキャリア基板上の接地電極とを電気的に接続する導電
層と、その導電層を被覆する保護層とを有する半導体装
置であり、急激な温度変化、または導電層のガラス転移
点以上の高温度環境下における導電層の接着強度の低下
やクラックの発生を防ぎ、半導体素子の裏面に設けられ
た導電性被膜とキャリア基板上の接地電極との電気的接
続の信頼性を向上することができる。DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention described in claim 1 of the present invention is as follows.
A carrier substrate having a ground electrode provided on a part of its surface; a semiconductor element flip-chip connected to the carrier substrate; a sealing portion filled in a connection portion between the carrier substrate and the semiconductor element and a peripheral portion of the semiconductor element A resin, a conductive film formed on the back surface of the semiconductor element, a conductive layer electrically connecting the conductive film and a ground electrode on the carrier substrate, and a protective layer covering the conductive layer. A semiconductor device, which prevents a rapid temperature change, or a decrease in the adhesive strength of the conductive layer or the occurrence of cracks in a high temperature environment above the glass transition point of the conductive layer, and a conductive film provided on the back surface of the semiconductor element. The reliability of electrical connection with the ground electrode on the carrier substrate can be improved.
【００１４】本発明の請求項２に記載の発明は、表面に
複数のランド電極と接地電極とを備え、裏面に格子状に
配列された外部電極端子が設けられているキャリア基板
と、そのキャリア基板表面の複数のランド電極に対して
導電性接着剤により接合された複数の突起電極を備える
半導体素子と、キャリア基板と半導体素子との接続部お
よび半導体素子の周辺部に充填された封止樹脂と、半導
体素子裏面上に形成された導電性被膜と、その導電性被
膜とキャリア基板上の接地電極とを電気的に接続する導
電層と、その導電層を被覆する保護層とを有する半導体
装置であり、請求項１に記載の場合と同様の効果を得る
ことができる。According to a second aspect of the present invention, there is provided a carrier substrate provided with a plurality of land electrodes and a ground electrode on a front surface, and provided with external electrode terminals arranged in a lattice on a rear surface, A semiconductor element having a plurality of protruding electrodes joined to a plurality of land electrodes on a substrate surface by a conductive adhesive, and a sealing resin filled in a connection portion between the carrier substrate and the semiconductor element and a peripheral portion of the semiconductor element And a conductive film formed on the back surface of the semiconductor element, a conductive layer electrically connecting the conductive film to the ground electrode on the carrier substrate, and a protective layer covering the conductive layer. Thus, the same effect as in the case of the first aspect can be obtained.
【００１５】本発明の請求項３に記載の発明は、請求項
１または２に記載の半導体装置に関し、半導体素子の周
辺部に充填された封止樹脂の表面が、半導体素子の裏面
上に設けられている導電性被膜の表面と同一面を形成し
ているか、または導電性被膜の表面の一部を覆うように
形成されているものであり、導電性被膜と封止樹脂の接
続部に角部のない緩やかな勾配を形成することにより、
導電層の塗布厚さを均一なものとすることができるので
急激な温度変化や機械的衝撃に対してクラック等の発生
しにくい導電層を得ることができ、優れた接続信頼性を
得ることが可能となる。According to a third aspect of the present invention, there is provided the semiconductor device according to the first or second aspect, wherein a surface of the sealing resin filled in a peripheral portion of the semiconductor element is provided on a back surface of the semiconductor element. Formed on the same surface as the surface of the conductive film, or formed so as to cover a part of the surface of the conductive film. By forming a gentle gradient without parts,
Since the coating thickness of the conductive layer can be made uniform, it is possible to obtain a conductive layer in which cracks and the like are unlikely to occur due to a rapid temperature change or mechanical shock, and to obtain excellent connection reliability. It becomes possible.
【００１６】本発明の請求項４に記載の発明は、裏面に
導電性被膜を有する半導体素子を接地電極が設けられて
いるキャリア基板にフリップチップ接続する工程と、キ
ャリア基板と半導体素子との接続部および半導体素子の
周辺部に封止樹脂を充填して導電性被膜の上面の一辺か
らキャリア基板上の接地電極の付近まで段差のない連続
した緩やかな勾配を有するフィレットを形成する工程
と、導電性被膜の上面からフィレットの上面およびキャ
リア基板上の接地電極の上面まで導電性材料を塗布して
導電層を形成する工程と、導電性被膜と導電層の全面を
絶縁樹脂よりなる保護層によって被覆する工程とを有す
る半導体装置の製造方法であり、電気的接続信頼性に優
れた半導体装置を形成することができる。According to a fourth aspect of the present invention, there is provided a method of flip-chip connecting a semiconductor element having a conductive film on a back surface to a carrier substrate provided with a ground electrode, and connecting the carrier element and the semiconductor element. Forming a fillet having a continuous gradual gradient with no steps from one side of the upper surface of the conductive film to the vicinity of the ground electrode on the carrier substrate by filling a sealing resin into the peripheral portion of the conductive element and the semiconductor element; Forming a conductive layer by applying a conductive material from the upper surface of the conductive film to the upper surface of the fillet and the upper surface of the ground electrode on the carrier substrate; and covering the entire surface of the conductive film and the conductive layer with a protective layer made of an insulating resin. A semiconductor device having excellent electrical connection reliability.
【００１７】本発明の請求項５に記載の発明は、裏面に
導電性被膜を有する半導体素子の複数の電極上に突起電
極を形成してその突起電極上に導電性接着剤を塗布する
工程と、突起電極と裏面に一定の間隔で格子状に形成さ
れた外部電極端子を有するキャリア基板の表面の複数の
ランド電極とを導電性接着剤により接合した後、その導
電性接着剤を熱硬化させる工程と、半導体素子とキャリ
ア基板との接続部および半導体素子の周辺部に封止樹脂
を充填して導電性被膜の上面の一辺からキャリア基板上
の接地電極の付近まで段差のない連続した緩やかな勾配
を有するフィレットを形成する工程と、導電性被膜の上
面からフィレットの上面およびキャリア基板上の接地電
極の上面まで導電性材料を塗布して導電層を形成する工
程と、導電性被膜と導電層の全面を絶縁樹脂よりなる保
護層によって被覆する工程とを有する半導体装置の製造
方法であり、請求項４の場合と同様な効果を得ることが
できる。According to a fifth aspect of the present invention, there is provided a method for forming a projecting electrode on a plurality of electrodes of a semiconductor device having a conductive film on a back surface, and applying a conductive adhesive on the projecting electrode. After bonding the protruding electrodes and a plurality of land electrodes on the surface of the carrier substrate having external electrode terminals formed in a grid pattern at regular intervals on the back surface with a conductive adhesive, the conductive adhesive is thermally cured. Step: filling a connection portion between the semiconductor element and the carrier substrate and a peripheral portion of the semiconductor element with a sealing resin to form a continuous and gentle step-free process from one side of the upper surface of the conductive film to the vicinity of the ground electrode on the carrier substrate. Forming a fillet having a gradient, applying a conductive material from the upper surface of the conductive film to the upper surface of the fillet and the upper surface of the ground electrode on the carrier substrate to form a conductive layer; The entire surface of the conductive layer with a protective layer made of an insulating resin is a method of manufacturing a semiconductor device having a step of coating, it is possible to obtain the same effect as the fourth aspect.
【００１８】以下、本発明の実施の形態について図面を
参照しながら図７、図８と同一部分には同一番号を付し
て説明する。Hereinafter, embodiments of the present invention will be described with reference to the drawings, in which the same parts as those in FIGS.
【００１９】図１は本発明の第１の実施の形態における
半導体装置の断面図、図２は同平面図であり、図１は図
２におけるＡ−Ａ’線部分の断面を示している。FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention, FIG. 2 is a plan view of the same, and FIG. 1 shows a section taken along line AA 'in FIG.
【００２０】図１に示すように、接地電極８を有するキ
ャリア基板３の上面には半導体素子２がフェイスダウン
ボンディングで半田ボール１１を介して接続されてい
る。半導体素子２の裏面上には半導体素子２をキャリア
基板３と同電位にするための導電性被膜７が形成されて
いる。そしてキャリア基板３と半導体素子２との接続部
と半導体素子２の周辺にはエポキシ樹脂等よりなる絶縁
性の封止樹脂１２が充填される。As shown in FIG. 1, the semiconductor element 2 is connected to the upper surface of the carrier substrate 3 having the ground electrode 8 through solder balls 11 by face-down bonding. On the back surface of the semiconductor element 2, a conductive film 7 for making the semiconductor element 2 the same potential as the carrier substrate 3 is formed. The connection between the carrier substrate 3 and the semiconductor element 2 and the periphery of the semiconductor element 2 are filled with an insulating sealing resin 12 made of epoxy resin or the like.
【００２１】このとき本発明の特徴とする封止樹脂１２
は図１に示すように、半導体素子２の裏面上に設けられ
ている導電性被膜７の上面と同一面を形成するように充
填されており、またキャリア基板３上の接地電極８側に
おいて半導体素子２と接地電極８との間で緩やかな勾配
を備えるように接地電極８の反対側の半導体素子側面よ
りも広い幅で形成されている。すなわち図１，図２に示
すように、接地電極８側のフィレットの幅Ｌ1は反対側
のフィレットの幅ｌ1よりも広く形成されている。した
がって導電性被膜７の上面と接地電極８側に形成されて
いる封止樹脂１２よりなるフィレットの上面の形状は、
その断面において連続した緩やかな勾配を備えており、
図７に示す従来のような角部Ｅは存在していない。At this time, the sealing resin 12 which is a feature of the present invention
1 is filled so as to form the same surface as the upper surface of the conductive film 7 provided on the back surface of the semiconductor element 2, and the semiconductor is formed on the side of the ground electrode 8 on the carrier substrate 3. In order to provide a gentle gradient between the element 2 and the ground electrode 8, the width is wider than the side of the semiconductor element opposite to the ground electrode 8. That is, FIG. 1, as shown in FIG. 2, the width L 1 of the fillet of the ground electrode 8 side is formed wider than the width l 1 of the opposite side of the fillet. Therefore, the shape of the upper surface of the fillet made of the sealing resin 12 formed on the upper surface of the conductive film 7 and the ground electrode 8 is
It has a continuous gentle gradient in its cross section,
There is no corner E as in the prior art shown in FIG.
【００２２】つぎに半導体素子２とキャリア基板３とを
同電位とするための導電層１３が導電性被膜７の上面か
ら封止樹脂１２の上面にかけて形成されることにより接
地電極８に接続され、さらにその導電層１３と導電性被
膜７を外気による腐食より保護するための絶縁性樹脂よ
りなる保護層１０が塗布されて本発明による半導体装置
が完成する。Next, a conductive layer 13 for making the semiconductor element 2 and the carrier substrate 3 have the same potential is formed from the upper surface of the conductive film 7 to the upper surface of the sealing resin 12 so as to be connected to the ground electrode 8. Further, a protective layer 10 made of an insulating resin for protecting the conductive layer 13 and the conductive film 7 from corrosion by the outside air is applied to complete the semiconductor device according to the present invention.
【００２３】図１より明らかなように導電層１３は、導
電性被膜７の上面から封止樹脂１２のフィレットの緩や
かな勾配を有する面上に段差なく形成されているために
塗布厚さも均一となり、かつ応力集中を招きクラック等
の破壊発生点となり得る角部が存在しないので急激な温
度変化や導電層１３のガラス転移点以上の高温度環境下
における大きな熱的衝撃、または機械的衝撃に対して十
分な衝撃緩和力を備えている。また導電層１３はその露
出する全表面を絶縁性の保護層１０によって被覆されて
いるため、使用環境下における空気暴露や有害ガスに対
しても腐食することなく、優れた電気的接続信頼性を備
えている。As is apparent from FIG. 1, the conductive layer 13 is formed with no steps on the surface of the fillet of the sealing resin 12 having a gentle gradient from the upper surface of the conductive film 7, so that the coating thickness becomes uniform. In addition, since there is no corner portion which can cause stress concentration and become a breaking point such as a crack, a large temperature shock or a large thermal shock in a high temperature environment equal to or higher than the glass transition point of the conductive layer 13 or a mechanical shock. And has sufficient shock absorbing power. Further, since the entire surface of the conductive layer 13 that is exposed is covered with the insulating protective layer 10, the conductive layer 13 does not corrode even when exposed to air or harmful gas under the use environment and has excellent electrical connection reliability. Have.
【００２４】なお、本実施の形態において図１には封止
樹脂１２よりなるフィレットを導電性被膜７の表面に段
差なく連なる同一面に形成した例について説明したが、
フィレットを導電性被膜７の表面の一辺に重畳して設け
ることも可能であり、同一の効果を得ることができる。In this embodiment, an example in which a fillet made of the sealing resin 12 is formed on the same surface which is continuous with the surface of the conductive film 7 without any step has been described with reference to FIG. 1.
A fillet can be provided so as to overlap one side of the surface of the conductive film 7, and the same effect can be obtained.
【００２５】次に、本発明の第２の実施の形態について
図３、図４を用いて説明する。図３は本実施の形態にお
ける半導体装置の断面を、図４は同じく半導体装置の平
面をそれぞれ示すものであり、図３は図４におけるＢ−
Ｂ’線部分の断面を示している。Next, a second embodiment of the present invention will be described with reference to FIGS. 3 shows a cross section of the semiconductor device according to the present embodiment, FIG. 4 shows a plan view of the semiconductor device, and FIG.
The cross section taken along the line B 'is shown.
【００２６】まず図３に示すように、表面のパッド電極
（図示せず）にＡｕバンプ等の突起電極１を備え、裏面
に導電性被膜７が形成されている半導体素子２が、その
表面側を下にしてセラミック絶縁体より構成された多層
回路基板であるキャリア基板３に接合されている。キャ
リア基板３の上面には半導体素子２表面のパッド電極と
接続するための複数のランド電極４が形成されており、
このランド電極４と半導体素子２上に形成されたＡｕバ
ンプ１とが導電性接着剤５によって接合されている。First, as shown in FIG. 3, a semiconductor element 2 provided with a bump electrode 1 such as an Au bump on a pad electrode (not shown) on the front surface and a conductive film 7 formed on the back surface, Is bonded to a carrier substrate 3 which is a multilayer circuit board made of a ceramic insulator with the lower side of the substrate. A plurality of land electrodes 4 for connecting to pad electrodes on the surface of the semiconductor element 2 are formed on the upper surface of the carrier substrate 3.
The land electrode 4 and the Au bump 1 formed on the semiconductor element 2 are joined by a conductive adhesive 5.
【００２７】接合された半導体素子２とキャリア基板３
との接続部および半導体素子２の周辺部にはエポキシ樹
脂等よりなる封止樹脂１２が充填される。The bonded semiconductor element 2 and carrier substrate 3
And the periphery of the semiconductor element 2 are filled with a sealing resin 12 made of epoxy resin or the like.
【００２８】本実施の形態における封止樹脂１２はすで
に説明した第１の実施の形態の場合と同様であり、半導
体素子２の裏面上に設けられている導電性被膜７の上面
と同一面を形成するように充填されていてキャリア基板
３上の接地電極８側において半導体素子２と接地電極８
との間で緩やかな勾配を備えるように形成されている。The sealing resin 12 in the present embodiment is the same as that in the first embodiment already described, and the same surface as the upper surface of the conductive film 7 provided on the back surface of the semiconductor element 2 is used. The semiconductor element 2 and the ground electrode 8 are filled on the carrier substrate 3 on the side of the ground electrode 8.
Are formed so as to have a gentle gradient between them.
【００２９】したがって図３、図４に見られるように、
接地電極８側に形成されたフィレットの幅Ｌ2は反対側
のフィレットの幅ｌ2よりも大きく形成されており、導
電性被膜７の上面と封止樹脂１２よりなるフィレットの
上面の形状は、その断面において段差のない連続した緩
やかな勾配を備えていて従来のような破壊開始点となる
角部が生じることはない。Therefore, as can be seen in FIGS.
Width L 2 of a fillet formed on the ground electrode 8 side is formed larger than the width l 2 of the opposite side of the fillet, the shape of the upper surface of the fillet made of top and the sealing resin 12 of the conductive coating 7, The cross section has a continuous gentle gradient with no steps, and there is no occurrence of a corner serving as a breaking start point as in the related art.
【００３０】つぎに半導体素子２とキャリア基板３とを
同電位とするための導電層１３が導電性被膜７の上面か
ら連続する同一面を有するフィレットの上面にかけて形
成されることにより接地電極８に接続される。つぎに導
電層１３と導電性被膜７を外気による腐食より保護する
ための絶縁性樹脂よりなる保護層１０が塗布されて本実
施の形態における半導体装置を得ることができる。Next, a conductive layer 13 for making the semiconductor element 2 and the carrier substrate 3 have the same potential is formed from the upper surface of the conductive film 7 to the upper surface of a fillet having the same continuous surface, so that the ground electrode 8 is formed. Connected. Next, a protective layer 10 made of an insulating resin for protecting the conductive layer 13 and the conductive film 7 from corrosion by the outside air is applied, and the semiconductor device according to the present embodiment can be obtained.
【００３１】図３より明らかなように導電層１３は、キ
ャリア基板３上の接地電極８側において、導電性被膜７
の上面から連続して同一面を備えている封止樹脂１２の
フィレットの緩やかな勾配を有する面上に段差なく形成
されているために塗布厚さも均一となり、かつ応力集中
を招き破壊発生点となり得る角部が存在しないので急激
な温度変化や導電層１３のガラス転移点以上の高温度環
境下における大きな熱的衝撃、または機械的衝撃に対し
て十分な衝撃緩和力を備えている。また導電層１３はそ
の露出する全表面を絶縁性の保護層１０によって被覆さ
れているため、使用環境下における空気暴露や有害ガス
に対しても腐食することなく、優れた電気的接続信頼性
を備えることができる。As is apparent from FIG. 3, the conductive layer 13 is formed on the conductive film 7 on the side of the ground electrode 8 on the carrier substrate 3.
Is formed without any steps on the surface of the fillet of the sealing resin 12 having a gentle slope having the same surface continuously from the upper surface of the sealing resin 12, so that the coating thickness becomes uniform, and stress concentration is caused to cause a breakage point. Since there are no corners to be obtained, a sufficient impact relaxation force is provided against a sudden temperature change, a large thermal shock in a high temperature environment equal to or higher than the glass transition point of the conductive layer 13, or a mechanical shock. Further, since the entire surface of the conductive layer 13 that is exposed is covered with the insulating protective layer 10, the conductive layer 13 does not corrode even when exposed to air or harmful gas under the use environment and has excellent electrical connection reliability. Can be prepared.
【００３２】つぎに本発明における半導体装置の製造方
法について第２の実施の形態の半導体装置の場合を例と
して説明する。図５（ａ）〜（ｄ）は本製造方法におけ
る前半工程、図６（ａ）、（ｂ）は同じく後半工程を示
すものである。Next, a method of manufacturing a semiconductor device according to the present invention will be described by taking the case of the semiconductor device of the second embodiment as an example. FIGS. 5A to 5D show the first half of the manufacturing method, and FIGS. 6A and 6B show the second half of the manufacturing method.
【００３３】まず、図５（ａ）に示すように、ボールボ
ンディング法を用いて半導体素子２のパッド電極１６上
に突起電極として２段の突起形状を有するＡｕバンプ１
を下記のように形成する。すなわちＡｕワイヤーの先端
に形成したボールを半導体素子２上に形成されたアルミ
ニウムよりなるパッド電極１６に熱圧接して２段突起の
下段部を形成し、さらにキャピラリー１４を移動させる
ことにより形成したＡｕワイヤーループにより２段突起
の上段部を形成する。つぎに２段突起形状のＡｕバンプ
１の高さを均一なものとするため頂部を加圧して高さの
均一化および頂部の平坦化を行う。First, as shown in FIG. 5A, an Au bump 1 having a two-stage projection shape as a projection electrode is formed on a pad electrode 16 of a semiconductor element 2 by using a ball bonding method.
Is formed as described below. That is, the ball formed at the tip of the Au wire is thermally pressed to the pad electrode 16 made of aluminum formed on the semiconductor element 2 to form a lower step portion of the two-step projection, and further, the Au formed by moving the capillary 14. The upper part of the two-step projection is formed by a wire loop. Next, in order to make the height of the Au bump 1 having the two-step projection uniform, the top is pressed to make the height uniform and the top flat.
【００３４】つぎに回転する円盤上にドクターブレード
法により適当な厚さで塗布されたＡｇ−Ｐｄを導電物質
とし、バインダーとしてエポキシレジンを用いた導電性
接着剤５にＡｕバンプ１を設けた半導体素子２を押し当
てた後に引き上げる方法によって図５（ｂ）に示すよう
に、Ａｕバンプ１の上面に導電性接着剤５を転写する。Next, a semiconductor in which Ag-Pd applied to a rotating disk by a doctor blade method with an appropriate thickness is used as a conductive material, and an Au bump 1 is provided on a conductive adhesive 5 using epoxy resin as a binder. As shown in FIG. 5B, the conductive adhesive 5 is transferred onto the upper surface of the Au bump 1 by a method in which the element 2 is pressed and then pulled up.
【００３５】つぎに図５（ｃ）に示すように、半導体素
子２をＡｕバンプ１および導電性接着剤５が設けられて
いる表面を下にして裏面に外部電極端子１５が格子状に
形成されているキャリア基板３の上に載置し、フリップ
チップ方式によりキャリア基板３上のランド電極４とＡ
ｕバンプ１とを位置合わせして接合した後、一定の温度
で導電性接着剤５を熱硬化させる。Next, as shown in FIG. 5C, the external electrode terminals 15 are formed in a grid pattern on the back surface of the semiconductor element 2 with the Au bumps 1 and the conductive adhesive 5 provided on the lower side. And the land electrodes 4 on the carrier substrate 3 by flip-chip method.
After aligning and bonding with the u bump 1, the conductive adhesive 5 is thermally cured at a certain temperature.
【００３６】つぎに図５（ｄ）に示すように、エポキシ
系の封止樹脂１２をキャリア基板３上の接地電極８側か
ら半導体素子２とキャリア基板３との接続部に注入する
と同時に半導体素子２の周辺部に盛り上げ、半導体素子
２上の導電性被膜７の表面と同一面まで、または導電性
被膜７の表面の一部に僅かに重なるまで充填することに
より、緩やかな勾配を有するフィレットがＬ2の幅で接
地電極８側に形成される。また接地電極８側から封止樹
脂１２を注入することにより、接地電極８とは反対側の
キャリア基板３上には狭い幅ｌ2を有するフィレットが
形成される。Next, as shown in FIG. 5D, an epoxy-based sealing resin 12 is injected from the side of the ground electrode 8 on the carrier substrate 3 into the connection between the semiconductor device 2 and the carrier substrate 3 and at the same time, 2 and filled up to the same plane as the surface of the conductive coating 7 on the semiconductor element 2 or until it slightly overlaps a part of the surface of the conductive coating 7, thereby forming a fillet having a gentle gradient. a width of L 2 is formed on the ground electrode 8 side. Also, by injecting the sealing resin 12 from the ground electrode 8 side, a fillet having a narrow width l 2 is formed on the carrier substrate 3 on the side opposite to the ground electrode 8.
【００３７】ここで封止樹脂１２としてはエポキシ系樹
脂に高熱伝導セラミックである窒化アルミニウム（Ａｌ
Ｎ）または窒化珪素（ＳｉＮ）等をフィラーとして添加
したものを用いることができる。Here, the sealing resin 12 is made of an epoxy resin such as aluminum nitride (Al) which is a high thermal conductive ceramic.
N) or silicon nitride (SiN) added as a filler can be used.
【００３８】つぎに図６（ａ）に示すように、注入ノズ
ル等を用いてＡｇ−Ｐｄ等の導電物質を含有する導電性
接着剤を半導体素子２の導電性被膜７の上面から封止樹
脂１２により形成された緩やかな勾配を有するフィレッ
ト表面を経てキャリア基板３上の接地電極８の上面に至
るまで塗布して硬化させることにより導電層１３を形成
する。Next, as shown in FIG. 6A, a conductive adhesive containing a conductive substance such as Ag-Pd is applied from the upper surface of the conductive film 7 of the semiconductor element 2 to the sealing resin using an injection nozzle or the like. The conductive layer 13 is formed by applying the coating to the upper surface of the ground electrode 8 on the carrier substrate 3 through the fillet surface having a gentle gradient formed by the coating 12 and hardening the coating.
【００３９】つぎに図６（ｂ）に示すように、注入ノズ
ル等を用いて導電性被膜７の上面および導電層１３の露
出面を完全に被覆するように絶縁樹脂よりなる保護層１
０を塗布し、硬化させることにより本発明に関わる半導
体装置を得ることができる。Next, as shown in FIG. 6B, the protective layer 1 made of an insulating resin is completely covered with an injection nozzle or the like so as to completely cover the upper surface of the conductive film 7 and the exposed surface of the conductive layer 13.
By applying and curing 0, a semiconductor device according to the present invention can be obtained.
【００４０】このように導電層１３は、導電性被膜７お
よび導電性被膜７の表面と同一面まで充填された封止樹
脂１２による緩やかな勾配を有するフィレットの表面に
沿って形成されているために半導体素子２の角部が導電
層１３内に突出することがなく、かつ導電性被膜７の表
面から緩やかな勾配を有するフィレットの表面まで連続
した面に導電層１３を均一な厚さで形成することができ
るためクラック等の発生に対して大きな衝撃緩和力を備
えることが可能となる。また導電層１３はその全面を保
護層１０で被覆されているため、外気による腐食等を防
止することができる。As described above, the conductive layer 13 is formed along the surface of the fillet having a gentle gradient by the conductive film 7 and the sealing resin 12 filled up to the same surface as the surface of the conductive film 7. The conductive layer 13 is formed with a uniform thickness on the continuous surface from the surface of the conductive coating 7 to the surface of the fillet having a gentle gradient without the corners of the semiconductor element 2 protruding into the conductive layer 13. Therefore, it is possible to provide a large impact relaxation force against the occurrence of cracks and the like. Further, since the entire surface of the conductive layer 13 is covered with the protective layer 10, corrosion or the like due to outside air can be prevented.
【００４１】[0041]
【発明の効果】上記実施の形態より明らかなように本発
明は、フリップチップ接続されたキャリア基板と半導体
素子との接続部および半導体素子の周辺部に封止樹脂を
充填して導電性被膜の表面と同一面上からキャリア基板
上の接地電極の付近まで段差のない連続した緩やかな勾
配を有するフィレットを形成することにより導電性被膜
の上面とフィレットの上面を段差や角部の無い平滑な表
面とし、導電性被膜の表面の一部からフィレットの上面
およびキャリア基板上の接地電極の上面まで導電層を塗
布したのち、さらに導電性被膜と導電層の全面に絶縁樹
脂よりなる保護層を被覆しているために、急激な温度変
化、または導電層のガラス転移点以上の高温度環境下に
おける導電層の接着強度の低下やクラックの発生を防
ぎ、半導体素子の裏面に設けられた導電性被膜とキャリ
ア基板上の接地電極との電気的接続の信頼性を向上する
ことができる。As is apparent from the above embodiment, the present invention is directed to a method of filling a conductive film by filling a sealing resin in a connection portion between a flip chip-connected carrier substrate and a semiconductor element and a peripheral portion of the semiconductor element. The upper surface of the conductive film and the upper surface of the fillet are smooth with no steps or corners by forming a fillet with a continuous gentle gradient without steps from the same plane as the surface to the vicinity of the ground electrode on the carrier substrate. After applying the conductive layer from a part of the surface of the conductive film to the upper surface of the fillet and the upper surface of the ground electrode on the carrier substrate, furthermore, cover the entire surface of the conductive film and the conductive layer with a protective layer made of insulating resin. This prevents sudden changes in temperature or a decrease in the adhesive strength of the conductive layer and the occurrence of cracks in a high-temperature environment above the glass transition point of the conductive layer. It is possible to improve the reliability of electrical connection between the ground electrode on the conductive film and the carrier substrate provided.
【図面の簡単な説明】[Brief description of the drawings]
【図１】本発明の第１の実施の形態における半導体装置
の断面図FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention;
【図２】同半導体装置の平面図FIG. 2 is a plan view of the semiconductor device.
【図３】本発明の第２の実施の形態における半導体装置
の断面図FIG. 3 is a sectional view of a semiconductor device according to a second embodiment of the present invention;
【図４】同半導体装置の平面図FIG. 4 is a plan view of the semiconductor device.
【図５】（ａ）〜（ｄ）は本発明の第２の実施の形態に
おける半導体装置の製造方法を説明する前半工程図FIGS. 5A to 5D are first-half process diagrams illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention; FIGS.
【図６】（ａ）、（ｂ）は同製造方法の後半工程図FIGS. 6A and 6B are second half process charts of the manufacturing method.
【図７】従来の半導体装置を示す断面図FIG. 7 is a sectional view showing a conventional semiconductor device.
【図８】同半導体装置の平面図FIG. 8 is a plan view of the semiconductor device.
２ 半導体素子 ３ キャリア基板 ７ 導電性被膜 ８ 接地電極 １０ 保護層 １２ 封止樹脂 １３ 導電層 Reference Signs List 2 semiconductor element 3 carrier substrate 7 conductive film 8 ground electrode 10 protective layer 12 sealing resin 13 conductive layer
Claims (5)
キャリア基板と、そのキャリア基板にフリップチップ接
続された半導体素子と、前記キャリア基板と前記半導体
素子との接続部および前記半導体素子の周辺部に充填さ
れた封止樹脂と、前記半導体素子の裏面上に形成された
導電性被膜と、その導電性被膜と前記キャリア基板上の
前記接地電極とを電気的に接続する導電層と、その導電
層を被覆する保護層とを有する半導体装置。1. A carrier substrate having a ground electrode provided on a part of a surface thereof, a semiconductor element flip-chip connected to the carrier substrate, a connection portion between the carrier substrate and the semiconductor element, and a semiconductor element. A sealing resin filled in the peripheral portion, a conductive film formed on the back surface of the semiconductor element, a conductive layer for electrically connecting the conductive film and the ground electrode on the carrier substrate, A semiconductor device having a protective layer covering the conductive layer.
備え、裏面に格子状に配列された外部電極端子が設けら
れているキャリア基板と、そのキャリア基板表面の前記
複数のランド電極に対して導電性接着剤により接合され
た複数の突起電極を備える半導体素子と、前記キャリア
基板と前記半導体素子との接続部および前記半導体素子
の周辺部に充填された封止樹脂と、前記半導体素子裏面
上に形成された導電性被膜と、その導電性被膜とキャリ
ア基板上の前記接地電極とを電気的に接続する導電層
と、その導電層を被覆する保護層とを有する半導体装
置。2. A carrier substrate having a plurality of land electrodes and a ground electrode on a front surface, and having external electrode terminals arranged in a grid on a back surface, and a plurality of land electrodes on a surface of the carrier substrate. Semiconductor device having a plurality of protruding electrodes joined by a conductive adhesive, a sealing resin filled in a connection portion between the carrier substrate and the semiconductor device and a peripheral portion of the semiconductor device, and a back surface of the semiconductor device. A semiconductor device comprising: a conductive film formed thereon; a conductive layer that electrically connects the conductive film to the ground electrode on a carrier substrate; and a protective layer that covers the conductive layer.
脂の表面が、前記半導体素子の裏面上に設けられている
導電性被膜の表面と同一面を形成、または前記導電性被
膜の表面の一部を覆うように形成されている請求項１ま
たは２に記載の半導体装置。3. The surface of a sealing resin filled in a peripheral portion of a semiconductor element forms the same surface as a surface of a conductive film provided on a back surface of the semiconductor element, or a surface of the conductive film. 3. The semiconductor device according to claim 1, wherein the semiconductor device is formed so as to cover a part of the semiconductor device.
接地電極が設けられているキャリア基板にフリップチッ
プ接続する工程と、前記キャリア基板と前記半導体素子
との接続部および前記半導体素子の周辺部に封止樹脂を
充填して前記導電性被膜の上面の一辺からキャリア基板
上の前記接地電極の付近まで段差のない連続した緩やか
な勾配を有するフィレットを形成する工程と、前記導電
性被膜の上面から前記フィレットの上面およびキャリア
基板上の前記接地電極の上面まで導電性材料を塗布して
導電層を形成する工程と、前記導電性被膜と前記導電層
の全面を絶縁樹脂よりなる保護層によって被覆する工程
とを有する半導体装置の製造方法。4. A step of flip-chip connecting a semiconductor element having a conductive film on a back surface to a carrier substrate provided with a ground electrode, a connection part between the carrier substrate and the semiconductor element, and a peripheral part of the semiconductor element. Forming a fillet having a continuous gradual slope with no step from one side of the upper surface of the conductive film to the vicinity of the ground electrode on the carrier substrate by filling a sealing resin into the upper surface of the conductive film; Forming a conductive layer by applying a conductive material to the upper surface of the fillet and the upper surface of the ground electrode on the carrier substrate; and covering the entire surface of the conductive film and the conductive layer with a protective layer made of an insulating resin. And a method of manufacturing a semiconductor device.
複数の電極上に突起電極を形成してその突起電極上に導
電性接着剤を塗布する工程と、前記突起電極と裏面に一
定の間隔で格子状に形成された外部電極端子を有するキ
ャリア基板の表面の複数のランド電極とを前記導電性接
着剤により接合したのち前記導電性接着剤を熱硬化させ
る工程と、前記半導体素子と前記キャリア基板との接続
部および前記半導体素子の周辺部に封止樹脂を充填して
前記導電性被膜の上面の一辺からキャリア基板上の前記
接地電極の付近まで段差のない連続した緩やかな勾配を
有するフィレットを形成する工程と、前記導電性被膜の
上面から前記フィレットの上面およびキャリア基板上の
前記接地電極の上面まで導電性材料を塗布して導電層を
形成する工程と、前記導電性被膜と前記導電層の全面を
絶縁樹脂よりなる保護層によって被覆する工程とを有す
る半導体装置の製造方法。5. A step of forming a protruding electrode on a plurality of electrodes of a semiconductor element having a conductive film on the back surface and applying a conductive adhesive on the protruding electrode, and a predetermined distance between the protruding electrode and the back surface. Bonding a plurality of land electrodes on the surface of a carrier substrate having external electrode terminals formed in a lattice shape with the conductive adhesive, and then thermally curing the conductive adhesive, the semiconductor element and the carrier A fillet having a continuous gradual slope without a step from one side of the upper surface of the conductive film to the vicinity of the ground electrode on the carrier substrate by filling a sealing resin into a connection portion with a substrate and a peripheral portion of the semiconductor element. Forming a conductive layer by applying a conductive material from the upper surface of the conductive coating to the upper surface of the fillet and the upper surface of the ground electrode on the carrier substrate. Covering the entire surface of the conductive layer with a protective layer made of an insulating resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11177933A JP2001007257A (en) | 1999-06-24 | 1999-06-24 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11177933A JP2001007257A (en) | 1999-06-24 | 1999-06-24 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001007257A true JP2001007257A (en) | 2001-01-12 |
Family
ID=16039614
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11177933A Pending JP2001007257A (en) | 1999-06-24 | 1999-06-24 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2001007257A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010062286A (en) * | 2008-09-03 | 2010-03-18 | Toyoda Gosei Co Ltd | Semiconductor light emitting device |
-
1999
- 1999-06-24 JP JP11177933A patent/JP2001007257A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010062286A (en) * | 2008-09-03 | 2010-03-18 | Toyoda Gosei Co Ltd | Semiconductor light emitting device |
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