JP3650748B2 - Semiconductor package and manufacturing method thereof - Google Patents

Semiconductor package and manufacturing method thereof Download PDF

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Publication number
JP3650748B2
JP3650748B2 JP2001319218A JP2001319218A JP3650748B2 JP 3650748 B2 JP3650748 B2 JP 3650748B2 JP 2001319218 A JP2001319218 A JP 2001319218A JP 2001319218 A JP2001319218 A JP 2001319218A JP 3650748 B2 JP3650748 B2 JP 3650748B2
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carrier substrate
semiconductor element
gap
resin
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JP2003124402A (en
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博之 倉田
健司 田中
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New Japan Radio Co Ltd
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New Japan Radio Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体素子に形成したバンプがキャリア用基板にフェースダウンボンディングされて成る半導体パッケージにおいて、特にパッケージング後の半導体集積回路の特性変動を小さくできる半導体パッケージの構造およびその製造方法に関する。
【０００２】
【従来の技術】
従来の半導体パッケージの一例として、ＬＣＣ（Ｌｅａｄｌｅｓｓ Ｃｈｉｐ Ｃａｒｒｉｅｒ）構造の半導体パッケージの断面図を図３に示す。
図３において、チップ状の半導体素子１の各電極に設けられた金属バンプ２が、キャリア用基板３の第１層基板３ａ表面に設けられている導電パタ一ン４と電気的に接続されるようにフェースダウンボンディングされている。第１層基板３ａの裏面側には第２層基板３ｂが貼着されており、導電パターン４と電気的に接続するようにその側壁から裏面にかけて導電性の外部接続端子（ランド用パターン）５が設けられている。半導体素子１とキャリア用基板３との隙間はフィラー６を含むアンダーフィル樹脂７で充填され、全体をアンダーフィル樹脂７と同様にフィラー６を含むオーバーコート樹脂８で被覆された構造となっている。（低弾性樹脂膜９については後述する。）
【０００３】
図３の半導体パッケージの製造方法は、半導体素子１の金属バンプ２を超音波熱圧着によりキャリア用基板３の導電パターン４にフェースダウンボンディングした後、半導体素子１とキャリア用基板の隙間よりも小さい粒径のフィラー６を含むアンダーフィル樹脂７をディスペンス装置などを使用して前記隙間に注入・充填し、全体をアンダーフィル樹脂７と同様にフィラー６を含むオーバーコート樹脂８をポッティング法を使って封止し硬化する方法で行われている。
ここで、フィラー６を添加した樹脂を使用することにより、半導体装置の耐湿性や放熱性を向上させることができる。
【０００４】
一方、このような半導体パッケージの構造および製造方法では、樹脂を硬化する場合の熱処理時に、半導体素子１とキャリア用基板３の隙間に充填されたフィラー６を含むアンダーフィル樹脂７と半導体素子１との熱膨張係数差などに基づき、半導体素子１にストレスが加わり、半導体素子１の特性が変動してしまうという問題がある。
【０００５】
このような特性の変動を抑制するため、図３に示されるように、半導体素子１の表面に低弾性樹脂膜９を形成して、樹脂の熱硬化収縮での影響を緩和する構造のものも用いられている。
【０００６】
【発明が解決しようとする課題】
従来のような半導体パッケージおよびその製造方法では、樹脂を硬化する場合の熱処理時に、フィラー６を含むアンダーフィル樹脂７から半導体素子１にストレスが加わり、半導体素子の特性が変動してしまうという問題がある。
一方、アンダーフィル樹脂７の成分からフィラー６を除去すればパッケージ単体としては低弾性となるが、反りの発生による組立の難しさ、およびパッケージの放熱性低下や、吸湿に弱くなるといった問題がある。
【０００７】
また、半導体素子１の表面に低弾性樹脂膜９を形成する場合、ウェハプロセスのどこかで追加工程を設けないと実現することができないため、コストアップに繋がるという問題がある。
本発明はこのような問題を解決するためになされたもので、特性のバラツキが少なく、かつ、小型の半導体パッケージおよびその製造方法を提供することを目的とする。
【０００８】
【課題を解決するための手段】
本発明の半導体パッケージは、キャリア用基板と、該キャリア用基板表面の導電パターンに、表面に形成された金属バンプがフェースダウンで接続される半導体素子と、前記キャリア用基板と前記半導体素子の隙間にアンダーフィル樹脂が充填されるとともに前記半導体素子全体および前記アンダーフィル樹脂を含む前記キャリア用基板表面を被覆するオーバーコート樹脂からなる半導体パッケージにおいて、前記アンダーフィル樹脂に含有するフィラーの粒径が前記キャリア用基板表面と前記半導体素子表面の間隔より大きく、前記キャリア用基板と前記半導体素子の隙間には前記フィラーを含まない前記アンダーフィル樹脂により充填され、かつ前記隙間の外周は前記フィラーを含む前記アンダーフィル樹脂で覆われ、前記半導体素子全体および前記アンダーフィル樹脂を含む前記キャリア用基板表面が前記オーバーコート樹脂で覆われていることを特徴とするものである。
また、本発明の半導体パッケージの製造方法として、キャリア用基板表面の導電パターンに半導体素子表面に形成した金属バンプをフェースダウンで接続する工程と、前記キャリア用基板表面と前記半導体素子表面の間隔より粒径が大きいフィラーを含有するアンダーフィル樹脂を用いて前記キャリア用基板表面と前記半導体素子の隙間に前記アンダーフィル樹脂を充填することにより、前記隙間には前記フィラーを含まない前記アンダーフィル樹脂を充填し、かつ前記隙間以外の外周は前記フィラーを含む前記アンダーフィル樹脂で被覆する工程と、前記半導体素子全体および前記アンダーフィル樹脂を含む前記キャリア用基板表面をオーバーコート樹脂で被覆する工程とを含むことを特徴とするものである。
【０００９】
【作用】
本発明による半導体パッケージおよび製造方法を適用することにより、半導体素子とキャリア用基板の隙間が小さくなり組立工程で最も特性変動に影響を与える樹脂に関してチップ面への絶対量を少なくすることが出来る。またフィラーを大きくすることにより、キャリア基板と半導体素子の隙間へはフィラーを除くエポキシ樹脂成分と応力緩和剤成分が充填されることになり、低弾性構造が実現される。
そのため、製造工程で樹脂熱硬化収縮時のストレスがかかっても、そのストレスを緩和することができ、特性の変動を抑制できる。
【００１０】
【発明の実施の形態】
本発明による半導体パッケージの構造の一例として、ＬＣＣ構造の半導体パッケージの断面図を図１に示す。
半導体パッケージのキャリア用基板３は、たとえばアルミナセラミック基板などからなる絶縁基板に銅などの金属メッキ層などにより導電パターン４が形成された第１層基板３ａと、導電パターン４から側壁を経て裏面側に電気的に接続されるように銅などの金属メッキ層からなる外部電極端子（ランド用パターン）５が形成された第２層基板３ｂとから形成されている。このキャリア用基板３は、第１層基板３ａと第２層基板３ｂとの２層構造であるが、１層あるいは３層以上の接合で形成したものでもよい。
【００１１】
半導体素子１の金属バンプ２を、キャリア用基板３表面の導電パターン４に、フェースダウンボンディングすることにより、キャリア用基板３の側壁を経てその裏面側に導出される外部接続端子５に電気的に接続され、実装基板などにマウントできる構造になっている。
【００１２】
半導体素子１とキャリア用基板３の隙間(ギャップ)の間隔は例えば２５μｍにする。なお、この間隔はフリップチップ下のボイド発生を防ぐ為、チップ面積等を考慮してフィラー１０を除くアンダーフィル樹脂７が隙間に充填されるだけの最小限の高さを確保する必要があるとともに、特性変動に影響を与える樹脂のチップ面への絶対量を少なくすることも考慮し、例えば、１０〜３０μｍ程度であれば良い。
【００１３】
一方、アンダーフィル樹脂７に含まれるフィラー１０の粒径は半導体素子１とキャリア用基板３の隙間より大きいもの（例えば３０μｍ）を使用するようにする。これにより、注入時にフィラー１０が隙間にせき止められ、半導体素子１とキャリア用基板３の隙間にはフィラー１０を除くエポキシ樹脂成分とシリコーン等の応力緩和剤成分のみの樹脂が充填されており、一方、半導体素子１とキャリア用基板３の隙間以外の周辺の樹脂にはせき止められたフィラー１０を含んでいることになる。
そして半導体素子１を含むキャリア用基板３表面全体は、フィラー６を含むエポキシ樹脂などのオーバーコート樹脂８で被覆されている。なお、オーバーコート樹脂８のフィラー６の粒径は特に規定しなくても良い。
【００１４】
次に本発明の具体的な製造方法の例を示す。
図１のキャリア用基板３の第１層基板３ａは、たとえばヤング率の高いアルミナセラミック基板などからなる絶縁基板を用い、導電ぺ一ストあるいは銅などの金属メッキ層などにより導電パターン４を形成する。一方、第２層基板３ｂは、同じくアルミナセラミック基板などからなる絶縁基板を用い、側壁を経て裏面側に電気的に接続されるように銅などの金属メッキ層からなる外部電極端子（ランド用パターン）５を形成し、第１層基板３ａとラミネート工法などで貼着することで、導電パターン４から外部接続端子５まで電気的に接続されたキャリア用基板３を形成する。キャリア用基板３は、第１層基板３ａと第２層基板３ｂとの接合により形成したが、１層あるいは３層以上の接合で形成したものでもよい。
【００１５】
半導体集積回路が形成されたベアチップ状の半導体素子１表面の各電極には金などからなる金属バンプ２を設け、金属バンプ２をキャリア用基板３の表面側の導電パターン４に、超音波熱圧着によりフェースダウンボンディングを行う。
なお、図１では１個の半導体素子１のみ示しているが、この段階では、キャリア用基板３は集合基板として、マトリックス状に複数の半導体素子１がフェイスダウンボンディングされる。
【００１６】
ここで、金属バンプ２の高さは、半導体素子１とキャリア用基板３の隙間(ギャップ)の間隔が例えば２５μｍになるような高さに形成する。なお、この間隔はフリップチップ下のボイド発生を防ぐ為、チップ面積等を考慮してフィラー１０を除くアンダーフィル樹脂７が隙間に充填されるだけの最小限の高さを確保する必要があるとともに、特性変動に影響を与える樹脂のチップ面への絶対量を少なくすることも考慮し、例えば、１０〜３０μｍであれば良い。
【００１７】
次に、半導体素子１とキャリア用基板３の隙間にディスペンス装置を使用してアンダーフィル樹脂７を注入、硬化して封止を行う。このときアンダーフィル樹脂７に含まれるのフィラー１０の粒径は、半導体素子１とキャリア用基板３の隙間より大きい、例えば３０μｍのものを用いる。
【００１８】
このことで注入時に隙間に制限されるような形でシリカまたはアルミナなどからなるフィラー１０がせき止められ、半導体素子１とキャリア用基板３の隙間にはフィラー１０を除くエポキシ樹脂成分とシリコーン等の応力緩和剤成分のみの樹脂が充填される。一方、半導体素子１とキャリア用基板３の隙間以外の周辺の部分の樹脂には隙間によりせき止められたフィラー１０を含んでいるため、耐湿性や放熱性などの信頼性の問題も防ぐことが出来る。
【００１９】
そして半導体素子１を含むキャリア用基板３表面全体を、フィラー６を含むエポキシ樹脂などによるオーバーコート樹脂８でポッティング法などを使って被覆後硬化させる。なお、オーバーコート樹脂８のフィラー６の粒径は特に規定しなくて良い。
最後に、この段階では集合基板状になっているため、個別の半導体パッケージにダイシングして分割することで本発明のＬＣＣ構造の半導体パッケージが形成される。
【００２０】
図１では、ＬＣＣ構造の半導体パッケージの例を挙げたが、本発明の構造およびその製造方法は、このパッケージにこだわるものではなく、半導体素子をキャリア用基板にフェイスダウンで接続する構造のパッケージであれば適用することができる。
【００２１】
図２に、シャントレギュレータの半導体素子を使って、従来の構造と本発明の構造でパッケージを組み立てて、基準電圧分布を比較したデータを示す。
本発明の構造での基準電圧の特性のバラツキは、従来構造の約５０％であり、半導体素子本来のピーク値（１．２２５Ｖ）からのずれもほとんどなくなっていることがわかる。
【００２２】
【発明の効果】
本発明の半導体パッケージの構造およびその製造方法により、組立工程で樹脂熱硬化収縮時のストレスがかかっても、そのストレスが緩和されるため、半導体装置の特性の変動を抑制でき、半導体素子上に低弾性樹脂膜を形成する必要がなくなりコストが上昇するという問題も発生しない。
以上のように、本発明によれば、半導体装置の製品コストを下げるとともに特性バラツキが少なく、かつ、小型の半導体装置およびその製造方法を提供することが出来る。
【図面の簡単な説明】
【図１】本発明によるＬＣＣ構造の半導体パッケージの断面図である。
【図２】本発明と従来の半導体パッケージでのシャントレギュレータの基準電圧分布である。
【図３】従来のＬＣＣ構造の半導体パッケージの断面図である。
【符号の説明】
１． 半導体素子
２． 金属バンプ
３． キャリア用基板
３ａ．第１層基板
３ｂ．第２層基板
４． 導電パターン
５． 外部接続端子
６、１０ フィラー
７． アンダーフィル樹脂
８． オーバーコート樹脂
９． 低弾性樹脂膜[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor package structure in which bumps formed on a semiconductor element are face-down bonded to a carrier substrate, and particularly to a structure of a semiconductor package that can reduce characteristic fluctuations of a semiconductor integrated circuit after packaging, and a manufacturing method thereof.
[0002]
[Prior art]
As an example of a conventional semiconductor package, FIG. 3 shows a cross-sectional view of a semiconductor package having an LCC (Leadless Chip Carrier) structure.
In FIG. 3, the metal bumps 2 provided on the respective electrodes of the chip-shaped semiconductor element 1 are electrically connected to the conductive pattern 4 provided on the surface of the first layer substrate 3a of the carrier substrate 3. It is face-down bonded. A second layer substrate 3b is adhered to the back surface side of the first layer substrate 3a, and conductive external connection terminals (land patterns) 5 from the side walls to the back surface so as to be electrically connected to the conductive pattern 4. Is provided. The gap between the semiconductor element 1 and the carrier substrate 3 is filled with an underfill resin 7 containing a filler 6, and the whole is covered with an overcoat resin 8 containing a filler 6 in the same manner as the underfill resin 7. . (The low elastic resin film 9 will be described later.)
[0003]
3 is smaller than the gap between the semiconductor element 1 and the carrier substrate after the metal bumps 2 of the semiconductor element 1 are face-down bonded to the conductive pattern 4 of the carrier substrate 3 by ultrasonic thermocompression bonding. An underfill resin 7 containing a particle size filler 6 is poured and filled into the gap using a dispensing device or the like, and the entire overcoat resin 8 containing the filler 6 is potted using the potting method in the same manner as the underfill resin 7. It is performed by a method of sealing and curing.
Here, by using the resin to which the filler 6 is added, the moisture resistance and heat dissipation of the semiconductor device can be improved.
[0004]
On the other hand, in such a semiconductor package structure and manufacturing method, the underfill resin 7 including the filler 6 filled in the gap between the semiconductor element 1 and the carrier substrate 3 and the semiconductor element 1 during the heat treatment for curing the resin, There is a problem that stress is applied to the semiconductor element 1 based on the difference in thermal expansion coefficient between the two and the characteristics of the semiconductor element 1 fluctuate.
[0005]
In order to suppress such fluctuations in characteristics, as shown in FIG. 3, a structure having a structure in which a low elastic resin film 9 is formed on the surface of the semiconductor element 1 so as to alleviate the influence of the thermosetting shrinkage of the resin. It is used.
[0006]
[Problems to be solved by the invention]
In the conventional semiconductor package and the manufacturing method thereof, there is a problem that stress is applied to the semiconductor element 1 from the underfill resin 7 including the filler 6 during the heat treatment when the resin is cured, and the characteristics of the semiconductor element fluctuate. is there.
On the other hand, if the filler 6 is removed from the components of the underfill resin 7, the package itself has low elasticity, but there are problems such as difficulty in assembly due to warpage, reduced heat dissipation of the package, and weakness in moisture absorption. .
[0007]
Further, when the low-elasticity resin film 9 is formed on the surface of the semiconductor element 1, it cannot be realized unless an additional process is provided somewhere in the wafer process, leading to a problem that the cost is increased.
The present invention has been made to solve such a problem, and an object of the present invention is to provide a small-sized semiconductor package and a method for manufacturing the same with little variation in characteristics.
[0008]
[Means for Solving the Problems]
The semiconductor package of the present invention includes a carrier substrate, a semiconductor element in which metal bumps formed on the surface are connected face-down to the conductive pattern on the surface of the carrier substrate, and a gap between the carrier substrate and the semiconductor element. In the semiconductor package made of an overcoat resin that covers the entire surface of the semiconductor element and the substrate substrate for the carrier containing the underfill resin, the particle size of the filler contained in the underfill resin is The gap between the carrier substrate surface and the semiconductor element surface is larger, the gap between the carrier substrate and the semiconductor element is filled with the underfill resin not containing the filler, and the outer periphery of the gap contains the filler Covered with underfill resin, all the semiconductor elements And the carrier substrate surface including the underfill resin is characterized in that it is covered with the overcoat resin.
According to another aspect of the present invention, there is provided a semiconductor package manufacturing method comprising: a step of connecting a metal bump formed on a semiconductor element surface face-down to a conductive pattern on a carrier substrate surface; and a distance between the carrier substrate surface and the semiconductor element surface. By filling the underfill resin in the gap between the carrier substrate surface and the semiconductor element using an underfill resin containing a filler having a large particle size, the gap does not contain the filler. Filling the outer periphery other than the gap with the underfill resin containing the filler, and covering the entire semiconductor element and the carrier substrate surface containing the underfill resin with an overcoat resin. It is characterized by including.
[0009]
[Action]
By applying the semiconductor package and the manufacturing method according to the present invention, the gap between the semiconductor element and the carrier substrate is reduced, and the absolute amount on the chip surface can be reduced with respect to the resin that most affects the characteristic variation in the assembly process. Further, by increasing the filler, the gap between the carrier substrate and the semiconductor element is filled with the epoxy resin component and the stress relaxation agent component excluding the filler, thereby realizing a low elastic structure.
For this reason, even when a stress is applied during the thermosetting shrinkage of the resin in the manufacturing process, the stress can be alleviated and the variation in characteristics can be suppressed.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
As an example of the structure of a semiconductor package according to the present invention, a cross-sectional view of a semiconductor package having an LCC structure is shown in FIG.
The substrate 3 for the carrier of the semiconductor package includes a first layer substrate 3a in which a conductive pattern 4 is formed on an insulating substrate made of, for example, an alumina ceramic substrate by a metal plating layer such as copper, and the back surface side through the side wall from the conductive pattern 4 And a second layer substrate 3b on which external electrode terminals (land patterns) 5 made of a metal plating layer such as copper are formed so as to be electrically connected to the substrate. The carrier substrate 3 has a two-layer structure of a first layer substrate 3a and a second layer substrate 3b, but may be formed by bonding one layer or three or more layers.
[0011]
The metal bumps 2 of the semiconductor element 1 are electrically bonded to the external connection terminals 5 led out to the back side through the side walls of the carrier substrate 3 by face-down bonding to the conductive pattern 4 on the surface of the carrier substrate 3. It is connected and can be mounted on a mounting board.
[0012]
The gap (gap) between the semiconductor element 1 and the carrier substrate 3 is set to 25 μm, for example. In addition, in order to prevent void generation under the flip chip, it is necessary to secure a minimum height that allows the underfill resin 7 excluding the filler 10 to be filled in the gap in consideration of the chip area and the like. In consideration of reducing the absolute amount of the resin on the chip surface that affects the characteristic variation, for example, it may be about 10 to 30 μm.
[0013]
On the other hand, the filler 10 contained in the underfill resin 7 has a particle size larger than the gap between the semiconductor element 1 and the carrier substrate 3 (for example, 30 μm). As a result, the filler 10 is blocked in the gap at the time of injection, and the gap between the semiconductor element 1 and the carrier substrate 3 is filled with an epoxy resin component excluding the filler 10 and a resin containing only a stress relaxation component such as silicone, The peripheral resin other than the gap between the semiconductor element 1 and the carrier substrate 3 contains the filler 10 that is blocked.
The entire surface of the carrier substrate 3 including the semiconductor element 1 is covered with an overcoat resin 8 such as an epoxy resin including a filler 6. Note that the particle size of the filler 6 of the overcoat resin 8 may not be specified.
[0014]
Next, an example of a specific production method of the present invention will be shown.
The first substrate 3a of the carrier substrate 3 in FIG. 1 uses an insulating substrate made of, for example, an alumina ceramic substrate having a high Young's modulus, and the conductive pattern 4 is formed by a conductive paste or a metal plating layer such as copper. . On the other hand, the second layer substrate 3b is an insulating substrate made of an alumina ceramic substrate or the like, and external electrode terminals (land pattern) made of a metal plating layer such as copper so as to be electrically connected to the back side through the side wall. ) 5 is formed and bonded to the first layer substrate 3a by a laminating method or the like, thereby forming the carrier substrate 3 electrically connected from the conductive pattern 4 to the external connection terminal 5. The carrier substrate 3 is formed by bonding the first layer substrate 3a and the second layer substrate 3b, but may be formed by bonding one layer or three or more layers.
[0015]
A metal bump 2 made of gold or the like is provided on each electrode on the surface of the bare chip-shaped semiconductor element 1 on which the semiconductor integrated circuit is formed, and the metal bump 2 is ultrasonically thermocompression bonded to the conductive pattern 4 on the surface side of the carrier substrate 3. Then, face down bonding is performed.
Although only one semiconductor element 1 is shown in FIG. 1, at this stage, a plurality of semiconductor elements 1 are face-down bonded in a matrix with the carrier substrate 3 as an aggregate substrate.
[0016]
Here, the height of the metal bump 2 is formed such that the gap between the semiconductor element 1 and the carrier substrate 3 is, for example, 25 μm. In addition, in order to prevent void generation under the flip chip, it is necessary to secure a minimum height that allows the underfill resin 7 excluding the filler 10 to be filled in the gap in consideration of the chip area and the like. In consideration of reducing the absolute amount of the resin on the chip surface that affects the characteristic variation, for example, it may be 10 to 30 μm.
[0017]
Next, the underfill resin 7 is injected into the gap between the semiconductor element 1 and the carrier substrate 3 by using a dispensing device, and cured and sealed. At this time, the particle size of the filler 10 contained in the underfill resin 7 is larger than the gap between the semiconductor element 1 and the carrier substrate 3, for example, 30 μm.
[0018]
As a result, the filler 10 made of silica or alumina is damped in such a manner that the gap is limited at the time of injection, and the gap between the semiconductor element 1 and the carrier substrate 3 is a stress such as an epoxy resin component excluding the filler 10 and silicone. The resin of only the relaxation agent component is filled. On the other hand, since the resin in the peripheral portion other than the gap between the semiconductor element 1 and the carrier substrate 3 contains the filler 10 blocked by the gap, problems of reliability such as moisture resistance and heat dissipation can be prevented. .
[0019]
Then, the entire surface of the carrier substrate 3 including the semiconductor element 1 is cured after being coated with an overcoat resin 8 such as an epoxy resin including a filler 6 using a potting method or the like. The particle size of the filler 6 of the overcoat resin 8 does not have to be specified.
Finally, since it is in the form of a collective substrate at this stage, the semiconductor package having the LCC structure of the present invention is formed by dicing and dividing into individual semiconductor packages.
[0020]
In FIG. 1, an example of a semiconductor package having an LCC structure is given. However, the structure of the present invention and the manufacturing method thereof are not limited to this package. If applicable, it can be applied.
[0021]
FIG. 2 shows data comparing reference voltage distributions by assembling a package with a conventional structure and the structure of the present invention using a semiconductor element of a shunt regulator.
It can be seen that the variation in the characteristics of the reference voltage in the structure of the present invention is about 50% of that in the conventional structure, and there is almost no deviation from the original peak value (1.225 V) of the semiconductor element.
[0022]
【The invention's effect】
With the structure of the semiconductor package and the manufacturing method thereof according to the present invention, even when stress is applied during resin thermosetting shrinkage in the assembly process, the stress is alleviated, so that fluctuations in the characteristics of the semiconductor device can be suppressed and There is no need to form a low-elasticity resin film, and there is no problem of increased costs.
As described above, according to the present invention, it is possible to provide a small-sized semiconductor device and a method for manufacturing the same, which reduce the product cost of the semiconductor device and reduce the characteristic variation.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a semiconductor package having an LCC structure according to the present invention.
FIG. 2 is a reference voltage distribution of a shunt regulator in the present invention and a conventional semiconductor package.
FIG. 3 is a cross-sectional view of a conventional semiconductor package having an LCC structure.
[Explanation of symbols]
1. 1. Semiconductor element Metal bump 3. Carrier substrate 3a. First layer substrate 3b. Second layer substrate 4. 4. Conductive pattern External connection terminals 6, 10 Filler 7. Underfill resin8. 8. Overcoat resin Low elastic resin film

Claims (2)

キャリア用基板と、該キャリア用基板表面の導電パターンに、表面に形成された金属バンプがフェースダウンで接続される半導体素子と、前記キャリア用基板と前記半導体素子の隙間にアンダーフィル樹脂が充填されるとともに前記半導体素子全体および前記アンダーフィル樹脂を含む前記キャリア用基板表面を被覆するオーバーコート樹脂からなる半導体パッケージにおいて、前記アンダーフィル樹脂に含有するフィラーの粒径が前記キャリア用基板表面と前記半導体素子表面の間隔より大きく、前記キャリア用基板と前記半導体素子の隙間には前記フィラーを含まない前記アンダーフィル樹脂により充填され、かつ前記隙間の外周は前記フィラーを含む前記アンダーフィル樹脂で覆われ、前記半導体素子全体および前記アンダーフィル樹脂を含む前記キャリア用基板表面が前記オーバーコート樹脂で覆われていることを特徴とする半導体パッケージ。A carrier substrate, a semiconductor element in which metal bumps formed on the surface are connected face down to the conductive pattern on the surface of the carrier substrate, and an underfill resin is filled in a gap between the carrier substrate and the semiconductor element. In addition, in the semiconductor package made of an overcoat resin that covers the entire semiconductor element and the carrier substrate surface including the underfill resin, the particle size of the filler contained in the underfill resin is different from that of the carrier substrate surface and the semiconductor. The gap between the element surface is larger than the gap between the carrier substrate and the semiconductor element is filled with the underfill resin without the filler, and the outer periphery of the gap is covered with the underfill resin with the filler, The entire semiconductor device and the underfill tree A semiconductor package substrate surface for the carrier is characterized in that it is covered with the overcoat resin containing. キャリア用基板表面の導電パターンに半導体素子表面に形成した金属バンプをフェースダウンで接続する工程と、前記キャリア用基板表面と前記半導体素子表面の間隔より粒径が大きいフィラーを含有するアンダーフィル樹脂を用いて前記キャリア用基板表面と前記半導体素子の隙間に前記アンダーフィル樹脂を充填することにより、前記隙間には前記フィラーを含まない前記アンダーフィル樹脂を充填し、かつ前記隙間以外の外周は前記フィラーを含む前記アンダーフィル樹脂で被覆する工程と、前記半導体素子全体および前記アンダーフィル樹脂を含む前記キャリア用基板表面をオーバーコート樹脂で被覆する工程とを含むことを特徴とする半導体パッケージの製造方法。A step of connecting a metal bump formed on the surface of the semiconductor element to the conductive pattern on the surface of the carrier substrate in a face-down manner; and By using the underfill resin to fill the gap between the carrier substrate surface and the semiconductor element, the gap does not contain the filler, and the outer periphery other than the gap is the filler. A method of manufacturing a semiconductor package, comprising: coating with the underfill resin including: and coating the entire semiconductor element and the carrier substrate surface including the underfill resin with an overcoat resin.
JP2001319218A 2001-10-17 2001-10-17 Semiconductor package and manufacturing method thereof Expired - Fee Related JP3650748B2 (en)

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