JP3519285B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP3519285B2 JP3519285B2 JP27341198A JP27341198A JP3519285B2 JP 3519285 B2 JP3519285 B2 JP 3519285B2 JP 27341198 A JP27341198 A JP 27341198A JP 27341198 A JP27341198 A JP 27341198A JP 3519285 B2 JP3519285 B2 JP 3519285B2
- Authority
- JP
- Japan
- Prior art keywords
- heat dissipation
- semiconductor
- metal plating
- semiconductor element
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
Landscapes
- Wire Bonding (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、フリップチップ
で実装した半導体素子を支持する半導体キャリア基板に
関するもので、特に、動作時に発熱する前記半導体素子
からの放熱性の効果を向上させることに特徴を有する半
導体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor carrier substrate that supports a semiconductor element mounted by flip chip, and is particularly characterized by improving the effect of heat radiation from the semiconductor element that generates heat during operation. The present invention relates to a semiconductor device having the same.
【０００２】[0002]
【従来の技術】以下、図面を参照して従来の半導体装置
の構造を説明する。図６および図７は従来の半導体装置
の断面図および平面図である。図６に示す様に、電極パ
ッド５にバンプ６の形成された半導体素子２が、その主
面側を下にして、支持体であるセラミックを絶縁基体と
した多層回路基板よりなる半導体キャリア基板４に接合
されている。半導体素子２上に形成されたバンプ６と半
導体キャリア基板４上の複数の電極７とが半田或いは、
導電性接着剤８により接合されている。そして、接合さ
れた半導体素子２と半導体キャリア基板４との隙間には
エポキシ系の封止樹脂９が充填被覆されている。尚、半
導体キャリア基板４は、その裏面に外部端子１１を有
し、電極５と外部端子１１とは、半導体キャリア基板４
内に形成されたビア（図示せず）により、内部接続され
ているものである。また、図７に示す様に、半導体キャ
リア基板４上面には、半導体素子２がフリップチップ実
装されており、その周囲には、エポキシ系の封止樹脂７
が半導体素子２と半導体キャリア基板４との隙間に充填
されてフィレットが形成されおり、内層に接続するため
の金属配線１２が形成されているものである。製品状態
としては、半導体素子２裏面の露出側にエポキシ系のマ
ークインク１０で品番・密番等を捺印している半導体装
置である。2. Description of the Related Art The structure of a conventional semiconductor device will be described below with reference to the drawings. 6 and 7 are a cross-sectional view and a plan view of a conventional semiconductor device. As shown in FIG. 6, the semiconductor element substrate 2 having the bumps 6 formed on the electrode pads 5 is a semiconductor carrier substrate 4 made of a multilayer circuit board in which the main surface of the semiconductor element 2 is a ceramic insulating substrate. Is joined to. The bumps 6 formed on the semiconductor element 2 and the plurality of electrodes 7 on the semiconductor carrier substrate 4 are soldered or
It is joined by a conductive adhesive 8. An epoxy-based encapsulating resin 9 is filled and covered in the gap between the bonded semiconductor element 2 and semiconductor carrier substrate 4. The semiconductor carrier substrate 4 has external terminals 11 on its back surface, and the electrodes 5 and the external terminals 11 are connected to each other by the semiconductor carrier substrate 4.
They are internally connected by vias (not shown) formed inside. Further, as shown in FIG. 7, the semiconductor element 2 is flip-chip mounted on the upper surface of the semiconductor carrier substrate 4, and the epoxy sealing resin 7 is provided around the semiconductor element 2.
Is filled in the gap between the semiconductor element 2 and the semiconductor carrier substrate 4 to form a fillet, and the metal wiring 12 for connecting to the inner layer is formed. As a product state, the semiconductor device is a semiconductor device in which the exposed side of the back surface of the semiconductor element 2 is stamped with the epoxy mark ink 10 such as a product number and a serial number.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら前記従来
の半導体装置の構造では、消費電力が高い仕様の半導体
素子を用いてフリップチップ実装した場合、急激な半導
体素子の温度上昇により半導体素子が破壊し、半導体装
置が動作しなくなるといった不具合が発生する。そのた
め、高放熱仕様の半導体装置の実現が必要不可欠であっ
た。また、放熱板等を取り付けると半導体素子の温度上
昇は小さく半導体装置の動作不良は発生しないが、半導
体装置の薄型化や軽量化の実現ができなくなるといった
技術的な課題が発生する。However, in the structure of the conventional semiconductor device described above, when flip-chip mounting is performed using a semiconductor element with high power consumption specifications, the semiconductor element is destroyed due to a rapid temperature rise of the semiconductor element, A problem occurs that the semiconductor device does not operate. Therefore, it is essential to realize a semiconductor device with high heat dissipation specifications. Further, when a heat sink or the like is attached, the temperature rise of the semiconductor element is small and the malfunction of the semiconductor device does not occur, but there is a technical problem that the semiconductor device cannot be made thinner and lighter.
【０００４】したがって、この発明の目的は、前記従来
の課題を解決するもので、半導体素子より発生する熱の
放熱特性を向上させることはもちろん、半導体装置の薄
型化、軽量化も実現、確保でき、また放熱板の取り付け
も可能にした半導体装置を提供することである。Therefore, an object of the present invention is to solve the above-mentioned conventional problems, and it is possible to realize and secure the thinning and weight reduction of a semiconductor device, as well as improving the heat radiation characteristic of the heat generated from the semiconductor element. Another object of the present invention is to provide a semiconductor device in which a heat sink can be attached.
【０００５】[0005]
【課題を解決するための手段】前記課題を解決するため
にこの発明の請求項１記載の半導体装置は、半導体キャ
リア基板の半導体素子実装エリアにフリップチップで実
装した半導体素子を支持し、前記半導体キャリア基板の
上面に複数の電極と配線を形成した半導体装置であっ
て、前記半導体キャリア基板の上面の前記複数の電極と
配線以外の部分に、熱伝導性が良好な金属をめっきした
金属めっき放熱エリアと、前記半導体素子実装エリアか
ら前記金属めっき放熱エリアに導き、外周部が前記半導
体チップの上面レベルまで形成された金属めっき放熱パ
ターンとを設けたことを特徴とする。In order to solve the above problems, a semiconductor device according to claim 1 of the present invention supports a semiconductor element mounted by flip-chip in a semiconductor element mounting area of a semiconductor carrier substrate, A semiconductor device having a plurality of electrodes and wiring formed on an upper surface of a carrier substrate, wherein metal plating heat radiation is obtained by plating a metal having good thermal conductivity on a portion other than the plurality of electrodes and wiring on the upper surface of the semiconductor carrier substrate. An area and a metal-plating heat radiation pattern, which is guided from the semiconductor element mounting area to the metal-plating heat radiation area and whose outer peripheral portion is formed to the upper surface level of the semiconductor chip, are provided.
【０００６】このように、半導体キャリア基板の上面の
複数の電極と配線以外の部分に、熱伝導性が良好な金属
をめっきした金属めっき放熱エリアと、半導体素子実装
エリアから金属めっき放熱エリアに導き、外周部が前記
半導体チップの上面レベルまで形成された金属めっき放
熱パターンとを設けたので、動作時に発熱する半導体素
子からの熱をプリント実装基板へ効率良く放散させるこ
とができ、熱抵抗の低い半導体装置を実現できる。金属
めっき放熱パターンの外周部の金属めっき放熱層の体積
の増加によりさらに放熱性が向上する。また、金属めっ
き放熱パターンの外周部と半導体素子の上面が面一にな
っているので放熱板の取付けが可能になる。As described above, a portion other than the plurality of electrodes and wirings on the upper surface of the semiconductor carrier substrate is plated with a metal having a good thermal conductivity on a metal plating heat radiation area and a semiconductor element mounting area is led to a metal plating heat radiation area. Since the outer peripheral portion is provided with the metal plating heat radiation pattern formed to the upper surface level of the semiconductor chip, heat from the semiconductor element that generates heat during operation can be efficiently dissipated to the printed circuit board, and the thermal resistance is low. A semiconductor device can be realized. The heat dissipation is further improved by increasing the volume of the metal plating heat dissipation layer on the outer periphery of the metal plating heat dissipation pattern. Further, since the outer peripheral portion of the metal plating heat radiation pattern is flush with the upper surface of the semiconductor element, the heat radiation plate can be attached.
【０００７】[0007]
【０００８】請求項２記載の半導体装置は、請求項１に
おいて、金属めっき放熱エリアに形成した金属めっき放
熱層の断面形状を、波形や凹凸形として表面積を大きく
した。このように、金属めっき放熱エリアに形成した金
属めっき放熱層の断面形状を、波形や凹凸形として表面
積を大きくしたので、放熱性の向上を図ることができ
る。According to a second aspect of the present invention, in the semiconductor device according to the first aspect , the metal plating heat dissipation layer formed in the metal plating heat dissipation area has a cross-sectional shape that is corrugated or uneven to increase the surface area. In this way, since the cross-sectional shape of the metal-plated heat dissipation layer formed in the metal-plated heat dissipation area has a corrugated or uneven shape to increase the surface area, heat dissipation can be improved.
【０００９】請求項３記載の半導体装置は、請求項１ま
たは２において、金属めっき放熱エリアに形成した金属
めっき放熱層の上面に接し、かつ半導体素子の裏面と接
触させて放熱板を取付けた。このように、金属めっき放
熱エリアに形成した金属めっき放熱層の上面に接し、か
つ半導体素子の裏面と接触させて放熱板を取付けたの
で、半導体素子裏面のみでなく、半導体素子と金属めっ
き放熱層とを接触させることにより、発熱する半導体素
子からの熱を効率良く放散させることができ、優れた放
熱効果を有する。According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect , the semiconductor device is in contact with the upper surface of the metal plating heat dissipation layer formed in the metal plating heat dissipation area and in contact with the back surface of the semiconductor element. A heat sink is attached. In this way, since the heat dissipation plate was attached in contact with the top surface of the metal plating heat dissipation layer formed in the metal plating heat dissipation area and in contact with the back surface of the semiconductor element, not only the back surface of the semiconductor element but also the semiconductor element and the metal plating heat dissipation layer By contacting with, the heat generated from the semiconductor element can be efficiently dissipated, and an excellent heat dissipation effect can be obtained.
【００１０】[0010]
【発明の実施の形態】参考例を図１および図２に基づい
て説明する。図１は参考例の半導体装置の断面図であ
る。図１において、１は金属めっき放熱エリア、２は半
導体素子、３は金属めっき放熱パターン、４は半導体キ
ャリア基板、５は電極パッド、６はバンプ、７はキャリ
アの電極、８は半田或いは導電性接着剤、９はエポキシ
系封止樹脂、１０はエポキシ系マークインク、１１は外
部端子、１２は金属配線である。DESCRIPTION OF THE PREFERRED EMBODIMENTS A reference example will be described with reference to FIGS. FIG. 1 is a sectional view of a semiconductor device of a reference example . In FIG. 1, 1 is a metal plating heat radiation area, 2 is a semiconductor element, 3 is a metal plating heat radiation pattern, 4 is a semiconductor carrier substrate, 5 is an electrode pad, 6 is a bump, 7 is a carrier electrode, 8 is solder or conductive. An adhesive, 9 is an epoxy sealing resin, 10 is an epoxy mark ink, 11 is an external terminal, and 12 is a metal wiring.
【００１１】この半導体装置は、半導体素子２と、半導
体素子２を支持しかつ半導体素子２からの熱放散性を向
上させた半導体キャリア基板４とを備えている。半導体
素子２は、電極パッド５にバンプ６が形成されている。
半導体キャリア基板４は、支持体であるセラミックを絶
縁基体とした多層回路基板より成り、その底面に格子状
に配列された外部端子１１を有し、上面に複数の電極７
と金属配線１２を有する。電極７と外部端子１１とは半
導体キャリア基板４内に形成されたビア（図示せず）に
より内部に接続されている。金属配線１２は内層に接続
するためのものである。また、半導体キャリア基板４の
上面の複数の電極７、配線１２以外の部分に、表面外周
部にＣｕ等の熱伝導性が良好な金属メッキ放熱エリア１
と、半導体素子２の実装領域内側から金属めっき放熱エ
リア１へ導くもう一つの金属めっき放熱パターン３とが
設けてある。金属めっき放熱エリア１に形成した金属め
っき放熱層の厚みは、半導体素子２の厚みと同等以下で
設計する。This semiconductor device comprises a semiconductor element 2 and a semiconductor carrier substrate 4 supporting the semiconductor element 2 and improving the heat dissipation from the semiconductor element 2. In the semiconductor element 2, bumps 6 are formed on the electrode pads 5.
The semiconductor carrier substrate 4 is composed of a multi-layer circuit substrate having a ceramic as an insulating base as a support, has external terminals 11 arranged in a grid pattern on its bottom surface, and has a plurality of electrodes 7 on its top surface.
And metal wiring 12. The electrode 7 and the external terminal 11 are internally connected by a via (not shown) formed in the semiconductor carrier substrate 4. The metal wiring 12 is for connecting to the inner layer. In addition, on the upper surface of the semiconductor carrier substrate 4, except for the plurality of electrodes 7 and the wiring 12, the metal plating heat dissipation area 1 having good thermal conductivity such as Cu on the outer peripheral surface of the surface.
And another metal plating heat radiation pattern 3 which is guided from the inside of the mounting area of the semiconductor element 2 to the metal plating heat radiation area 1. The thickness of the metal plating heat dissipation layer formed in the metal plating heat dissipation area 1 is designed to be equal to or less than the thickness of the semiconductor element 2.
【００１２】製造時において、半導体素子２はその主面
側を下にして半導体キャリア基板４に接続される。すな
わち、半導体素子２上に形成されたバンプ６と半導体キ
ャリア基板４上の複数の電極７とが半田或いは導電性接
着剤８等により接続されている。そして、接続された半
導体素子２と半導体キャリア基板４との隙間にはエポキ
シ系の封止樹脂９が充填されている。製品状態として
は、半導体素子２の裏面の露出面にエポキシ系のマーク
インク１０で品番や密番等が捺印されている半導体装置
である。At the time of manufacture, the semiconductor element 2 is connected to the semiconductor carrier substrate 4 with its main surface side facing down. That is, the bumps 6 formed on the semiconductor element 2 and the plurality of electrodes 7 on the semiconductor carrier substrate 4 are connected by solder or a conductive adhesive 8. An epoxy-based sealing resin 9 is filled in the gap between the connected semiconductor element 2 and semiconductor carrier substrate 4. As a product state, the semiconductor device is a semiconductor device in which the exposed part of the back surface of the semiconductor element 2 is stamped with the epoxy mark ink 10 such as a product number and a serial number.
【００１３】図２は参考例の半導体装置の平面図であ
る。図２に示すように、金属めっき放熱エリア１と金属
めっき放熱パターン３を設けた半導体キャリア基板４上
に、半導体素子２がフリップチップ実装されており、半
導体素子２の裏面が露出しているものである。以上のよ
うに参考例によれば、フリップチップで実装した半導体
素子２を支持する半導体キャリア基板４の上面に、熱伝
導性が良好な金属めっき放熱層を形成したことから、動
作時に発熱する半導体素子からの熱をプリント実装基板
へ効率良く放散させることができ、熱抵抗の低い半導体
装置を実現できる。FIG. 2 is a plan view of the semiconductor device of the reference example . As shown in FIG. 2, the metal plating heat dissipation area 1 and the metal
The semiconductor element 2 is flip-chip mounted on the semiconductor carrier substrate 4 provided with the plating heat dissipation pattern 3, and the back surface of the semiconductor element 2 is exposed. As described above, according to the reference example , since the metal-plated heat dissipation layer having good thermal conductivity is formed on the upper surface of the semiconductor carrier substrate 4 that supports the semiconductor element 2 mounted by flip chip, a semiconductor that generates heat during operation is formed. The heat from the element can be efficiently dissipated to the printed circuit board, and a semiconductor device with low thermal resistance can be realized.
【００１４】また、このように、金属めっき放熱層の厚
みは、半導体素子２の厚みと同等以下であるので、半導
体装置の薄型化が実現できる。また、金属めっき放熱層
の表面を波形や凹凸状に形成することにより、表面積が
大きくなり、放熱性の向上を図ることができる。図３〜
図５はこの発明の実施の形態を示す。なお、同様の部材
には同一符号を付してその説明を省略する。Further, since the thickness of the metal plating heat dissipation layer is equal to or less than the thickness of the semiconductor element 2, the semiconductor device can be thinned. Further, by forming the surface of the metal-plated heat dissipation layer in a corrugated or uneven shape, the surface area is increased and heat dissipation can be improved. Figure 3-
Figure 5 shows a form of implementation of the present invention. The same members are designated by the same reference numerals and the description thereof will be omitted.
【００１５】図３はこの発明の第１の実施の形態の半導
体装置を示す断面図である。この実施の形態では、金属
めっき放熱エリア１に形成された金属めっき放熱層の外
周部１ａを半導体素子２の上面レベルまで形成してあ
る。この場合、外周部１ａの層上面に凹凸が形成してあ
る。そして、金属めっき放熱エリア１を形成した半導体
キャリア基板４とフリップチップ実装された半導体素子
２との隙間にエポキシ系の封止樹脂９を塗布させ、金属
めっき放熱エリア１の外周部１ａの層上面と半導体素子
２の上面までエポキシ系封止樹脂９が充填被覆されてい
る。以上のようにこの実施の形態によれば、金属めっき
放熱層の体積の増加および外周部１ａの層上面の凹凸に
よりさらに放熱性が向上する。また、金属めっき放熱層
の外周部１ａと半導体素子２の上面が面一になっている
ので後述の放熱板の取付けが可能になる。FIG. 3 is a sectional view showing a semiconductor device according to the first embodiment of the present invention. In this embodiment, the outer peripheral portion 1a of the metal plating heat dissipation layer formed in the metal plating heat dissipation area 1 is formed up to the upper surface level of the semiconductor element 2. In this case, irregularities are formed on the upper surface of the layer of the outer peripheral portion 1a. Then, epoxy-based encapsulating resin 9 is applied in a gap between the semiconductor carrier substrate 4 having the metal plating heat radiation area 1 formed thereon and the semiconductor element 2 mounted by flip-chip mounting, and the upper surface of the layer of the outer peripheral portion 1 a of the metal plating heat radiation area 1 is applied. The epoxy-based encapsulating resin 9 is filled and coated on the upper surface of the semiconductor element 2. As described above, according to this embodiment, the heat dissipation is further improved by the increase of the volume of the metal plating heat dissipation layer and the unevenness of the layer upper surface of the outer peripheral portion 1a. Further, since the outer peripheral portion 1a of the metal plated heat dissipation layer and the upper surface of the semiconductor element 2 are flush with each other, a heat dissipation plate described later can be attached.
【００１６】図４はこの発明の第２の実施の形態の半導
体装置を示す断面図、図５はこの発明の第２の実施の形
態の半導体装置の変形例である。この実施の形態では、
図４に示すように、金属めっき放熱エリア１に形成され
た金属めっき放熱層の形状は第１の実施の形態と同様で
ある。また、金属めっき放熱エリア１の上面と半導体素
子２の上面とを熱伝導性が良好で且つ軽量化が図れる金
属等の放熱板１３で接触させ、その隙間には放熱用の接
着材１４を塗布して接合させている。なお、放熱板１３
を取り付ける場合は、放熱用の接着剤１４を用いること
から、金属めっき放熱層の上面部の形状は、凹凸形状で
も図５に示すようなフラット形状でも取り付け可能であ
る。また、放熱板１３の取り付けにより、半導体素子２
の裏面への捺印は、放熱板１３上面に捺印することがで
きるものである。以上のようにこの実施の形態によれ
ば、金属めっき放熱エリア１に形成した金属めっき放熱
層の上面に接し、かつ半導体素子２の裏面と接触させて
放熱板１３を取付けたので、半導体素子裏面のみでな
く、半導体素子２と金属めっき放熱層とを接触させるこ
とにより、発熱する半導体素子２からの熱を効率良く放
散させることができ、優れた放熱効果を有する。[0016] Figure 4 is a sectional view showing a semiconductor device of the second embodiment of the present invention, FIG 5 is a modification of the semiconductor device of the second embodiment of the present invention. In this embodiment,
As shown in FIG. 4, the shape of the metal plating heat dissipation layer formed in the metal plating heat dissipation area 1 is the same as that of the first embodiment. Further, the upper surface of the metal plating heat radiation area 1 and the upper surface of the semiconductor element 2 are brought into contact with each other by a heat radiation plate 13 made of metal or the like which has good thermal conductivity and can be reduced in weight, and an adhesive 14 for heat radiation is applied to the gap. And then joined. The heat sink 13
Since the adhesive 14 for heat dissipation is used when attaching, the shape of the upper surface portion of the metal plating heat dissipation layer can be an uneven shape or a flat shape as shown in FIG. Further, by mounting the heat dissipation plate 13, the semiconductor element 2
The marking on the back surface of can be done on the upper surface of the heat dissipation plate 13. As described above, according to this embodiment, since the heat dissipation plate 13 is attached in contact with the upper surface of the metal plating heat dissipation layer formed in the metal plating heat dissipation area 1 and in contact with the back surface of the semiconductor element 2, the semiconductor element back surface is attached. Not only that, by bringing the semiconductor element 2 and the metal plating heat dissipation layer into contact with each other, the heat generated from the semiconductor element 2 can be efficiently dissipated, and an excellent heat dissipation effect is provided.
【００１７】なお、図１において、金属めっき放熱エリ
ア１に形成した金属めっき放熱層の断面形状を、波形ま
たは凹凸形として表面積を大きくしてもよい。また、図
３および図４において、金属めっき放熱エリア１の外周
部１ａの層上面を凹凸形としたが波形にしてもよい。In FIG. 1, the cross-sectional shape of the metal plating heat dissipation layer formed in the metal plating heat dissipation area 1 may be corrugated or uneven to increase the surface area. Further, in FIG. 3 and FIG. 4, the layer upper surface of the outer peripheral portion 1a of the metal plating heat radiation area 1 has an uneven shape, but may have a corrugated shape.
【００１８】[0018]
【発明の効果】この発明の半導体装置によれば、半導体
キャリア基板の上面の複数の電極と配線以外の部分に、
熱伝導性が良好な金属をめっきした金属めっき放熱エリ
アと、半導体素子実装エリアから金属めっき放熱エリア
に導き、外周部が前記半導体チップの上面レベルまで形
成された金属めっき放熱パターンとを設けたので、動作
時に発熱する半導体素子からの熱をプリント実装基板へ
効率良く放散させることができ、熱抵抗の低い半導体装
置を実現できる。金属めっき放熱パターンの外周部の金
属めっき放熱層の体積の増加によりさらに放熱性が向上
する。また、金属めっき放熱パターンの外周部と半導体
素子の上面が面一になっているので放熱板の取付けが可
能になる。According to the semiconductor device of the present invention, in the portion other than the plurality of electrodes and the wiring on the upper surface of the semiconductor carrier substrate,
Since a metal plating heat dissipation area plated with a metal having good thermal conductivity and a metal plating heat dissipation pattern which is led from the semiconductor element mounting area to the metal plating heat dissipation area and whose outer peripheral portion is formed to the upper surface level of the semiconductor chip are provided. The heat generated from the semiconductor element during operation can be efficiently dissipated to the printed circuit board, and a semiconductor device with low thermal resistance can be realized. The heat dissipation is further improved by increasing the volume of the metal plating heat dissipation layer on the outer periphery of the metal plating heat dissipation pattern. Further, since the outer peripheral portion of the metal plating heat radiation pattern is flush with the upper surface of the semiconductor element, the heat radiation plate can be attached.
【００１９】[0019]
【００２０】請求項２では、金属めっき放熱エリアに形
成した金属めっき放熱層の断面形状を、波形や凹凸形と
して表面積を大きくしたので、放熱性の向上を図ること
ができる。請求項３では、金属めっき放熱エリアに形成
した金属めっき放熱層の上面に接し、かつ半導体素子の
裏面と接触させて放熱板を取付けたので、半導体素子裏
面のみでなく、半導体素子と金属めっき放熱層とを接触
させることにより、発熱する半導体素子からの熱を効率
良く放散させることができ、優れた放熱効果を有する。In the second aspect , since the metal plating heat dissipation layer formed in the metal plating heat dissipation area has a corrugated shape or a corrugated shape to increase the surface area, heat dissipation can be improved. In the third aspect , since the heat dissipation plate is attached in contact with the upper surface of the metal plating heat dissipation layer formed in the metal plating heat dissipation area and in contact with the back surface of the semiconductor element, the semiconductor element and the metal plating heat dissipation are not limited to the back surface of the semiconductor element. By bringing the layer into contact with the layer, heat generated from the semiconductor element can be efficiently dissipated, and an excellent heat dissipation effect can be obtained.
【図１】参考例の半導体装置を示す断面図である。FIG. 1 is a cross-sectional view showing a semiconductor device of a reference example .
【図２】参考例の半導体装置を示す平面図である。FIG. 2 is a plan view showing a semiconductor device of a reference example .
【図３】この発明の第１の実施の形態の半導体装置を示
す断面図である。FIG. 3 is a sectional view showing a semiconductor device according to a first embodiment of the present invention.
【図４】この発明の第２実施の形態の半導体装置を示す
断面図である。FIG. 4 is a sectional view showing a semiconductor device according to a second embodiment of the present invention.
【図５】この発明の第２の実施の形態の半導体装置の変
形例を示す断面図である。FIG. 5 is a sectional view showing a modification of the semiconductor device according to the second embodiment of the present invention.
【図６】従来例の半導体装置を示す断面図である。FIG. 6 is a sectional view showing a conventional semiconductor device.
【図７】従来例の半導体装置を示す平面図である。FIG. 7 is a plan view showing a conventional semiconductor device.
１ 金属めっき放熱エリア ２ 半導体素子 ３ 金属めっき放熱パターン ４ 半導体キャリア基板 ５ 電極パッド ６ バンプ ７ キャリアの電極 ８ 半田或いは導電性接着剤 ９ エポキシ系封止樹脂 １０ エポキシ系マークインク １１ 外部端子 １２ 金属配線 １３ 放熱板 １４ 放熱用の接着材 1 Metal plating heat dissipation area 2 Semiconductor element 3 Metal plating heat radiation pattern 4 Semiconductor carrier substrate 5 electrode pads 6 bumps 7 Carrier electrodes 8 Solder or conductive adhesive 9 Epoxy type sealing resin 10 Epoxy mark ink 11 External terminal 12 Metal wiring 13 Heat sink 14 Heat dissipation adhesive
Claims (3)
リアにフリップチップで実装した半導体素子を支持し、
前記半導体キャリア基板の上面に複数の電極と配線を形
成した半導体装置であって、前記半導体キャリア基板の
上面の前記複数の電極と配線以外の部分に、熱伝導性が
良好な金属をめっきした金属めっき放熱エリアと、前記
半導体素子実装エリアから前記金属めっき放熱エリアに
導き、外周部が前記半導体チップの上面レベルまで形成
された金属めっき放熱パターンとを設けたことを特徴と
する半導体装置。1. A semiconductor element mounted by flip chip is supported on a semiconductor element mounting area of a semiconductor carrier substrate,
A semiconductor device in which a plurality of electrodes and wirings are formed on the upper surface of the semiconductor carrier substrate, wherein a metal other than the plurality of electrodes and wirings on the upper surface of the semiconductor carrier substrate is plated with a metal having good thermal conductivity. A semiconductor device comprising: a plating heat radiation area; and a metal plating heat radiation pattern which is guided from the semiconductor element mounting area to the metal plating heat radiation area and whose outer peripheral portion is formed to the upper surface level of the semiconductor chip.
っき放熱層の断面形状を、波形または凹凸形として表面
積を大きくした請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the metal plating heat dissipation layer formed in the metal plating heat dissipation area has a corrugated or concave-convex cross-section to have a large surface area.
っき放熱層の上面に接し、かつ半導体素子の裏面と接触
させて放熱板を取付けた請求項１または２記載の半導体
装置。3. The semiconductor device according to claim 1, wherein the heat dissipation plate is attached in contact with the top surface of the metal plating heat dissipation layer formed in the metal plating heat dissipation area and in contact with the back surface of the semiconductor element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27341198A JP3519285B2 (en) | 1998-09-28 | 1998-09-28 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27341198A JP3519285B2 (en) | 1998-09-28 | 1998-09-28 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000106410A JP2000106410A (en) | 2000-04-11 |
| JP3519285B2 true JP3519285B2 (en) | 2004-04-12 |
Family
ID=17527525
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27341198A Expired - Fee Related JP3519285B2 (en) | 1998-09-28 | 1998-09-28 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3519285B2 (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW497371B (en) * | 2000-10-05 | 2002-08-01 | Sanyo Electric Co | Semiconductor device and semiconductor module |
| DE10051159C2 (en) * | 2000-10-16 | 2002-09-19 | Osram Opto Semiconductors Gmbh | LED module, e.g. White light source |
| DE10297766T5 (en) * | 2002-07-30 | 2005-09-29 | Infineon Technologies Ag | Heat dissipation device for integrated circuits |
| JP4390541B2 (en) | 2003-02-03 | 2009-12-24 | Ｎｅｃエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
| JP5126219B2 (en) | 2007-03-27 | 2013-01-23 | 富士通株式会社 | Semiconductor component and method for manufacturing semiconductor component |
| JP2010103244A (en) | 2008-10-22 | 2010-05-06 | Sony Corp | Semiconductor device, and method of manufacturing the same |
| JP2011222818A (en) * | 2010-04-12 | 2011-11-04 | Yokogawa Electric Corp | Cooling structure for semiconductor device |
| JP2012182376A (en) * | 2011-03-02 | 2012-09-20 | Stanley Electric Co Ltd | Wavelength conversion member and light source device |
-
1998
- 1998-09-28 JP JP27341198A patent/JP3519285B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2000106410A (en) | 2000-04-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2755252B2 (en) | Semiconductor device package and semiconductor device | |
| TWI529878B (en) | Hybrid thermal interface material for ic packages with integrated heat spreader | |
| US5521435A (en) | Semiconductor device and a fabrication process thereof | |
| WO2006132151A1 (en) | Interposer and semiconductor device | |
| JP2003068931A (en) | Semiconductor package and its manufacturing method | |
| JPH0917919A (en) | Semiconductor device | |
| US7176563B2 (en) | Electronically grounded heat spreader | |
| JP4494249B2 (en) | Semiconductor device | |
| JP3519285B2 (en) | Semiconductor device | |
| US20020063331A1 (en) | Film carrier semiconductor device | |
| JPH09199629A (en) | Semiconductor device | |
| KR20030045950A (en) | Multi chip package comprising heat sinks | |
| JP3587043B2 (en) | BGA type semiconductor device and stiffener used for the device | |
| GB2301937A (en) | IC package with a ball grid array on a single layer ceramic substrate | |
| JP3549316B2 (en) | Wiring board | |
| KR100533763B1 (en) | semiconductor package | |
| JPH09326450A (en) | Semiconductor device and its manufacture | |
| TW417265B (en) | Low-cost surface-mount compatible land-grid array (lga) chips cale package (csp) for packaging solder-bumped flip chips | |
| US6291893B1 (en) | Power semiconductor device for “flip-chip” connections | |
| JPH08274214A (en) | Semiconductor device | |
| US7190056B2 (en) | Thermally enhanced component interposer: finger and net structures | |
| JP4193702B2 (en) | Semiconductor package mounting structure | |
| JP2004087700A (en) | Semiconductor device and its manufacturing method | |
| JP3024596B2 (en) | BGA type semiconductor device using film carrier tape | |
| JPH0897336A (en) | Semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20040127 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20040128 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080206 Year of fee payment: 4 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090206 Year of fee payment: 5 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100206 Year of fee payment: 6 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100206 Year of fee payment: 6 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110206 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120206 Year of fee payment: 8 |
|
| LAPS | Cancellation because of no payment of annual fees |