JP2014013836A - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
JP2014013836A
JP2014013836A JP2012150755A JP2012150755A JP2014013836A JP 2014013836 A JP2014013836 A JP 2014013836A JP 2012150755 A JP2012150755 A JP 2012150755A JP 2012150755 A JP2012150755 A JP 2012150755A JP 2014013836 A JP2014013836 A JP 2014013836A
Authority
JP
Japan
Prior art keywords
semiconductor chip
resin
semiconductor device
wiring board
low
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2012150755A
Other languages
Japanese (ja)
Inventor
Sensho Usami
宣丞 宇佐美
Koji Hosokawa
浩二 細川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
PS4 Luxco SARL
Original Assignee
PS4 Luxco SARL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by PS4 Luxco SARL filed Critical PS4 Luxco SARL
Priority to JP2012150755A priority Critical patent/JP2014013836A/en
Priority to US13/933,318 priority patent/US20140008775A1/en
Publication of JP2014013836A publication Critical patent/JP2014013836A/en
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/06—Containers; Seals characterised by the material of the container or its electrical properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which reduces warpage of the semiconductor device at low costs in a short development period without inhibiting the thickness reduction.SOLUTION: A semiconductor device 100 includes: a wiring board 1; a semiconductor chip 2 mounted on one surface of the wiring board 1; a sealing resin 7 which is provided on one surface of the wiring board 1 so as to cover the semiconductor chip 2; and a low elastic resin 8 which has the elastic modulus lower than the elastic modulus of the sealing resin 7 and is disposed between the wiring board 1 and the sealing resin 7.

Description

本発明は、半導体装置に関し、特に、ＢＧＡ（Ball Grid Array）型の半導体装置に関する。   The present invention relates to a semiconductor device, and more particularly to a BGA (Ball Grid Array) type semiconductor device.

一般的なＢＧＡ（Ball Grid Array）型半導体装置は、配線基板に搭載された半導体チップと、半導体チップの電極パッドと配線基板の接続パッドとを電気的に接続するボンディングワイヤを有する。   A general BGA (Ball Grid Array) type semiconductor device has a semiconductor chip mounted on a wiring board, and a bonding wire that electrically connects an electrode pad of the semiconductor chip and a connection pad of the wiring board.

これに関連する技術として、例えば、特開２０１１−５４７７１号公報（特許文献１）がある。特許文献１には、配線基板上に半導体チップを搭載し、半導体チップを覆うように配線基板上に封止樹脂を配置したＢＧＡ型の半導体装置と、封止後に封止樹脂に荷重をかけながらベークすることで反りを低減する技術が開示されている。   For example, JP 2011-54771 A (Patent Document 1) is a related technology. In Patent Document 1, a semiconductor chip is mounted on a wiring board and a sealing resin is disposed on the wiring board so as to cover the semiconductor chip, and a load is applied to the sealing resin after sealing. A technique for reducing warpage by baking is disclosed.

上記ＢＧＡ型の半導体装置では、配線基板、半導体チップ及び封止樹脂は、それぞれ異なる材料から構成されているため、半導体装置に反りが発生する。上記特許文献１のように、封止後、封止樹脂に荷重をかけながらベークすることで、ある程度の反り量を減らすことは可能であるが、反り量が大きい場合には荷重ベークだけで実装に問題ないレベルまで反りを減らすことができない恐れがある。   In the BGA type semiconductor device, since the wiring board, the semiconductor chip, and the sealing resin are made of different materials, the semiconductor device is warped. As described in Patent Document 1, it is possible to reduce the amount of warping to some extent by baking while applying a load to the sealing resin after sealing, but when the amount of warping is large, mounting is performed only by load baking. There is a risk that the warp cannot be reduced to a level where there is no problem.

そのため、開発段階で、配線基板や封止樹脂の材料変更により半導体装置の反りを調整する必要がある。この半導体装置の反りの調整には、例えば、配線基板や封止樹脂の材料変更による試作を繰り返すために、開発期間が延び、半導体装置のコストアップにもつながる。   Therefore, it is necessary to adjust the warpage of the semiconductor device at the development stage by changing the material of the wiring board or the sealing resin. For adjusting the warpage of the semiconductor device, for example, the trial period by changing the material of the wiring board or the sealing resin is repeated, so that the development period is extended and the cost of the semiconductor device is increased.

そこで、配線基板と半導体素子（半導体チップ）との接続部分の低応力化のために、半導体素子を低弾性樹脂で覆う技術がある（特開２００６−１２０９３５号公報（特許文献２）参照）。   Therefore, there is a technique for covering the semiconductor element with a low elastic resin in order to reduce the stress at the connection portion between the wiring board and the semiconductor element (semiconductor chip) (see JP 2006-120935 A (Patent Document 2)).

しかし、特許文献２のように、半導体チップ上に低弾性樹脂を配置すると、低弾性樹脂にはマークを形成するのが困難であるため、低弾性樹脂の上にも封止樹脂を配置する必要が生じる。そのため、半導体チップ上の封止樹脂の厚さが大きくなり、半導体装置の薄型化を阻害するという問題がある。   However, as in Patent Document 2, if a low-elasticity resin is arranged on a semiconductor chip, it is difficult to form a mark on the low-elasticity resin. Therefore, it is necessary to arrange a sealing resin on the low-elasticity resin. Occurs. For this reason, there is a problem that the thickness of the sealing resin on the semiconductor chip becomes large and obstructs the thinning of the semiconductor device.

特開２０１１−５４７７１号公報JP 2011-54771 A 特開２００６−１２０９３５号公報JP 2006-120935 A

本発明は、短い開発期間かつ低コストで薄型化を阻害することなく半導体装置の反りを低減することが可能な半導体装置を提供する。   The present invention provides a semiconductor device capable of reducing the warpage of the semiconductor device without impairing the thinning with a short development period and low cost.

本発明の一態様に係る半導体装置は、
配線基板と、 前記配線基板の一面に搭載された半導体チップと、
前記半導体チップを覆うように、前記配線基板の前記一面に設けられた封止樹脂と、 前記封止樹脂の弾性率より低い弾性率を有し、前記配線基板と前記封止樹脂の間に配置された低弾性樹脂とを有することを特徴とする。 A semiconductor device according to one embodiment of the present invention includes:
A wiring board; and a semiconductor chip mounted on one surface of the wiring board;
A sealing resin provided on the one surface of the wiring substrate so as to cover the semiconductor chip; and an elastic modulus lower than an elastic modulus of the sealing resin, and disposed between the wiring substrate and the sealing resin. And having a low elasticity resin.

また、本発明の他の態様に係る半導体装置は、
配線基板と、 前記配線基板の一面に搭載された第１の半導体チップと、
前記第１の半導体チップからオーバーハングするように前記第１の半導体チップ上に積層された第２の半導体チップと、 前記第１の半導体チップと前記第２の半導体チップを覆うように、前記配線基板の前記一面に設けられた封止樹脂と、 前記封止樹脂の弾性率より低い弾性率を有し、前記配線基板と前記封止樹脂の間に配置された低弾性樹脂とを有し、
前記第２の半導体チップのオーバーハング部が、前記低弾性樹脂の上方に位置することを特徴とする。 In addition, a semiconductor device according to another aspect of the present invention is provided.
A wiring board; a first semiconductor chip mounted on one surface of the wiring board;
A second semiconductor chip stacked on the first semiconductor chip so as to overhang from the first semiconductor chip; and the wiring so as to cover the first semiconductor chip and the second semiconductor chip A sealing resin provided on the one surface of the substrate, and an elastic modulus lower than an elastic modulus of the sealing resin, and a low elastic resin disposed between the wiring substrate and the sealing resin,
The overhang portion of the second semiconductor chip is located above the low-elasticity resin.

本発明によれば、短い開発期間かつ低コストで薄型化を阻害することなく半導体装置の反りを低減することができる。   According to the present invention, it is possible to reduce warpage of a semiconductor device without hindering thinning in a short development period and at low cost.

本発明の第１の実施形態に係る半導体装置の概略構成を示す図であり、（ａ）は平面図であり、（ｂ）は（ａ）のＣ−Ｃ’断面図である。BRIEF DESCRIPTION OF THE DRAWINGS It is a figure which shows schematic structure of the semiconductor device which concerns on the 1st Embodiment of this invention, (a) is a top view, (b) is C-C 'sectional drawing of (a). 本発明の第１の実施形態に係る半導体装置の組立フローを示す断面図である。It is sectional drawing which shows the assembly flow of the semiconductor device which concerns on the 1st Embodiment of this invention. 本発明の第１の実施形態に係る半導体装置の変形例を示す断面図である。It is sectional drawing which shows the modification of the semiconductor device which concerns on the 1st Embodiment of this invention. 本発明の第２の実施形態に係る半導体装置の概略構成を示す図であり、（ａ）は平面図であり、（ｂ）は（ａ）のＡ−Ａ’断面図であり、（ｃ）は（ａ）のＢ−Ｂ’断面図である。It is a figure which shows schematic structure of the semiconductor device which concerns on the 2nd Embodiment of this invention, (a) is a top view, (b) is AA 'sectional drawing of (a), (c) FIG. 4B is a sectional view taken along line BB ′ in FIG. 本発明の第３の実施形態に係る半導体装置の概略構成を示す図であり、（ａ）は平面図であり、（ｂ）は（ａ）のＤ−Ｄ’断面図である。It is a figure which shows schematic structure of the semiconductor device which concerns on the 3rd Embodiment of this invention, (a) is a top view, (b) is D-D 'sectional drawing of (a). 本発明の第４の実施形態に係る半導体装置の概略構成を示す図であり、（ａ）は平面図であり、（ｂ）は（ａ）のＥ−Ｅ’断面図であり、（ｃ）は（ａ）のＦ−Ｆ’断面図である。It is a figure which shows schematic structure of the semiconductor device which concerns on the 4th Embodiment of this invention, (a) is a top view, (b) is EE 'sectional drawing of (a), (c) FIG. 4 is a sectional view taken along line FF ′ in FIG. 本発明の第５の実施形態に係る半導体装置の概略構成を示す図であり、（ａ）は平面図であり、（ｂ）は（ａ）のＧ−Ｇ’断面図であり、（ｃ）は（ａ）のＨ−Ｈ’断面図である。It is a figure which shows schematic structure of the semiconductor device which concerns on the 5th Embodiment of this invention, (a) is a top view, (b) is GG 'sectional drawing of (a), (c) FIG. 6 is a cross-sectional view taken along line HH ′ of FIG.

以下、図面を参照しながら、本発明の実施の形態について詳細に説明する。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

（第１の実施形態） 図１は、本発明の第１の実施形態に係る半導体装置の概略構成を示す図であり、（ａ）は平面図であり、（ｂ）は（ａ）のＣ−Ｃ’断面図である。   First Embodiment FIG. 1 is a diagram showing a schematic configuration of a semiconductor device according to a first embodiment of the present invention, (a) is a plan view, and (b) is a diagram C of (a). It is -C 'sectional drawing.

第１の実施形態に係る半導体装置１００では、図１に示すように、配線基板１の一面上に半導体チップ２が接着部材３を介して搭載されている。配線基板１は、例えば、ガラスエポキシ基材からなる配線基板である。   In the semiconductor device 100 according to the first embodiment, as shown in FIG. 1, the semiconductor chip 2 is mounted on one surface of the wiring board 1 via an adhesive member 3. The wiring board 1 is a wiring board made of, for example, a glass epoxy base material.

半導体チップ２上の周辺には、電極パッド４が配置されている。半導体チップ２の電極パッド４は、ワイヤ５によって配線基板１の接続パッド６に電気的に接続されている。配線基板１の一面には封止樹脂７が形成されており、半導体チップ２及びワイヤ５は封止樹脂７で覆われている。なお、配線基板１の一面にはソルダーレジソト膜１１が形成されている。一方、配線基板１の他面のランド９上には、はんだボール１０が搭載されている。   Electrode pads 4 are arranged around the semiconductor chip 2. The electrode pads 4 of the semiconductor chip 2 are electrically connected to the connection pads 6 of the wiring board 1 by wires 5. A sealing resin 7 is formed on one surface of the wiring substrate 1, and the semiconductor chip 2 and the wires 5 are covered with the sealing resin 7. Note that a solder resist film 11 is formed on one surface of the wiring board 1. On the other hand, solder balls 10 are mounted on the lands 9 on the other surface of the wiring board 1.

第１の実施形態に係る半導体装置１００では、図１（ｂ）に示すように、配線基板１と封止樹脂７との間に、低弾性樹脂８が配置されている。低弾性樹脂８は、封止樹脂７の弾性率よりも小さい弾性率を有する材料、例えばシリコーン樹脂やアンダーフィルで形成されている。低弾性樹脂８は、図１（ａ）に示すように、半導体チップ２の搭載位置の外側に略枠状に形成されている。   In the semiconductor device 100 according to the first embodiment, as shown in FIG. 1B, a low elastic resin 8 is disposed between the wiring substrate 1 and the sealing resin 7. The low elastic resin 8 is formed of a material having an elastic modulus smaller than that of the sealing resin 7, for example, a silicone resin or an underfill. The low-elasticity resin 8 is formed in a substantially frame shape outside the mounting position of the semiconductor chip 2 as shown in FIG.

このように、配線基板１と封止樹脂７の間に、封止樹脂７の弾性率より小さい弾性率を有する低弾性樹脂８を配置した。これにより、低弾性樹脂８が、配線基板１と封止樹脂７の間の緩衝材となり、封止樹脂７の硬化収縮による影響を小さくし、半導体装置１００の反りを低減できる。さらに、開発段階での反りの調整も容易になり、開発期間の短縮及び開発コストの低減を図ることができる。   As described above, the low elastic resin 8 having an elastic modulus smaller than the elastic modulus of the sealing resin 7 is disposed between the wiring substrate 1 and the sealing resin 7. Thereby, the low elastic resin 8 becomes a buffer material between the wiring substrate 1 and the sealing resin 7, and the influence of the curing shrinkage of the sealing resin 7 can be reduced, and the warpage of the semiconductor device 100 can be reduced. Furthermore, it is easy to adjust the warpage at the development stage, and the development period can be shortened and the development cost can be reduced.

次に、図２を参照して、第１の実施形態に係る半導体装置の製造方法について図１をも使用して説明する。ここで、図２は、第１の実施形態に係る半導体装置１００の組立フローを示す断面図である。   Next, with reference to FIG. 2, the manufacturing method of the semiconductor device according to the first embodiment will be described with reference to FIG. Here, FIG. 2 is a sectional view showing an assembly flow of the semiconductor device 100 according to the first embodiment.

まず、図２（ａ）に示すように、配線基板１が準備される。配線基板１は絶縁基材１２で形成されており、一面に絶縁膜１３と接続パッド６が形成されている。一方、配線基板１の他面には、絶縁膜１４とランド９が形成されている。さらに、配線基板１にはダイシングライン１５が設けられている。   First, as shown in FIG. 2A, a wiring board 1 is prepared. The wiring substrate 1 is formed of an insulating base material 12, and an insulating film 13 and connection pads 6 are formed on one surface. On the other hand, an insulating film 14 and a land 9 are formed on the other surface of the wiring board 1. Further, the wiring board 1 is provided with a dicing line 15.

そして、半導体チップ２の搭載前に、図示しない塗布装置のディスペンサーによって、配線基板１のチップ搭載位置の外側に枠状に描画するように低弾性樹脂８を供給する。次に、配線基板１に供給された低弾性樹脂８を所定の温度でキュアすることで硬化させる。   Then, before the semiconductor chip 2 is mounted, the low-elasticity resin 8 is supplied by a dispenser of a coating apparatus (not shown) so as to draw a frame shape outside the chip mounting position of the wiring substrate 1. Next, the low elastic resin 8 supplied to the wiring board 1 is cured by curing at a predetermined temperature.

このように、配線基板１の周囲に略枠状に低弾性樹脂８を配置したことで、薄い配線基板１の剛性を高めることができ、薄い配線基板１のハンドリング性を向上できる。   Thus, by arranging the low-elasticity resin 8 in a substantially frame shape around the wiring board 1, the rigidity of the thin wiring board 1 can be increased, and the handling property of the thin wiring board 1 can be improved.

次に、図２（ｂ）に示すように、裏面に接着部材３が形成された半導体チップ２が配線基板１に搭載される。そして、半導体チップ２の電極パッド４と配線基板１の接続パッド６とをワイヤ５により電気的に接続する。   Next, as shown in FIG. 2B, the semiconductor chip 2 having the adhesive member 3 formed on the back surface is mounted on the wiring substrate 1. Then, the electrode pads 4 of the semiconductor chip 2 and the connection pads 6 of the wiring board 1 are electrically connected by wires 5.

ここで、ワイヤ５は例えばＡｕ等からなり、図示しないワイヤボンディング装置により、溶融され先端にボールが形成されたワイヤ５を半導体チップ２の電極パッド４上に超音波熱圧着することで接続し、その後、所定のループ形状を描き、ワイヤ５の後端を対応する接続パッド６上に超音波熱圧着することで結線される。   Here, the wire 5 is made of, for example, Au or the like, and is connected by ultrasonic thermocompression bonding on the electrode pad 4 of the semiconductor chip 2 with the wire 5 melted and formed with a ball at the tip by a wire bonding apparatus (not shown). After that, a predetermined loop shape is drawn, and the rear end of the wire 5 is connected to the corresponding connection pad 6 by ultrasonic thermocompression bonding.

次に、図２（ｃ）に示すように、一括モールドすることで、配線基板１の一面上に封止樹脂７が形成される。封止樹脂２は、例えば、図示しないトランスファーモールド装置の上型と下型からなる成形金型で、配線基板２を型締めし、ゲートから上型と下型によって形成されたキャビティ内に熱硬化性のエポキシ樹脂を圧入させ、キャビティ内に充填された後、熱硬化させることで形成される。   Next, as shown in FIG. 2C, the sealing resin 7 is formed on one surface of the wiring substrate 1 by batch molding. The sealing resin 2 is, for example, a molding die composed of an upper mold and a lower mold of a transfer mold apparatus (not shown), and the wiring substrate 2 is clamped and thermally cured from the gate into a cavity formed by the upper mold and the lower mold. It is formed by press-fitting a functional epoxy resin, filling the cavity, and thermosetting.

次に、図２（ｄ）に示すように、配線基板１の他面のランド９上にはんだボール１０を搭載して外部端子（バンプ電極）を形成する。ボールマウント工程では、配線基板１上のランド９の配置に合わせて複数の吸着孔が形成された図示しない吸着機構を用いて、はんだボール１０を吸着孔に保持し、保持されたはんだボール１０にフラックスを転写形成し、配線基板１のランド９に一括搭載する。ボール搭載後、リフローすることで外部端子が形成される。   Next, as shown in FIG. 2D, the solder balls 10 are mounted on the lands 9 on the other surface of the wiring board 1 to form external terminals (bump electrodes). In the ball mounting process, the solder balls 10 are held in the suction holes by using a suction mechanism (not shown) in which a plurality of suction holes are formed in accordance with the arrangement of the lands 9 on the wiring board 1. The flux is transferred and mounted on the land 9 of the wiring board 1 at a time. After mounting the ball, external terminals are formed by reflowing.

次に、図２（ｅ）に示すように、外部端子の形成された配線基板１は、ダイシングライン１５で切断・分離し個片化する。基板ダイシングは、配線基板１の封止樹脂７をダイシングテープに接着し、ダイシングテープによって配線基板１を支持する。配線基板１を図示しないダイシングブレードにより縦横にダイシングライン１５を切断して配線基板１を個片化する。個片化完了後、ダイシングテープからピックアップすることで、図１に示すような半導体装置１００が得られる。   Next, as shown in FIG. 2E, the wiring board 1 on which the external terminals are formed is cut and separated by the dicing line 15 and separated into individual pieces. In substrate dicing, the sealing resin 7 of the wiring substrate 1 is bonded to a dicing tape, and the wiring substrate 1 is supported by the dicing tape. The wiring board 1 is cut into individual pieces by cutting the dicing lines 15 vertically and horizontally with a dicing blade (not shown). After completion of singulation, the semiconductor device 100 as shown in FIG. 1 is obtained by picking up from the dicing tape.

尚、薄い配線基板１のハンドリング性を向上するために、半導体チップ２の搭載前に低弾性樹脂８を供給するようにしたが、半導体チップ２の搭載後、或いは、ワイヤボンディング後に、低弾性樹脂８を供給しても良い。   In order to improve handling of the thin wiring board 1, the low elastic resin 8 is supplied before the semiconductor chip 2 is mounted. However, after the semiconductor chip 2 is mounted or after the wire bonding, the low elastic resin 8 is supplied. 8 may be supplied.

このように、第１の実施形態では、配線基板１と封止樹脂７の間に、封止樹脂７より低い弾性率を有する低弾性樹脂８を設けた。これにより、低弾性樹脂８が、封止樹脂７と配線基板１の間の緩衝材となり、封止後の半導体装置１００の反りを低減できる。   As described above, in the first embodiment, the low elastic resin 8 having an elastic modulus lower than that of the sealing resin 7 is provided between the wiring substrate 1 and the sealing resin 7. Thereby, the low elastic resin 8 becomes a buffer material between the sealing resin 7 and the wiring substrate 1, and the warpage of the semiconductor device 100 after sealing can be reduced.

さらに、トランスファーモールド装置により、封止樹脂を形成する場合には、ゲート側とエアベント側の製品領域で、フィラーの分布が異なってしまい、製品領域毎に反りにバラツキが生じる問題がある。しかし、第１の実施形態では、それぞれの製品領域の配線基板１と封止樹脂７の間に、封止樹脂７より低い弾性率を有する低弾性樹脂８を設けることで、製品領域毎のバラツキも低減できる。   Further, when the sealing resin is formed by the transfer mold apparatus, there is a problem that the distribution of the filler is different between the product region on the gate side and the air vent side, and the warp varies for each product region. However, in the first embodiment, by providing the low elastic resin 8 having an elastic modulus lower than that of the sealing resin 7 between the wiring substrate 1 and the sealing resin 7 in each product region, the variation for each product region is increased. Can also be reduced.

図３は、第１の実施形態に係る半導体装置１００の変形例を示す断面図である。   FIG. 3 is a cross-sectional view showing a modification of the semiconductor device 100 according to the first embodiment.

図３に示すように、低弾性樹脂８の幅を変更することで、配線基板１と封止樹脂７との接触する面積を変更し、半導体装置１００の反りを調整することもできる。例えば、反り量が大きい場合には、低弾性樹脂８の面積をさらに大きくすることで、配線基板１と封止樹脂７の接触する面積を小さくし、さらに反りを低減できる。   As shown in FIG. 3, by changing the width of the low elastic resin 8, the contact area between the wiring substrate 1 and the sealing resin 7 can be changed and the warpage of the semiconductor device 100 can be adjusted. For example, when the amount of warping is large, the area of the low elastic resin 8 is further increased to reduce the area where the wiring substrate 1 and the sealing resin 7 are in contact with each other, thereby further reducing warpage.

（第２の実施形態）
図４は、本発明の第２の実施形態に係る半導体装置２００の概略構成を示す断面図であり、（ａ）は平面図であり、（ｂ）は（ａ）のＡ−Ａ’断面図であり、（ｃ）は（ａ）のＢ−Ｂ’断面図である。 (Second Embodiment)
4A and 4B are cross-sectional views showing a schematic configuration of a semiconductor device 200 according to the second embodiment of the present invention, where FIG. 4A is a plan view and FIG. 4B is a cross-sectional view along AA ′ in FIG. (C) is a BB ′ sectional view of (a).

尚、説明の便宜上、図１に示す半導体装置１００と同じ構成要素には、同じ参照符号が付されている。ここで、図４において、参照符号５０は開口部を示している。   For convenience of explanation, the same reference numerals are assigned to the same components as those of the semiconductor device 100 shown in FIG. Here, in FIG. 4, reference numeral 50 indicates an opening.

第２の実施形態では、配線基板１に搭載される半導体チップ２が略長方形状であり、縦方向の半導体チップ２の端部と配線基板１の端部の間の領域と、横方向の半導体チップ２の端部と配線基板１の端部との間の領域に差がある場合を示している。この場合、横方向が配線基板１と封止樹脂７の接触面積が多く、封止樹脂７の量が多く配置されるため、封止樹脂７は縦方向よりも横方向に大きく、半導体装置２００の反りが発生する。そのため、半導体チップ２の端部と配線基板１の端部の間の領域が大きい横方向にのみ低弾性樹脂８を設けることで、横方向での反りを調整し、半導体装置２００の反りを低減できる。   In the second embodiment, the semiconductor chip 2 mounted on the wiring substrate 1 has a substantially rectangular shape, the region between the end of the semiconductor chip 2 in the vertical direction and the end of the wiring substrate 1, and the semiconductor in the horizontal direction. The case where there is a difference in the area between the end of the chip 2 and the end of the wiring substrate 1 is shown. In this case, since the contact direction between the wiring substrate 1 and the sealing resin 7 is large in the horizontal direction and the amount of the sealing resin 7 is large, the sealing resin 7 is larger in the horizontal direction than in the vertical direction. Warpage occurs. Therefore, by providing the low elastic resin 8 only in the lateral direction where the region between the end portion of the semiconductor chip 2 and the end portion of the wiring substrate 1 is large, the warpage in the lateral direction is adjusted and the warpage of the semiconductor device 200 is reduced. it can.

さらに、低弾性樹脂８を、接続パッド６の設けられていない側の領域にのみ配置するため、低弾性樹脂８が接続パッド６を覆うリスクを低減できる。   Furthermore, since the low elastic resin 8 is disposed only in the region where the connection pads 6 are not provided, the risk that the low elastic resin 8 covers the connection pads 6 can be reduced.

（第３の実施形態）
図５は、本発明の第３の実施形態に係る半導体装置３００の概略構成を示す図であり、（ａ）は平面図であり、（ｂ）は（ａ）のＤ−Ｄ’断面図である。 (Third embodiment)
5A and 5B are diagrams showing a schematic configuration of a semiconductor device 300 according to the third embodiment of the present invention, in which FIG. 5A is a plan view and FIG. 5B is a sectional view taken along line DD ′ in FIG. is there.

尚、説明の便宜上、図１に示す半導体装置１００と同じ構成要素には、同じ参照符号が付されている。   For convenience of explanation, the same reference numerals are assigned to the same components as those of the semiconductor device 100 shown in FIG.

第３の実施形態では、低弾性樹脂８が半導体チップ２の側面も覆うように形成した点で、第１の実施形態と異なっている。この場合には、ワイヤボンディング後、半導体チップ２の周辺に低弾性樹脂８を塗布することで形成する。   The third embodiment is different from the first embodiment in that the low elastic resin 8 is formed so as to cover the side surface of the semiconductor chip 2. In this case, the low-elasticity resin 8 is applied around the semiconductor chip 2 after wire bonding.

第３の実施形態では、第１の実施形態と同様な効果が得られると共に、半導体チップ２の側面を低弾性樹脂８で覆うようにしたことで、封止時の半導体チップ２の側面へのボイドの発生を抑制できる。また、ワイヤ５が低弾性樹脂８で覆われることで、ワイヤ流れやワイヤショートの発生を低減できる。   In the third embodiment, the same effects as those of the first embodiment can be obtained, and the side surface of the semiconductor chip 2 is covered with the low elastic resin 8 so that the side surface of the semiconductor chip 2 at the time of sealing is covered. Generation of voids can be suppressed. Further, since the wire 5 is covered with the low-elasticity resin 8, the occurrence of wire flow and wire short can be reduced.

ここで、半導体チップ２上にまで低弾性樹脂８を配置してしまうと、低弾性樹脂８にはマークを形成するのが困難であるため、低弾性樹脂８の上にも封止樹脂７を配置する必要が生じる。この結果、半導体チップ２上の封止樹脂７の厚さが大きくなり、半導体装置３００の薄型化を阻害する。このため、半導体チップ２上には低弾性樹脂８を配置しない方が好ましい。   Here, if the low elastic resin 8 is disposed on the semiconductor chip 2, it is difficult to form a mark on the low elastic resin 8. It becomes necessary to arrange. As a result, the thickness of the sealing resin 7 on the semiconductor chip 2 is increased, and the thinning of the semiconductor device 300 is hindered. For this reason, it is preferable not to arrange the low-elasticity resin 8 on the semiconductor chip 2.

（第４の実施形態）
図６は、本発明の第４の実施形態に係る半導体装置４００の概略構成を示す図であり、（ａ）は平面図であり、（ｂ）は（ａ）のＥ−Ｅ’断面図であり、（ｃ）は（ａ）のＦ−Ｆ’断面図である。 (Fourth embodiment)
6A and 6B are diagrams showing a schematic configuration of a semiconductor device 400 according to the fourth embodiment of the present invention. FIG. 6A is a plan view, and FIG. 6B is a cross-sectional view taken along line EE ′ of FIG. (C) is a cross-sectional view taken along line FF ′ of (a).

尚、説明の便宜上、図１に示す半導体装置１００と同じ構成要素には、同じ参照符号が付されている。   For convenience of explanation, the same reference numerals are assigned to the same components as those of the semiconductor device 100 shown in FIG.

第４の実施形態では、配線基板１に第１の半導体チップ２が搭載され、第１の半導体チップ２上に第２の半導体チップ２０が積層されるように構成されている。そして、第２の半導体チップ２０は、第１の半導体チップ２からオーバーハングするように積層されており、第１の半導体チップ２の周辺に設けられた低弾性樹脂８が第２の半導体チップ２０のオーバーハング部３０の下に配置される。   In the fourth embodiment, the first semiconductor chip 2 is mounted on the wiring substrate 1, and the second semiconductor chip 20 is stacked on the first semiconductor chip 2. The second semiconductor chip 20 is stacked so as to overhang from the first semiconductor chip 2, and the low-elasticity resin 8 provided around the first semiconductor chip 2 is formed by the second semiconductor chip 20. It is arranged under the overhang part 30.

第４の実施形態では、第３の実施形態と同様な効果が得られると共に、低弾性樹脂８によって第２の半導体チップ２０のオーバーハング部３０を支えることができ、第２の半導体チップ２０のワイヤボンディング時のチップクラックを抑制し、良好にワイヤ接続できる。   In the fourth embodiment, the same effect as in the third embodiment can be obtained, and the overhang portion 30 of the second semiconductor chip 20 can be supported by the low elastic resin 8, so that the second semiconductor chip 20 Chip cracks during wire bonding can be suppressed and wire connection can be made satisfactorily.

（第５の実施形態）
図７は、本発明の第５の実施形態に係る半導体装置５００の概略構成を示す図であり、（ａ）は平面図であり、（ｂ）は（ａ）のＧ−Ｇ’断面図であり、（ｃ）は（ａ）のＨ−Ｈ’断面図である。 (Fifth embodiment)
7A and 7B are diagrams showing a schematic configuration of a semiconductor device 500 according to the fifth embodiment of the present invention, in which FIG. 7A is a plan view and FIG. 7B is a sectional view taken along line GG ′ in FIG. (C) is a cross-sectional view taken along line HH ′ of (a).

尚、説明の便宜上、図６に示す半導体装置４００と同じ構成要素には、同じ参照符号が付されている。   For convenience of explanation, the same components as those in the semiconductor device 400 shown in FIG.

第５の実施形態では、第４の実施形態と同様に構成されており、第１の半導体チップ２上にも低弾性樹脂４０が配置されている点で異なっている。第１の半導体チップ２と第２の半導体チップ２０がクロス積層するように構成されている場合、H-H’方向が、G-G’方向よりもチップ上の樹脂が厚く構成されるため、封止樹脂７の厚いH-H’方向がG-G’方向よりも凹反りを発生する傾向にある。   The fifth embodiment is configured in the same manner as the fourth embodiment, and is different in that a low elastic resin 40 is also disposed on the first semiconductor chip 2. When the first semiconductor chip 2 and the second semiconductor chip 20 are configured to cross-stack, the HH ′ direction is configured to have a thicker resin on the chip than the GG ′ direction. The thick HH ′ direction of the sealing resin 7 tends to generate a concave warp than the GG ′ direction.

第５の実施形態では、第４の実施形態と同様な効果が得られると共に、第１の半導体チップ２上にも低弾性樹脂４０を配置したことで、H-H’方向での凹反りを抑えることができ、XY方向での反りのバランスを向上できる。   In the fifth embodiment, the same effects as in the fourth embodiment can be obtained, and the low elastic resin 40 is also disposed on the first semiconductor chip 2, so that the concave warpage in the HH ′ direction is achieved. It can be suppressed and the balance of warpage in the XY direction can be improved.

尚、第５の実施形態では、第１の半導体チップ２の電極パッド４を覆わないように低弾性樹脂４０を配置するようにしたが、第１の半導体チップ２のワイヤ接続後に、第１の半導体チップ２上に低弾性樹脂４０を形成する場合には、低弾性樹脂４０は電極パッド４上も覆うようにしても良い。   In the fifth embodiment, the low elastic resin 40 is disposed so as not to cover the electrode pads 4 of the first semiconductor chip 2. However, after the first semiconductor chip 2 is connected to the wire, When the low elastic resin 40 is formed on the semiconductor chip 2, the low elastic resin 40 may also cover the electrode pads 4.

以上、本発明者によってなされた発明を実施例に基づき説明したが、本発明は上記実施例に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることは言うまでもない。   As mentioned above, although the invention made | formed by this inventor was demonstrated based on the Example, this invention is not limited to the said Example, It cannot be overemphasized that it can change variously in the range which does not deviate from the summary.

本実施の形態では、低弾性樹脂８を配線基板１上に部分的に配置するように構成したが、チップ搭載領域を除く、全面に設けるようにしても良い。   In the present embodiment, the low-elasticity resin 8 is partially arranged on the wiring board 1, but it may be provided on the entire surface except for the chip mounting area.

また、本実施の形態では、ガラスエポキシ基材からなる配線基板について説明したが、ポリイミド基材からなるフレキシブルな配線基板等に適用しても良い。   In the present embodiment, the wiring board made of a glass epoxy base material has been described. However, the present invention may be applied to a flexible wiring board made of a polyimide base material.

上記の実施形態の一部又は全部は、以下の付記のようにも記載され得るが、以下には限られない。   A part or all of the above embodiments can be described as in the following supplementary notes, but is not limited thereto.

（付記１）
配線基板を準備する工程と、
前記配線基板の一面のチップ搭載位置の外側に低弾性樹脂を形成する工程と、
前記チップ搭載位置に半導体チップを搭載する工程と、
前記半導体チップ及び前記低弾性樹脂を覆うように、前記配線基板の前記一面に封止樹脂を形成する工程を有し、 前記低弾性樹脂は、前記封止樹脂の弾性率より低い弾性率を有することを特徴とする半導体装置の製造方法。 (Appendix 1)
Preparing a wiring board; and
Forming a low-elasticity resin outside the chip mounting position on one side of the wiring board;
Mounting a semiconductor chip at the chip mounting position;
Forming a sealing resin on the one surface of the wiring substrate so as to cover the semiconductor chip and the low-elasticity resin, and the low-elasticity resin has an elastic modulus lower than an elastic modulus of the sealing resin. A method for manufacturing a semiconductor device.

（付記２）
前記低弾性樹脂を形成する工程は、
前記チップ搭載位置の外側に前記低弾性樹脂を供給し、
前記配線基板に供給された前記低弾性樹脂を所定の温度でキュアすることにより硬化させることを特徴とする付記１に記載の半導体装置の製造方法。 (Appendix 2)
The step of forming the low-elasticity resin includes
Supplying the low elastic resin to the outside of the chip mounting position;
The method for manufacturing a semiconductor device according to claim 1, wherein the low-elasticity resin supplied to the wiring board is cured by curing at a predetermined temperature.

（付記３）
前記低弾性樹脂は、前記配線基板と前記封止樹脂の間の緩衝材として作用して前記半導体装置の反りを低減することを特徴とする付記１又は２に記載の半導体装置の製造方法。 (Appendix 3)
3. The method of manufacturing a semiconductor device according to claim 1, wherein the low elastic resin acts as a buffer material between the wiring substrate and the sealing resin to reduce warpage of the semiconductor device.

（付記４）
前記低弾性樹脂を、前記チップ搭載位置の外側に略枠状に形成することを特徴とする付記１から３のいずれか１項に記載の半導体装置の製造方法。 (Appendix 4)
4. The method of manufacturing a semiconductor device according to claim 1, wherein the low-elasticity resin is formed in a substantially frame shape outside the chip mounting position.

（付記５）
前記低弾性樹脂の幅を変更することにより、前記配線基板と前記封止樹脂との接触する面積を変更して前記半導体装置の反りを調整することを特徴とする付記１から４のいずれか１項に記載の半導体装置の製造方法。 (Appendix 5)
Any one of appendices 1 to 4, wherein the warp of the semiconductor device is adjusted by changing the area of contact between the wiring board and the sealing resin by changing the width of the low-elasticity resin. A method for manufacturing the semiconductor device according to the item.

（付記６）
前記低弾性樹脂を、シリコーン樹脂又はアンダーフィルで形成したことを特徴とする付記１から５のいずれか１項に記載の半導体装置の製造方法。 (Appendix 6)
6. The method of manufacturing a semiconductor device according to any one of appendices 1 to 5, wherein the low-elasticity resin is formed of a silicone resin or an underfill.

（付記７）
配線基板と、
前記配線基板の一面に搭載された第１の半導体チップと、
少なくとも前記第１の半導体チップの対向する２辺に沿うように、前記配線基板上に配置された樹脂部と、
対向する２辺が前記樹脂部の上方に位置するように、前記第１の半導体チップ上に積層された第２の半導体チップと、
前記第１の半導体チップ、前記第２の半導体チップ及び前記樹脂部を覆う封止樹脂とを有することを特徴とする半導体装置。 (Appendix 7)
A wiring board;
A first semiconductor chip mounted on one surface of the wiring board;
A resin portion disposed on the wiring board so as to extend along at least two opposing sides of the first semiconductor chip; and
A second semiconductor chip stacked on the first semiconductor chip such that two opposing sides are positioned above the resin portion;
A semiconductor device comprising: a sealing resin that covers the first semiconductor chip, the second semiconductor chip, and the resin portion.

（付記８）
前記樹脂部は、前記封止樹脂の弾性率より低い弾性率を有することを特徴とする付記７に記載の半導体装置。 (Appendix 8)
The semiconductor device according to appendix 7, wherein the resin portion has an elastic modulus lower than that of the sealing resin.

１ 配線基板
２ 半導体チップ（第１半導体チップ）
３ 接着部材
４ 電極パッド
５ ワイヤ
６ 接続パッド
７ 封止樹脂
８ 低弾性樹脂
９ ランド
１０ はんだボール
１１ ソルダーレジスト膜
１２ 絶縁基材
１３ 絶縁膜
１４ 絶縁膜
１５ ダイシングライン
２０ 第２半導体チップ
３０オーバーハング部
４０低弾性樹脂
５０ 開口部
１００半導体装置
２００半導体装置
３００半導体装置
４００半導体装置
５００半導体装置 DESCRIPTION OF SYMBOLS 1 Wiring board 2 Semiconductor chip (1st semiconductor chip)
3 Adhesive member 4 Electrode pad 5 Wire 6 Connection pad 7 Sealing resin 8 Low elastic resin 9 Land 10 Solder ball 11 Solder resist film 12 Insulating base material 13 Insulating film 14 Insulating film 15 Dicing line 20 Second semiconductor chip 30 Overhang portion 40 low elastic resin 50 opening 100 semiconductor device 200 semiconductor device 300 semiconductor device 400 semiconductor device 500 semiconductor device

Claims (10)

配線基板と、
前記配線基板の一面に搭載された半導体チップと、
前記半導体チップを覆うように、前記配線基板の前記一面に設けられた封止樹脂と、 前記封止樹脂の弾性率より低い弾性率を有し、前記配線基板と前記封止樹脂の間に配置された低弾性樹脂とを有することを特徴とする半導体装置。 A wiring board;
A semiconductor chip mounted on one surface of the wiring board;
A sealing resin provided on the one surface of the wiring substrate so as to cover the semiconductor chip; and an elastic modulus lower than an elastic modulus of the sealing resin, and disposed between the wiring substrate and the sealing resin. And a low-elasticity resin. 前記低弾性樹脂は、前記配線基板と前記封止樹脂の間の緩衝材として作用して前記半導体装置の反りを低減することを特徴とする請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein the low elastic resin acts as a buffer material between the wiring substrate and the sealing resin to reduce warpage of the semiconductor device. 前記低弾性樹脂は、前記半導体チップの外側に略枠状に形成されていることを特徴とする請求項１又は２に記載の半導体装置。   The semiconductor device according to claim 1, wherein the low-elasticity resin is formed in a substantially frame shape outside the semiconductor chip. 前記低弾性樹脂の幅を変更することにより前記半導体装置の反りを調整することを特徴とする請求項１から３のいずれか１項に記載の半導体装置。   4. The semiconductor device according to claim 1, wherein warpage of the semiconductor device is adjusted by changing a width of the low-elasticity resin. 5. 前記半導体チップは略長方形状であり、かつ横方向における前記半導体チップの端部と前記配線基板の端部の間の第１の領域が、縦方向における前記半導体チップの端部と前記配線基板の端部の間の第２の領域よりも広く構成され、
前記低弾性樹脂は、前記第１の領域にのみ縦方向に沿って配置されていることを特徴とする請求項１又は２に記載の半導体装置。 The semiconductor chip has a substantially rectangular shape, and the first region between the end of the semiconductor chip and the end of the wiring board in the horizontal direction is the end of the semiconductor chip in the vertical direction and the end of the wiring board. Configured wider than the second region between the ends,
The semiconductor device according to claim 1, wherein the low-elasticity resin is disposed along the vertical direction only in the first region. 前記低弾性樹脂は、前記前記半導体チップの上面には配置されておらず、前記半導体チップの側面を覆うよう配置されていることを特徴とする請求項１又は２に記載の半導体装置。   3. The semiconductor device according to claim 1, wherein the low-elasticity resin is not disposed on an upper surface of the semiconductor chip but is disposed so as to cover a side surface of the semiconductor chip. 前記低弾性樹脂は、シリコーン樹脂又はアンダーフィルから成ることを特徴とする請求項１から６のいずれか１項に記載の半導体装置。   The semiconductor device according to claim 1, wherein the low-elasticity resin is made of a silicone resin or an underfill. 配線基板と、
前記配線基板の一面に搭載された第１の半導体チップと、
前記第１の半導体チップからオーバーハングするように前記第１の半導体チップ上に積層された第２の半導体チップと、
前記第１の半導体チップと前記第２の半導体チップを覆うように、前記配線基板の前記一面に設けられた封止樹脂と、
前記封止樹脂の弾性率より低い弾性率を有し、前記配線基板と前記封止樹脂の間に配置された低弾性樹脂とを有し、
前記第２の半導体チップのオーバーハング部が、前記低弾性樹脂の上方に位置することを特徴とする半導体装置。 A wiring board;
A first semiconductor chip mounted on one surface of the wiring board;
A second semiconductor chip stacked on the first semiconductor chip so as to overhang from the first semiconductor chip;
A sealing resin provided on the one surface of the wiring board so as to cover the first semiconductor chip and the second semiconductor chip;
Having a lower elastic modulus than the elastic modulus of the sealing resin, and having a low elastic resin disposed between the wiring board and the sealing resin,
An overhang portion of the second semiconductor chip is located above the low elastic resin. 前記第１の半導体チップ上にも前記低弾性樹脂を配置したことを特徴とする請求項８に記載の半導体装置。   9. The semiconductor device according to claim 8, wherein the low-elasticity resin is also disposed on the first semiconductor chip. 前記低弾性樹脂は、前記配線基板と前記封止樹脂の間の緩衝材として作用して前記半導体装置の反りを低減することを特徴とする請求項８又は９に記載の半導体装置。   The semiconductor device according to claim 8, wherein the low-elasticity resin acts as a buffer material between the wiring board and the sealing resin to reduce warpage of the semiconductor device.
JP2012150755A 2012-07-04 2012-07-04 Semiconductor device Withdrawn JP2014013836A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2012150755A JP2014013836A (en) 2012-07-04 2012-07-04 Semiconductor device
US13/933,318 US20140008775A1 (en) 2012-07-04 2013-07-02 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012150755A JP2014013836A (en) 2012-07-04 2012-07-04 Semiconductor device

Publications (1)

Publication Number Publication Date
JP2014013836A true JP2014013836A (en) 2014-01-23

Family

ID=49877896

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012150755A Withdrawn JP2014013836A (en) 2012-07-04 2012-07-04 Semiconductor device

Country Status (2)

Country Link
US (1) US20140008775A1 (en)
JP (1) JP2014013836A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020513157A (en) * 2017-04-07 2020-04-30 ▲寧▼波舜宇光▲電▼信息有限公司 Semiconductor packaging method and semiconductor device based on molding process
US11081518B2 (en) 2017-04-07 2021-08-03 Ningbo Sunny Opotech Co., Ltd. Semiconductor packaging method and semiconductor device based on molding process

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9889502B2 (en) * 2014-06-25 2018-02-13 Halliburton Energy Services, Inc. Insulation enclosure with a radiant barrier
KR102493463B1 (en) * 2016-01-18 2023-01-30 삼성전자 주식회사 Printed circuit board, semiconductor package having the same, and method for manufacturing the same

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5866953A (en) * 1996-05-24 1999-02-02 Micron Technology, Inc. Packaged die on PCB with heat sink encapsulant
WO2001018864A1 (en) * 1999-09-03 2001-03-15 Seiko Epson Corporation Semiconductor device, method of manufacture thereof, circuit board, and electronic device
KR100401020B1 (en) * 2001-03-09 2003-10-08 앰코 테크놀로지 코리아 주식회사 Stacking structure of semiconductor chip and semiconductor package using it
JP4390541B2 (en) * 2003-02-03 2009-12-24 Ｎｅｃエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
JP4732535B2 (en) * 2009-06-09 2011-07-27 キヤノン株式会社 Liquid discharge recording head and manufacturing method thereof
US8143110B2 (en) * 2009-12-23 2012-03-27 Intel Corporation Methods and apparatuses to stiffen integrated circuit package

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020513157A (en) * 2017-04-07 2020-04-30 ▲寧▼波舜宇光▲電▼信息有限公司 Semiconductor packaging method and semiconductor device based on molding process
US11081518B2 (en) 2017-04-07 2021-08-03 Ningbo Sunny Opotech Co., Ltd. Semiconductor packaging method and semiconductor device based on molding process
JP7041167B2 (en) 2017-04-07 2022-03-23 ▲寧▼波舜宇光▲電▼信息有限公司 Semiconductor packaging methods and semiconductor devices based on the molding process
US11728368B2 (en) 2017-04-07 2023-08-15 Ningbo Sunny Opotech Co., Ltd. Semiconductor packaging method and semiconductor device based on molding process

Also Published As

Publication number Publication date
US20140008775A1 (en) 2014-01-09

Similar Documents

Publication Publication Date Title
US20110115085A1 (en) Semiconductor device and method of fabricating the same
JP5543086B2 (en) Semiconductor device and manufacturing method thereof
WO2014042165A1 (en) Semiconductor device and method for manufacturing semiconductor device
JP2011077108A (en) Semiconductor device
JP2013045863A (en) Semiconductor device and manufacturing method of the same
JP2010153466A (en) Wiring board
JP2012230981A (en) Semiconductor device and manufacturing method of the same
JP2006344898A (en) Semiconductor device and its manufacturing method
JP5557439B2 (en) Semiconductor device and manufacturing method thereof
KR20150135412A (en) Semiconductor device
JP2014013836A (en) Semiconductor device
JP5667381B2 (en) Semiconductor device and manufacturing method thereof
JP2012028513A (en) Semiconductor device and manufacturing method of the same
JP2012009713A (en) Semiconductor package and method of manufacturing the same
JP5579982B2 (en) Intermediate structure of semiconductor device and method of manufacturing intermediate structure
JP2010135501A (en) Method of manufacturing semiconductor device
JP2009182004A (en) Semiconductor device
JP5666211B2 (en) Wiring substrate and semiconductor device manufacturing method
US20100265683A1 (en) Semiconductor device
JP2011061055A (en) Method of manufacturing semiconductor device
JP2015056540A (en) Semiconductor device and manufacturing method of the same
JP2013157433A (en) Semiconductor device
JP2011151104A (en) Method for manufacturing semiconductor device and intermediate structure of the semiconductor device
JP2012138394A (en) Semiconductor manufacturing method
JP2013172069A (en) Semiconductor device and manufacturing method of the same

Legal Events

Date Code Title Description
A761 Written withdrawal of application

Free format text: JAPANESE INTERMEDIATE CODE: A761

Effective date: 20141224