JP3915325B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

Info

Publication number
JP3915325B2
JP3915325B2 JP19054699A JP19054699A JP3915325B2 JP 3915325 B2 JP3915325 B2 JP 3915325B2 JP 19054699 A JP19054699 A JP 19054699A JP 19054699 A JP19054699 A JP 19054699A JP 3915325 B2 JP3915325 B2 JP 3915325B2
Authority
JP
Japan
Prior art keywords
electrode
circuit board
chip
wafer
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP19054699A
Other languages
Japanese (ja)
Other versions
JP2001024086A (en
Inventor
俊夫 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Denso Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Corp filed Critical Denso Corp
Priority to JP19054699A priority Critical patent/JP3915325B2/en
Publication of JP2001024086A publication Critical patent/JP2001024086A/en
Application granted granted Critical
Publication of JP3915325B2 publication Critical patent/JP3915325B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Wire Bonding (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、プリント回路基板上に実装される半導体装置およびその製造方法に関するものであり、特にチップとほぼ同じ大きさを有するチップ・サイズ・パッケージに用いられるものである。
【０００２】
【従来の技術】
従来、多端子のＩＣパッケージを小型化するものとして、半導体チップとほぼ同等あるいはわずかに大きいサイズのＣＳＰ（チップ・サイズ・パッケージ）がある。ＣＳＰはウエハから切り出したチップ毎にパッケージするものである。図４は従来構造における２種類のＣＳＰの構成を示しており、ＣＳＰの電極接合は一般的に図４（ａ）に示すワイヤボンディングあるいは図４（ｂ）に示すフリップチップなどにより行われる。
【０００３】
ワイヤボンディングによる電極接合を行うＣＳＰの製造工程は、次のように行われる。まず、ウエハをカットして形成した半導体チップＪ１ａを回路基板Ｊ２上にダイマウントし、チップ側電極Ｊ３と回路基板側電極Ｊ４とをＡｕワイヤによりボンディングして接続する。次にチップＪ１ａを封止するための樹脂Ｊ１０を塗布して硬化させる。最後に回路基板におけるチップ搭載側の反対側の外側電極Ｊ５上に突起電極Ｊ７を形成する。
【０００４】
また、フリップチップによる電極接合を行うＣＳＰの製造工程は、次のように行われる。まず、予めチップ側電極Ｊ３上に突起電極Ｊ３ａを形成したウエハをカットしてチップＪ１ａを形成し、突起電極Ｊ３ａと回路基板側電極Ｊ４とをはんだ付け等で接続することによりチップＪ１ａを回路基板Ｊ２に組み付ける。次に、チップＪ１ａを封止するための樹脂Ｊ１０をチップＪ１ａと回路基板Ｊ２との間に注入して硬化させる。最後に回路基板Ｊ２におけるチップ搭載側の反対側に突起電極Ｊ７を形成する。
【０００５】
以上のように、従来のＣＳＰではワイヤボンディング、フリップチップ等による電極接合と、樹脂によるチップ封止等が必要であり、組み付け工程が長くなり、パッケージコストが高くなるという問題があった。
【０００６】
また、ＣＳＰのコストダウンを目的として特開平９−８２８５０号公報および特開平１０−５０７７２号公報に記載されている半導体装置がある。しかしながら、特開平９−８２８５０号公報に記載されている半導体装置では、チップ上の表面電極から外部接続端子部までの配線形成工程とチップ表面を樹脂で封止する工程とが別になり、全体の工程が長くなるという問題がある。また、特開平１０−５０７７２号公報に記載されている半導体装置では、チップ上の表面電極から外側に伸びる外部接続端子をワイヤボンディングにより１つずつ形成しなければならず、ボンディング工程に時間がかかるという問題があった。
【０００７】
これに対し、特開平８−３３５６５３号公報において、チップ上の表面電極から外部接続端子までの配線形成とチップ表面の樹脂封止を同時に実施する半導体装置が記載されている。この半導体装置の構成を図５に示す。この半導体装置は、回路基板側電極Ｊ４上に突起電極Ｊ４ａを形成した補助配線板（回路基板）Ｊ２とチップ側電極Ｊ３を形成したチップＪ１ａとを熱融着性ポリイミド樹脂Ｊ１０を介して接着するように構成されている。これにより、チップ側電極Ｊ３と回路基板側電極Ｊ４と接続するとともに、熱融着性ポリイミド樹脂Ｊ１０によってチップＪ１ａと回路基板Ｊ２との間隙を封止するものである。
【０００８】
【発明が解決しようとする課題】
しかしながら、上記特開平８−３３５６５３号公報に記載された半導体装置は以下に述べるような問題がある。
【０００９】
すなわち、回路基板Ｊ２以外に樹脂封止のための熱融着性ポリイミド樹脂Ｊ１０が必要である。また、回路基板Ｊ２への半導体チップＪ１ａの接着が１チップ毎に行われるため、生産性が低い。さらに、回路基板側電極Ｊ４は突起電極により構成されるため、回路基板側電極Ｊ４をチップ側電極Ｊ３に接続する際、突起電極に高さバラツキがある場合には、低すぎる突起電極はチップ側電極に接続できなくなり、逆に高すぎる突起電極はチップ側電極との接続時につぶれて横に広がり、隣の突起電極にショートしてしまう場合がある。
【００１０】
本発明は、上記点に鑑み、製造コストが低減でき、かつ、信頼性の高い半導体装置およびその製造方法を提供することを目的とする。
【００１１】
本発明は、上記目的を達成するために、請求項１記載の発明では、一面に複数の平坦な第１の電極（３）が形成されたウエハ（１）と、一面に第１の電極（３）に対応する複数の平坦な第２の電極（４）が形成された回路基板（２）とを用意する工程と、第１の電極（３）と第２の電極（４）とが接触するとともに、半導体チップ（１ａ）の電極形成面における第１の電極（３）が形成されていない部分と回路基板（２）の電極形成面における第２の電極（４）が形成されていない部分とが接触するように、ウエハ（１）と回路基板（２）と接触させる工程と、ウエハ（１）と回路基板（２）とを加圧した後で加熱して、第１の電極（３）と第２の電極（４）とを接触、接着または接合させるとともに、半導体チップ（１ａ）の電極形成面における第１の電極（３）が形成されていない部分と回路基板（２）の電極形成面における第２の電極（４）が形成されていない部分とを接触または接着させることにより、ウエハ（１）と回路基板（２）とを接着させる工程と、接着工程の後、ウエハ（１）および回路基板（２）とを半導体チップ（１ａ）単位に切断する工程とを備えている。
【００１２】
このように第１の電極（３）および第２の電極（４）を平坦状に形成することにより、突起電極のように電極の高さバラツキが発生することを防止できる。これにより、電極の接続不良発生を防止することができる。また、回路基板（２）の電極が形成されていない樹脂部分によって半導体チップ（１ａ）の樹脂封止を行うことができる。従って、樹脂封止のため専用の樹脂材料を用いることなく、第１の電極（３）と第２の電極（４）との接合と半導体チップ（１ａ）の樹脂封止を同時に実施することが可能になる。
【００１３】
また、回路基板（２）は熱可塑性樹脂材料から形成され、半導体チップ（１ａ）と回路基板（２）は加圧された後で加熱されることによって接着されていることで、回路基板（２）の第２の電極（４）が形成されていない樹脂部分と半導体チップ（１ａ）の電極が形成されていない部分とを良好に接着することができる。なお、熱可塑性樹脂として、具体的にはポリイミドを用いることができる。
【００１５】
このように、回路基板（２）にチップ（１ａ）毎に組み付けるのではなく、ウエハ（１）毎に組み付け、その後チップ単位に切断することにより、生産性を向上させることができ、パッケージコストを下げることができる。
【００１６】
なお、上記各手段の括弧内の符号は、後述する実施形態に記載の具体的手段との対応関係を示す一例である。
【００１７】
【発明の実施の形態】
以下、本発明を適用した実施形態について図に基づいて説明する。
【００１８】
まず、本実施形態における半導体装置の構成について図１に基づいて説明する。図１は半導体装置の概略構成を示す断面図である。なお、本実施形態における半導体装置はＣＳＰ（チップ・サイズ・パッケージ）タイプのものである。
【００１９】
半導体装置１０は半導体チップ１ａおよび回路基板２とから形成される。半導体チップ１ａはウエハをカットすることにより形成されるものであり、その一面には複数の第１の電極（チップ側電極）３が形成されている。また、回路基板２におけるチップ１ａが接着される面には、チップ側電極３に対応する複数の第２の電極（回路基板側電極）４が形成されている。チップ側電極３および回路基板側電極４ともにそれぞれが形成されている面に対して平坦になるように形成されている。
【００２０】
また、回路基板２におけるチップ接着側の反対側にも平坦な外側電極５が形成されおり、これらの回路基板側電極４および外側電極５を電気的に接続するための内部配線６が回路基板２内に形成されている。外側電極５にはマザーボードであるプリント基板に接続するための突起電極７が形成されている。
【００２１】
回路基板２は、例えば熱可塑性樹脂材料から形成される。本実施形態では、回路基板２はポリイミド樹脂から形成されている。なお、本実施形態においては、回路基板２の厚さを２００μｍとしている。チップ側電極３は例えばＡｌから形成され、回路基板側電極４は例えばＡｕから形成されている。
【００２２】
チップ１ａと回路基板２とは、チップ側電極３と回路基板側電極４とが対向するように接続されている。このとき、電極が形成されていないチップ１ａの表面と回路基板表面の樹脂とが直接接着されている。
【００２３】
次に、上記構成の半導体装置１０の製造方法を図２に基づいて説明する。図２は、本実施形態における半導体装置の製造工程を示している。
【００２４】
まず、図２（ａ）に示すように、チップ単位にカットしていない複数のチップ側電極３が形成されたウエハ１と、チップ側電極３に対応する回路基板側電極４が形成された回路基板２を用意する。
【００２５】
次に、図２（ｂ）に示すように、ウエハ１と回路基板２とを、互いの電極３、４の位置を合わせて接触させる。このとき、ウエハ１と回路基板２とは、電極同士が接触しているとともに、ウエハ表面の電極が形成されていない部分と回路基板表面の電極が形成されていない樹脂部分とが接触している。
【００２６】
次に、ウエハ１と回路基板２とを挟み込むようにして加圧する。この際、上記のように回路基板２の外側電極５は平坦に形成されているので、加圧作業を行いやすくなっている。そして、ウエハ１と回路基板２に圧力をかけた状態で加熱を行う。これによって、ウエハ内のチップ１ａのチップ側電極３と回路基板表面に形成された回路基板側電極４とが接続される。具体的には、本実施形態のようにチップ側電極３がＡｌもしくはＡｕであり、回路基板側電極４がＡｕであれば、ＡｌとＡｕもしくはＡｕ同士の固相拡散により電極同士の接続が形成される。また、チップ側電極３と回路基板側電極４はＡｌやＡｕ以外の金属でも可能であり、さらに少なくとも一方が導電性接着剤でも接続は可能となる。
【００２７】
回路基板２は熱可塑性樹脂から形成されていることから加熱によって軟化し、回路基板２の樹脂部分とチップ１ａ表面の保護膜とが接着される。本実施形態で回路基板２として用いているポリイミド樹脂等の有機物は官能基を有していることから、回路基板２を加熱する際に官能基がチップ表面の保護膜の原子に接近して接合状態を作り、化学的な結合が得やすくなると考えられる。このように、回路基板２とチップ１ａとを接着することにより、チップ表面を樹脂で覆うことになり、電極接続と同時に樹脂によるチップ封止を実施することができる。
【００２８】
このとき、室温ではウエハ１上のチップ側電極３と回路基板２上の回路基板側電極４との位置合わせができていても、加熱した後ではウエハ１と回路基板２とは線膨張係数が異なるので、チップ側電極３と回路基板側電極４との位置ずれが発生してしまう。これに対して、本実施形態では室温でウエハ１と回路基板２を挟み込んで加圧した後に加熱することにより、お互いの熱による変位の差による位置ずれを問題ないレベルに抑えている。
【００２９】
さらに通常、回路基板２には反りなどによる変形が発生しており、回路基板２上に形成した平坦な電極４の位置が上下にばらつくことがある。これについても、ウエハ１と回路基板２を挟み込んで加圧し、この後に加熱することで回路基板２を軟らかくして、反りなどの変形をなくすことができ、チップ側電極３と回路基板側電極４との良好な接続を得ることができる。
【００３０】
以上の工程における加熱温度は１００〜３００℃で、特に望ましくは１５０〜２５０℃であり、加圧時間は３０秒〜３０分であり、加圧力は５〜５０ｋｇ／ｃｍ2程度である。
【００３１】
この後、図２（ｃ）に示すように、マザーボードであるプリント基板への接続のために必要であれば、ウエハ１を接着しない回路基板側の外側電極５上にハンダバンプからなる突起電極７を形成する。この突起電極７は例えばハンダボールを用いて形成する。
【００３２】
上記各工程終了後、図２（ｄ）に示すように、ウエハ１をチップ単位（図２（ｄ）中の破線）でカットすることにより、複数のＣＳＰタイプの半導体装置１０を得ることができる。
【００３３】
以上のように、本実施形態の半導体装置によれば、ウエハから切り出したチップ単位で回路基板に組み付けるのではなく、ウエハ単位で組み付けを行うので、半導体装置製造における生産性を向上させることができ、パッケージコストを低減させることができる。
【００３４】
また、チップ側電極および回路基板側電極を、突起電極でなく平坦な電極として形成することにより、電極の高さバラツキによる接続不具合をなくすことができる。
【００３５】
さらに、電極が形成されていないチップ表面と回路基板表面の樹脂部とを接着することにより、電極接続と同時にチップの樹脂封止を実現できるため、樹脂封止のための樹脂材料が不要となる。
【００３６】
ところで、上述の特開平８−３３５６５３号公報に記載された半導体装置では、チップを接着する回路基板の厚さが５０〜１５０μｍと薄く形成されている。このため、回路基板におけるチップ接着側の反対側に形成された突起電極を介して、例えばハンダ付け等でマザーボードであるプリント基板に接続する際、プリント基板とチップ（Ｓｉ）との線膨張係数の差が大きすぎて冷熱サイクルが加わると回路基板の電極とプリント基板の電極とを接続しているハンダ接続部にクラックが入ってオープンに至るという不具合があった。
【００３７】
これに対し、本実施形態ではチップとプリント基板との間に位置することになる回路基板の厚さを２００μｍ以上としている。このようにすることで、チップとマザーボードであるプリント基板との線膨張係数の差によって上記のハンダ接合部に発生する歪みを軽減することができる。
【００３８】
次に、チップ１ａのチップ側電極３の配置、および回路基板２のチップ接着側の反対側に形成された外側電極５の配置を図３に基づいて説明する。図３（ａ）はチップ側電極３の配置を示すチップ１ａの底面図であり、図３（ｂ）は外側電極５の配置を示す回路基板２の底面図である。
【００３９】
ウエハ１内のチップ１ａ上のチップ側電極３は、通常、図３（ａ）に示すようにチップ１ａの外周縁部に配置されており、この電極ピッチは通常１００〜１５０μｍである。これに対して、本実施形態における回路基板２におけるチップ１ａを接着していない側の外側電極５は、図３（ｂ）に示すように面配置されている。このため、外側電極５のピッチをチップ側電極３のピッチより大きくすることができ、例えば３００μｍ以上の電極ピッチを確保することも可能である。
【００４０】
これにより、ウエハレベルバーンインに使用するプロービング治具のピッチも従来の１００〜１５０μｍより大きくすることができる。これにより、特殊なプロービング治具が不要となり、プロービング治具のコストダウンが可能になる。
【００４１】
また、マザーボード上に半導体装置を接続する電極のピッチも長くすることができるため、マザーボードとしてファインラインが形成された高価なビルドアップ基板を用いる必要がなくなり、コストダウンにつながる。
（他の実施形態）
なお、本実施形態ではチップ１ａのチップ側電極３および回路基板２の回路基板側電極４を、それぞれが形成された面に対して平坦になるように構成したが、これに限らず、チップ側電極と回路基板側電極とが接触する同時に、電極が形成されていない部分も接触するように構成すればよい。例えば、チップ側電極３を凹形状に形成し、回路基板側電極４をチップ側電極３に対応する凸形状に形成してもよい。
【図面の簡単な説明】
【図１】実施形態の半導体装置の全体構成を示す断面図である。
【図２】図１に示す半導体装置の製造方法を示す工程図である。
【図３】（ａ）はチップ側電極の配置を示す半導体チップの底面図であり、（ｂ）は外側電極の配置を示す回路基板の底面図である。
【図４】従来技術の半導体装置の構成を示す断面図である。
【図５】従来技術の半導体装置の構成を示す断面図である。
【符号の説明】
１…ウエハ、１ａ…半導体チップ、２…回路基板、３…第１の電極（チップ側電極）、４…第２の電極（回路基板側電極）。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device mounted on a printed circuit board and a method for manufacturing the same, and particularly to a chip size package having almost the same size as a chip.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, a CSP (chip size package) having a size almost equal to or slightly larger than a semiconductor chip is known as a miniaturization of a multi-terminal IC package. The CSP is packaged for each chip cut out from the wafer. FIG. 4 shows the structure of two types of CSPs in the conventional structure, and the electrode bonding of the CSP is generally performed by wire bonding shown in FIG. 4A or flip chip shown in FIG. 4B.
[0003]
The manufacturing process of CSP which performs electrode bonding by wire bonding is performed as follows. First, the semiconductor chip J1a formed by cutting the wafer is die-mounted on the circuit board J2, and the chip-side electrode J3 and the circuit board-side electrode J4 are bonded and connected by an Au wire. Next, a resin J10 for sealing the chip J1a is applied and cured. Finally, the protruding electrode J7 is formed on the outer electrode J5 on the circuit board opposite to the chip mounting side.
[0004]
In addition, the manufacturing process of the CSP that performs electrode bonding by flip chip is performed as follows. First, the wafer on which the protruding electrode J3a is formed in advance on the chip side electrode J3 is cut to form the chip J1a, and the protruding electrode J3a and the circuit board side electrode J4 are connected by soldering or the like to connect the chip J1a to the circuit board. Assemble to J2. Next, a resin J10 for sealing the chip J1a is injected between the chip J1a and the circuit board J2 and cured. Finally, the protruding electrode J7 is formed on the opposite side of the circuit board J2 from the chip mounting side.
[0005]
As described above, the conventional CSP requires wire bonding, electrode bonding by flip chip, chip sealing by resin, and the like, and there is a problem that the assembly process becomes long and the package cost becomes high.
[0006]
In addition, there are semiconductor devices described in JP-A-9-82850 and JP-A-10-50772 for the purpose of reducing the cost of CSP. However, in the semiconductor device described in Japanese Patent Application Laid-Open No. 9-82850, the wiring forming process from the surface electrode on the chip to the external connection terminal portion and the process of sealing the chip surface with resin are separated, There is a problem that a process becomes long. Further, in the semiconductor device described in Japanese Patent Application Laid-Open No. 10-50772, external connection terminals extending outward from the surface electrodes on the chip must be formed one by one by wire bonding, and the bonding process takes time. There was a problem.
[0007]
On the other hand, Japanese Patent Application Laid-Open No. 8-335653 describes a semiconductor device that simultaneously performs wiring formation from a surface electrode on a chip to an external connection terminal and resin sealing of the chip surface. The structure of this semiconductor device is shown in FIG. In this semiconductor device, an auxiliary wiring board (circuit board) J2 in which a protruding electrode J4a is formed on a circuit board side electrode J4 and a chip J1a in which a chip side electrode J3 is formed are bonded via a heat-fusible polyimide resin J10. It is configured as follows. Thus, the chip-side electrode J3 and the circuit board-side electrode J4 are connected, and the gap between the chip J1a and the circuit board J2 is sealed by the heat-fusible polyimide resin J10.
[0008]
[Problems to be solved by the invention]
However, the semiconductor device described in JP-A-8-335653 has the following problems.
[0009]
That is, in addition to the circuit board J2, a heat-sealable polyimide resin J10 for resin sealing is required. Further, since the semiconductor chip J1a is bonded to the circuit board J2 for each chip, the productivity is low. Furthermore, since the circuit board side electrode J4 is constituted by a protruding electrode, when the circuit board side electrode J4 is connected to the chip side electrode J3 and the protruding electrode has a height variation, the protruding electrode too low On the contrary, the protruding electrode that is too high may be crushed and spread laterally when connected to the chip-side electrode, and may be short-circuited to the adjacent protruding electrode.
[0010]
In view of the above points, an object of the present invention is to provide a highly reliable semiconductor device and a manufacturing method thereof that can reduce manufacturing costs.
[0011]
In order to achieve the above object, according to the present invention, in the first aspect of the present invention, a wafer (1) having a plurality of flat first electrodes (3) formed on one surface, and a first electrode ( A step of preparing a circuit board (2) on which a plurality of flat second electrodes (4) corresponding to 3) are formed, and the first electrode (3) and the second electrode (4) are in contact with each other. In addition, a portion where the first electrode (3) is not formed on the electrode formation surface of the semiconductor chip (1a) and a portion where the second electrode (4) is not formed on the electrode formation surface of the circuit substrate (2). And the step of bringing the wafer (1) and the circuit board (2) into contact with each other, and heating the wafer (1) and the circuit board (2) after pressurizing the wafer (1) and the circuit board (2). ) And the second electrode (4) are brought into contact with, bonded to, or joined to, and on the electrode formation surface of the semiconductor chip (1a) By contacting or adhering a portion where the first electrode (3) is not formed and a portion where the second electrode (4) is not formed on the electrode formation surface of the circuit board (2), the wafer (1 ) And the circuit board (2), and after the bonding process, the wafer (1) and the circuit board (2) are cut into semiconductor chips (1a).
[0012]
Thus, by forming the first electrode (3) and the second electrode (4) in a flat shape, it is possible to prevent the height variation of the electrodes as in the protruding electrode. Thereby, it is possible to prevent an electrode connection failure. Moreover, the resin sealing of the semiconductor chip (1a) can be performed by the resin portion where the electrode of the circuit board (2) is not formed. Therefore, the bonding of the first electrode (3) and the second electrode (4) and the resin sealing of the semiconductor chip (1a) can be simultaneously performed without using a dedicated resin material for resin sealing. It becomes possible.
[0013]
Further, the circuit board (2) is formed from a thermoplastic resin material, a semiconductor chip (1a) and the circuit board (2) is that the are bonded by being heated after being pressurized, the circuit board (2 ) Can be satisfactorily bonded to the resin portion where the second electrode (4) is not formed and the portion where the electrode of the semiconductor chip (1a) is not formed. Specifically, polyimide can be used as the thermoplastic resin.
[0015]
In this way, productivity is improved by assembling every wafer (1) and then cutting into chips, instead of assembling the circuit board (2) for each chip (1a), thereby reducing the package cost. Can be lowered.
[0016]
In addition, the code | symbol in the bracket | parenthesis of each said means is an example which shows a corresponding relationship with the specific means as described in embodiment mentioned later.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments to which the present invention is applied will be described below with reference to the drawings.
[0018]
First, the configuration of the semiconductor device according to the present embodiment will be described with reference to FIG. FIG. 1 is a cross-sectional view showing a schematic configuration of a semiconductor device. Note that the semiconductor device in this embodiment is of a CSP (chip size package) type.
[0019]
The semiconductor device 10 is formed of a semiconductor chip 1a and a circuit board 2. The semiconductor chip 1a is formed by cutting a wafer, and a plurality of first electrodes (chip side electrodes) 3 are formed on one surface thereof. A plurality of second electrodes (circuit board side electrodes) 4 corresponding to the chip side electrodes 3 are formed on the surface of the circuit board 2 to which the chip 1a is bonded. Both the chip-side electrode 3 and the circuit board-side electrode 4 are formed so as to be flat with respect to the surface on which each is formed.
[0020]
Further, a flat outer electrode 5 is formed on the opposite side of the circuit board 2 from the chip bonding side, and an internal wiring 6 for electrically connecting the circuit board side electrode 4 and the outer electrode 5 is provided on the circuit board 2. Is formed inside. The outer electrode 5 is formed with a protruding electrode 7 for connection to a printed circuit board which is a mother board.
[0021]
The circuit board 2 is formed from, for example, a thermoplastic resin material. In this embodiment, the circuit board 2 is formed from a polyimide resin. In the present embodiment, the thickness of the circuit board 2 is 200 μm. The chip side electrode 3 is made of, for example, Al, and the circuit board side electrode 4 is made of, for example, Au.
[0022]
The chip 1a and the circuit board 2 are connected so that the chip side electrode 3 and the circuit board side electrode 4 face each other. At this time, the surface of the chip 1a on which no electrode is formed and the resin on the circuit board surface are directly bonded.
[0023]
Next, a method for manufacturing the semiconductor device 10 having the above configuration will be described with reference to FIG. FIG. 2 shows a manufacturing process of the semiconductor device according to this embodiment.
[0024]
First, as shown in FIG. 2A, a wafer 1 on which a plurality of chip-side electrodes 3 that are not cut into chips is formed, and a circuit on which circuit board-side electrodes 4 corresponding to the chip-side electrodes 3 are formed. A substrate 2 is prepared.
[0025]
Next, as shown in FIG. 2B, the wafer 1 and the circuit board 2 are brought into contact with each other by aligning the positions of the electrodes 3 and 4. At this time, the electrodes of the wafer 1 and the circuit board 2 are in contact with each other, and a portion where the electrode on the wafer surface is not formed and a resin portion where the electrode on the circuit board surface is not formed are in contact. .
[0026]
Next, pressure is applied so as to sandwich the wafer 1 and the circuit board 2. At this time, since the outer electrode 5 of the circuit board 2 is formed flat as described above, it is easy to perform a pressing operation. Then, heating is performed in a state where pressure is applied to the wafer 1 and the circuit board 2. Thereby, the chip side electrode 3 of the chip 1a in the wafer is connected to the circuit board side electrode 4 formed on the surface of the circuit board. Specifically, if the chip side electrode 3 is Al or Au and the circuit board side electrode 4 is Au as in this embodiment, the connection between the electrodes is formed by solid phase diffusion of Al and Au or Au. Is done. Further, the chip side electrode 3 and the circuit board side electrode 4 can be made of a metal other than Al or Au, and at least one of them can be connected with a conductive adhesive.
[0027]
Since the circuit board 2 is made of a thermoplastic resin, it is softened by heating, and the resin portion of the circuit board 2 and the protective film on the surface of the chip 1a are bonded. Since organic substances such as polyimide resin used as the circuit board 2 in this embodiment have a functional group, the functional group approaches the atoms of the protective film on the chip surface when the circuit board 2 is heated. It is considered that a state is created and chemical bonds are easily obtained. Thus, by bonding the circuit board 2 and the chip 1a, the chip surface is covered with the resin, and the chip sealing with the resin can be performed simultaneously with the electrode connection.
[0028]
At this time, even if the chip side electrode 3 on the wafer 1 and the circuit board side electrode 4 on the circuit board 2 can be aligned at room temperature, the linear expansion coefficient between the wafer 1 and the circuit board 2 after heating is increased. Since they are different, positional deviation between the chip side electrode 3 and the circuit board side electrode 4 occurs. On the other hand, in this embodiment, the wafer 1 and the circuit board 2 are sandwiched and pressurized at room temperature and then heated, so that the positional shift due to the difference in displacement due to the mutual heat is suppressed to a level with no problem.
[0029]
Further, the circuit board 2 is usually deformed due to warpage or the like, and the position of the flat electrode 4 formed on the circuit board 2 may vary vertically. Also in this case, the wafer 1 and the circuit board 2 are sandwiched and pressurized, and then heated to soften the circuit board 2 and eliminate deformation such as warping. The chip side electrode 3 and the circuit board side electrode 4 A good connection with can be obtained.
[0030]
The heating temperature in the above steps is 100 to 300 ° C., particularly preferably 150 to 250 ° C., the pressing time is 30 seconds to 30 minutes, and the pressing force is about 5 to 50 kg / cm 2 .
[0031]
Thereafter, as shown in FIG. 2C, if necessary for connection to a printed circuit board which is a mother board, a protruding electrode 7 made of a solder bump is formed on the outer electrode 5 on the circuit board side to which the wafer 1 is not bonded. Form. The protruding electrode 7 is formed using, for example, a solder ball.
[0032]
After the above steps are completed, as shown in FIG. 2D, the wafer 1 is cut in chip units (broken lines in FIG. 2D), so that a plurality of CSP type semiconductor devices 10 can be obtained. .
[0033]
As described above, according to the semiconductor device of the present embodiment, since the assembly is performed in units of wafers, not in units of chips cut out from the wafer, productivity in semiconductor device manufacturing can be improved. The package cost can be reduced.
[0034]
Further, by forming the chip-side electrode and the circuit board-side electrode as flat electrodes instead of protruding electrodes, it is possible to eliminate connection problems due to variations in electrode height.
[0035]
Further, by bonding the chip surface on which the electrode is not formed and the resin part on the circuit board surface, it is possible to realize the resin sealing of the chip simultaneously with the electrode connection, so that a resin material for resin sealing is not necessary. .
[0036]
By the way, in the semiconductor device described in the above-mentioned Japanese Patent Application Laid-Open No. 8-335653, the thickness of the circuit board to which the chip is bonded is as thin as 50 to 150 μm. For this reason, when connecting to the printed circuit board which is a mother board by soldering etc. via the protruding electrode formed on the side opposite to the chip bonding side in the circuit board, the linear expansion coefficient of the printed circuit board and the chip (Si) If the difference is too large and a thermal cycle is applied, there is a problem that the solder connection part connecting the electrode of the circuit board and the electrode of the printed board cracks and opens.
[0037]
On the other hand, in the present embodiment, the thickness of the circuit board that is positioned between the chip and the printed board is 200 μm or more. By doing in this way, the distortion which generate | occur | produces in said solder joint part by the difference in the linear expansion coefficient of the printed circuit board which is a chip | tip and a motherboard can be reduced.
[0038]
Next, the arrangement of the chip-side electrode 3 of the chip 1a and the arrangement of the outer electrode 5 formed on the side opposite to the chip bonding side of the circuit board 2 will be described with reference to FIG. FIG. 3A is a bottom view of the chip 1 a showing the arrangement of the chip-side electrode 3, and FIG. 3B is a bottom view of the circuit board 2 showing the arrangement of the outer electrode 5.
[0039]
The chip-side electrode 3 on the chip 1a in the wafer 1 is usually disposed on the outer peripheral edge of the chip 1a as shown in FIG. 3A, and the electrode pitch is usually 100 to 150 μm. On the other hand, the outer electrode 5 on the side where the chip 1a is not bonded to the circuit board 2 in the present embodiment is arranged as shown in FIG. For this reason, the pitch of the outer electrodes 5 can be made larger than the pitch of the chip-side electrodes 3, and for example, an electrode pitch of 300 μm or more can be secured.
[0040]
Thereby, the pitch of the probing jig used for wafer level burn-in can be made larger than the conventional 100 to 150 μm. This eliminates the need for a special probing jig and enables the cost of the probing jig to be reduced.
[0041]
In addition, since the pitch of the electrodes connecting the semiconductor device on the mother board can be increased, it is not necessary to use an expensive build-up board on which a fine line is formed as the mother board, leading to cost reduction.
(Other embodiments)
In the present embodiment, the chip side electrode 3 of the chip 1a and the circuit board side electrode 4 of the circuit board 2 are configured so as to be flat with respect to the surface on which they are formed. What is necessary is just to comprise so that the part in which the electrode is not formed may contact simultaneously with an electrode and the circuit board side electrode contacting. For example, the chip side electrode 3 may be formed in a concave shape, and the circuit board side electrode 4 may be formed in a convex shape corresponding to the chip side electrode 3.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing an overall configuration of a semiconductor device according to an embodiment.
2 is a process diagram showing a manufacturing method of the semiconductor device shown in FIG. 1; FIG.
FIG. 3A is a bottom view of a semiconductor chip showing the arrangement of chip-side electrodes, and FIG. 3B is a bottom view of a circuit board showing the arrangement of outer electrodes.
FIG. 4 is a cross-sectional view showing a configuration of a conventional semiconductor device.
FIG. 5 is a cross-sectional view showing a configuration of a conventional semiconductor device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Wafer, 1a ... Semiconductor chip, 2 ... Circuit board, 3 ... 1st electrode (chip side electrode), 4 ... 2nd electrode (circuit board side electrode).

Claims (1)

一面に複数の第１の電極（３）が形成される面に対して平坦に形成されたウエハ（１）と、一面に前記第１の電極（３）に対応する複数の第２の電極（４）が形成される面に対して平坦に形成された回路基板（２）とを用意する工程と、
前記第１の電極（３）と前記第２の電極（４）とが接触するとともに、前記ウエハ（１）の電極形成面における前記第１の電極（３）が形成されていない部分と前記回路基板（２）の電極形成面における前記第２の電極（４）が形成されていない部分とが接触するように、前記ウエハ（１）と前記回路基板（２）と接触させる工程と、
前記ウエハ（１）と前記回路基板（２）とを加圧した後で加熱して、前記第１の電極（３）と前記第２の電極（４）とを接触、接着または接合させるとともに、前記ウエハ（１）の電極形成面における前記第１の電極（３）が形成されていない部分と前記回路基板（２）の電極形成面における前記第２の電極（４）が形成されていない部分とを接触または接着させることにより、前記ウエハ（１）と前記回路基板（２）とを接着させる工程と、
前記接着工程の後、前記ウエハ（１）および前記回路基板（２）とを半導体チップ（１ａ）単位に切断する工程とを備える半導体装置の製造方法。A wafer (1) formed flat with respect to a surface on which a plurality of first electrodes (3) are formed on one surface, and a plurality of second electrodes (one corresponding to the first electrode (3) on one surface) 4) preparing a circuit board (2) formed flat with respect to the surface on which the surface is formed ;
The portion where the first electrode (3) and the second electrode (4) are in contact with each other and the first electrode (3) is not formed on the electrode forming surface of the wafer (1) and the circuit Contacting the wafer (1) and the circuit board (2) such that a portion of the electrode formation surface of the substrate (2) where the second electrode (4) is not formed is in contact;
Heating the wafer (1) and the circuit board (2) after pressurizing them to contact, bond or bond the first electrode (3) and the second electrode (4); A portion where the first electrode (3) is not formed on the electrode formation surface of the wafer (1) and a portion where the second electrode (4) is not formed on the electrode formation surface of the circuit substrate (2). Bonding the wafer (1) and the circuit board (2) by contacting or bonding
A method of manufacturing a semiconductor device comprising: a step of cutting the wafer (1) and the circuit board (2) into units of a semiconductor chip (1a) after the bonding step.
JP19054699A 1999-07-05 1999-07-05 Manufacturing method of semiconductor device Expired - Fee Related JP3915325B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19054699A JP3915325B2 (en) 1999-07-05 1999-07-05 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19054699A JP3915325B2 (en) 1999-07-05 1999-07-05 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
JP2001024086A JP2001024086A (en) 2001-01-26
JP3915325B2 true JP3915325B2 (en) 2007-05-16

Family

ID=16259887

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19054699A Expired - Fee Related JP3915325B2 (en) 1999-07-05 1999-07-05 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JP3915325B2 (en)

Also Published As

Publication number Publication date
JP2001024086A (en) 2001-01-26

Similar Documents

Publication Publication Date Title
JP3297254B2 (en) Semiconductor package and manufacturing method thereof
KR0172203B1 (en) Semiconductor package and its manufacturing method
JP2001308220A (en) Semiconductor package and its manufacturing method
JP3180800B2 (en) Semiconductor device and manufacturing method thereof
KR19990082715A (en) Semiconductor device
JPH07245360A (en) Semiconductor package and its manufacture
JPH1041615A (en) Substrate for mounting semiconductor chip and method for mounting semiconductor chip
WO2000019514A1 (en) Semiconductor package and flip-chip bonding method therefor
JP3705159B2 (en) Manufacturing method of semiconductor device
JP2626621B2 (en) Method for manufacturing semiconductor device
KR100379823B1 (en) Manufacturing method of semiconductor integrated circuit device
JP3915325B2 (en) Manufacturing method of semiconductor device
JPH10154726A (en) Semiconductor device and its manufacture
JPH10125734A (en) Semiconductor unit and manufacturing method thereof
JP3332555B2 (en) Semiconductor device and manufacturing method thereof
JP4035949B2 (en) Wiring board, semiconductor device using the same, and manufacturing method thereof
JP3572254B2 (en) Circuit board
JP3456576B2 (en) Semiconductor device and manufacturing method thereof
JPH11163054A (en) Structure of semiconductor device and its manufacture
JPH11340278A (en) Resin sheet for mounting semiconductor device, flip chip mounting method and circuit board
JP3547270B2 (en) Mounting structure and method of manufacturing the same
JP2002237566A (en) Three-dimensional mounting structure of semiconductor device, and method of manufacturing the same
JPH0236556A (en) Pin grid array and mounting of semiconductor element
JPH0992651A (en) Semiconductor element and connection method
JP3637438B2 (en) Wiring board manufacturing method

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20050823

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20060201

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20060808

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20061003

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20061024

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20061218

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20070116

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20070129

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110216

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120216

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130216

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140216

Year of fee payment: 7

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees