JP3705159B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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JP3705159B2
JP3705159B2 JP2001176141A JP2001176141A JP3705159B2 JP 3705159 B2 JP3705159 B2 JP 3705159B2 JP 2001176141 A JP2001176141 A JP 2001176141A JP 2001176141 A JP2001176141 A JP 2001176141A JP 3705159 B2 JP3705159 B2 JP 3705159B2
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electrode
circuit board
chip
wafer
semiconductor
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JP2002368159A (en
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俊夫 鈴木
宏司 近藤
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Denso Corp
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Denso Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、プリント回路基板上に実装される半導体装置の製造方法に関するものであり、特にチップとほぼ同じ大きさを有するチップ・サイズ・パッケージ（ＣＳＰ）に用いられるものである。
【０００２】
【従来の技術】
従来、多端子のＩＣパッケージを小型化するものとして、半導体チップとほぼ同等あるいはわずかに大きいサイズのＣＳＰがある。ＣＳＰはウェハから切り出したチップ毎にパッケージするものである。図３は従来構造における２種類のＣＳＰの概略断面構成を示しており、ＣＳＰの電極接合は一般的に図３（ａ）に示すワイヤボンディングあるいは図３（ｂ）に示すフリップチップなどにより行われる。
【０００３】
ワイヤボンディングによる電極接合を行うＣＳＰの製造工程は、次のように行われる。まず、ウェハをカットして形成した半導体チップＪ１を回路基板Ｊ２上にダイマウントし、チップ側電極Ｊ３と回路基板側電極Ｊ４とをＡｕワイヤＪ５によりボンディングして接続する。次にチップＪ１を封止するための樹脂Ｊ６を塗布して硬化させる。最後に回路基板Ｊ２におけるチップ搭載側の反対側の外側電極Ｊ７上に突起電極Ｊ８を形成する。
【０００４】
また、フリップチップによる電極接合を行うＣＳＰの製造工程は、次のように行われる。まず、予めチップ側電極Ｊ３上に突起電極Ｊ３ａを形成したウェハをカットしてチップＪ１を形成し、突起電極Ｊ３ａと回路基板側電極Ｊ４とをはんだ付け等で接続することによりチップＪ１を回路基板Ｊ２に組み付ける。次に、チップＪ１を封止するための樹脂Ｊ６をチップＪ１と回路基板Ｊ２との間に注入して硬化させる。最後に回路基板Ｊ２におけるチップ搭載側の反対側の外側電極Ｊ７上に突起電極Ｊ８を形成する。
【０００５】
以上のように、従来のＣＳＰでは、ワイヤボンディング、フリップチップ等による電極接合と、樹脂によるチップ封止等が必要であり、組み付け工程が長くなり、パッケージコストが高くなるという問題があった。
【０００６】
また、ＣＳＰのコストダウンを目的として特開平９−８２８５０号公報および特開平１０−５０７７２号公報に記載されている半導体装置がある。しかしながら、特開平９−８２８５０号公報に記載されている半導体装置では、チップ上の表面電極から外部接続端子部までの配線形成工程とチップ表面を樹脂で封止する工程とが別になり、全体の工程が長くなるという問題がある。
【０００７】
また、特開平１０−５０７７２号公報に記載されている半導体装置では、チップ上の表面電極から外側に延びる外部接続端子をワイヤボンディングにより１つずつ形成しなければならず、ボンディング工程に時間がかかるという問題があった。
【０００８】
これに対し、特開平８−３３５６５３号公報において、チップ上の表面電極から外部接続端子までの配線形成とチップ表面の樹脂封止とを同時に実施する半導体装置が記載されている。この半導体装置の構成を図４に示す。
【０００９】
この半導体装置は、回路基板側電極Ｊ４上に突起電極Ｊ４ａを形成した補助配線板（回路基板）Ｊ２とチップ側電極Ｊ３を形成したチップＪ１とを熱融着性ポリイミド樹脂Ｊ６を介して接着するように構成されている。これにより、チップ側電極Ｊ３と回路基板側電極Ｊ４と接続するとともに、熱融着性ポリイミド樹脂Ｊ６によってチップＪ１と回路基板Ｊ２との間隙を封止するものである。
【００１０】
しかしながら、上記特開平８−３３５６５３号公報に記載された半導体装置では、回路基板Ｊ２以外に樹脂封止のための熱融着性ポリイミド樹脂Ｊ６が必要であり、また、回路基板Ｊ２への半導体チップＪ１の接着が１チップ毎に行われるため、生産性が低いという問題があった。
【００１１】
上記した各従来公報における工程の手間や生産性の低下といった問題を解決するものとして、特開２００１−２４０８６号公報に記載の半導体装置が提案されている。
【００１２】
このものは、例えば熱可塑性樹脂材料で形成された回路基板の表面に平坦な電極を形成し、この回路基板をウェハに加圧・加熱することにより、ウェハ側の各チップに形成された平坦な電極と回路基板側の電極とを接続すると同時に、電極が形成されていない部分にてチップ表面（ウェハ表面）と回路基板の表面の樹脂部とを接着することにより、チップ表面の樹脂封止を同時に実施するものである。
【００１３】
【発明が解決しようとする課題】
しかしながら、本発明者等の検討によれば、上記特開２００１−２４０８６号公報に記載の半導体装置では、チップ側電極と回路基板側電極とが接触するのと同時に、電極が形成されていない部分にてチップ表面と回路基板の表面とが接触するため、チップ側電極と回路基板側電極との間に、回路基板表面の軟化した樹脂が侵入して良好な電極接続ができない場合が生じることがわかった。
【００１４】
本発明は上記問題に鑑み、製造コストが低減でき、かつ、信頼性の高い電極接続を実現することのできる半導体装置の製造方法を提供することを目的とする。
【００１５】
【課題を解決するための手段】
上記目的を達成するために、請求項１に記載の発明では、一面（１１）に第１の電極（３）が形成され第１の電極の表面に前記一面から突出する突起電極（８）が形成された半導体基板（１０）と、一面（２ａ）に第１の電極に対応する第２の電極（４）が形成された樹脂よりなる回路基板（２）とを用意する工程と、 半導体基板の前記一面と回路基板の前記一面とを対向させ、突起電極と第２の電極とを接触させる工程と、この工程の後、半導体基板と回路基板とを加圧しながら加熱することにより、突起電極と第２の電極とを圧着するとともに、回路基板を構成する樹脂を軟化させ、半導体基板の前記一面における第１の電極が形成されていない部分と回路基板の前記一面における第２の電極が形成されていない部分とを接着し、半導体基板と回路基板とを接着する工程と、を備えることを特徴としている。
【００１６】
それによれば、チップ側電極である第１の電極（３）に突起電極（８）を形成し、まず、この突起電極と回路基板側電極である第２の電極（４）とを接触させた後に、電極が形成されていない部分にて半導体基板（１０）の表面（１１）と回路基板（２）の表面（２ａ）とを接触させるため、突起電極と第２の電極との間に回路基板表面の軟化した樹脂が侵入するのを防止することができる。
【００１７】
また、突起電極（８）と回路基板側電極である第２の電極（４）と接触させる工程の後に、電極が形成されていない部分にて半導体基板（１０）の表面（１１）と回路基板（２）の表面（２ａ）とを接触させる工程を行うことは、これら両工程を同時に行う場合に比べても、時間的にはほとんど大差なく行うことが可能である。
【００１８】
従って、本発明によれば、製造コストが低減でき、かつ、信頼性の高い電極接続を実現することのできる半導体装置（Ｓ１）の製造方法を提供することができる。
【００１９】
ここで、半導体基板は、ウェハ（１０）でもチップ（１）でも良い。ウェハの場合には、半導体基板と回路基板とを接着する工程の後に、接着した両基板をチップ単位に切断すればよい。
【００２０】
また、請求項１に記載の発明では、半導体基板（１０）と回路基板（２）とを接着する工程では、半導体基板と回路基板とを加圧した後に、この加圧状態を保持しながら両基板の加熱を行っている。
【００２１】
上記加圧と加熱を同時に行うと、半導体基板（１０）と回路基板（２）との線膨張係数の相違に伴う両基板（２、１０）間の熱による変位の差により、当該両基板の間で位置ずれが発生しやすい。
【００２２】
その点、本発明によれば、両基板（２、１０）を加圧して押し付け合い互いに拘束された状態とした後に、加熱するので、両基板の熱による変位の差による位置ずれを、確実に抑制することができる。
【００２５】
なお、上記各手段の括弧内の符号は、後述する実施形態に記載の具体的手段との対応関係を示す一例である。
【００２６】
【発明の実施の形態】
以下、本発明を図に示す実施形態について説明する。図１は本実施形態に係る半導体装置Ｓ１の全体構成を示す図であり、（ａ）は概略断面図、（ｂ）は（ａ）のＡ矢視図（（ａ）の下側から見たもの）である。なお、この半導体装置Ｓ１はＣＳＰ（チップ・サイズ・パッケージ）タイプのものである。
【００２７】
半導体装置Ｓ１は、シリコン等の半導体よりなる半導体チップ１および樹脂よりなる回路基板２から形成される。半導体チップ１は後述するウェハ１０（図２参照）をカットすることにより形成されるものであり、その一面１ａには複数の第１の電極（チップ側電極）３が形成されている。
【００２８】
ここで、チップ側電極３は、半導体チップ１の一面１ａに対して平坦になるように形成されている。また、回路基板２におけるチップ１が接着される面２ａ側には、チップ側電極３に対応する複数の第２の電極（回路基板側電極）４が形成されている。
【００２９】
また、回路基板２におけるチップ接着側の反対側の面２ｂにも平坦な外側電極５が形成されており、回路基板２内には、これらの回路基板側電極４および外側電極５を電気的に接続するための内部配線６が形成されている。また、外側電極５にはマザーボードであるプリント基板（図示せず）に接続するための半田等よりなるバンプ７が形成されている。
【００３０】
回路基板２は、例えば熱可塑性樹脂材料から形成され、本例では、ポリイミド樹脂から形成されている。また、チップ側電極３は例えばＡｌから形成され、回路基板側電極４は例えばＳｎやＡｕ等の金属材料から形成されている。
【００３１】
ここにおいて、チップ側電極（第１の電極）３の表面には、半導体チップ１の一面１ａよりも回路基板４側へ突出する突起電極８が形成されている。この突起電極８は、例えば無電解メッキにより形成されたＮｉ−Ａｕバンプ（Ｎｉを芯材とし、Ｎｉ表面をＡｕで被覆したもの）からなるものにできる。
【００３２】
そして、この突起電極８と回路基板側電極４とが接触、接着または接合している。本例では、突起電極８の表面を構成するＡｕと、回路基板側電極４を構成するＳｎまたはＡｕとが固相拡散により接続されている。
【００３３】
また、半導体チップ１の一面１ａにおけるチップ側電極３が形成されていない部分（以下、半導体チップ１の電極非形成部という）と回路基板２の一面２ａにおける回路基板側電極４が形成されていない部分（以下、回路基板２の電極非形成部という）とが直接接着して、半導体チップ１と回路基板２とが接着されている。
【００３４】
半導体チップ１の電極非形成部は、図示しないが無機物（窒化膜等）や有機物等の保護膜にて被覆されている。一方、回路基板２の電極非形成部は、上記した熱可塑性樹脂等の樹脂材料よりなる。そして、両電極非形成部の対向部において、回路基板２の一面２ａ側の樹脂が、回路基板側電極４よりもチップ１側へ盛り上がってチップ１の電極非形成部に直接接着するとともに、電極３、４、８の接続部を封止している。
【００３５】
次に、上記構成の半導体装置Ｓ１の製造方法を図２に基づいて説明する。図２は、本実施形態における半導体装置の製造工程を示す概略断面図である。まず、図２（ａ）に示す様に、上記ウェハ（本発明でいう半導体基板）１０と回路基板２とを用意する。
【００３６】
ウェハ１０は、半導体チップ１としてチップ単位にカットされていないもので、その一面１１（上記半導体チップ１の一面１ａに相当する）には、複数のチップ側電極３が形成されている。また、ウェハ１０の一面１１におけるチップ側電極３が形成されていない部分（ウェハ１０の電極非形成部）は、上記の半導体チップ１の電極非形成部に相当する部位であり、上記した保護膜が設けられている。
【００３７】
このウェハ１０において、チップ側電極３の表面には、ウェハ１０の一面１１から突出する突起電極８が形成されている。一方、回路基板２の一面２ａには、チップ側電極３に対応する複数の回路基板側電極４が形成されている。
【００３８】
なお、ウェハ１０は、通常の半導体プロセスを経て製造することができ、突起電極８も、この半導体プロセスにおけるメッキプロセスにより、例えば上記Ｎｉ−Ａｕバンプとして容易に形成することができる。
【００３９】
次に、図２（ｂ）に示す様に、チップ側電極３と回路基板側電極４との位置を合わせながら、ウェハ１０の一面１１と回路基板の一面２ａとを対向させ、突起電極８と回路基板側電極４とを接触させる（突起電極接触工程）。
【００４０】
次に、図２（ｃ）に示す様に、ウェハ１０と回路基板２とを挟み込むようにして加圧する。この際、上記のように回路基板２の外側電極５は平坦に形成されているので、加圧作業を行いやすくなっている。そして、ウェハ１０と回路基板２に圧力をかけた状態で加熱を行う（加圧・加熱工程）。
【００４１】
この加圧・加熱によって、ウェハ１０内のチップ側電極３に形成された突起電極８と回路基板２に形成された回路基板側電極４とが圧着され、両電極４、８は、接触、接着または接合の形態にて電気的に接続される。具体的には、本実施形態のように突起電極８が表面をＡｕとしたＮｉ−Ａｕバンプであり、回路基板側電極４がＳｎ、Ａｕ等の金属材料であれば、ＡｕとＳｎもしくはＡｕ同士の固相拡散接合により電極同士の接続が形成される。
【００４２】
また、回路基板２は熱可塑性樹脂から形成されていることから上記加熱によって、軟化する。そして、加圧によって、回路基板２の電極非形成部の樹脂部分が、ウェハ１０側へ盛り上がり、ウェハ１０の電極非形成部に直接接着される。
【００４３】
ここで、本実施形態で回路基板２として用いているポリイミド樹脂等の有機物は官能基を有していることから、回路基板２を加熱する際に官能基がチップ表面（ウェハ表面）の保護膜の原子に接近して接合状態を作り、化学的な結合が得やすくなると考えられる。
【００４４】
このように、回路基板２とウェハ１０とを接着することにより、結果的に、チップ１の表面を樹脂で覆うことになり、電極４、８を接続すると同時に、当該電極接続部の樹脂による封止を実施することができる。
【００４５】
以上の加圧・加熱工程における加熱温度は１００〜３００℃で、特に望ましくは１５０〜２５０℃であり、加圧時間は３０秒〜３０分であり、加圧力は５００ｋＰａ〜５０００ｋＰａ程度である。
【００４６】
この後、図２（ｄ）に示す様に、マザーボードであるプリント基板への接続のために必要であれば、ウェハ１０を接着しない回路基板側の外側電極５上に半田等よりなるバンプ７を形成する。このバンプ７は例えばハンダボールを用いて形成する。そして、ウェハ１０及び回路基板２をチップ単位（図２（ｄ）中の破線）でカットすることにより、複数のＣＳＰタイプの半導体装置Ｓ１を得ることができる。
【００４７】
ところで、上記製造方法によれば、チップ側電極３に形成された突起電極８と回路基板側電極４とを接触させた後に、ウェハ１０及び回路基板２の電極非形成部にてウェハ表面と回路基板表面とを接触させるため、突起電極８と回路基板側電極４との間に回路基板表面の軟化した樹脂が侵入するのを防止することができる。
【００４８】
また、突起電極８と回路基板側電極４と接触させる工程（突起電極接触工程）の後に、両基板２、１０の電極非形成部にて、両基板２、１０の表面同士を接触させる工程（加圧・加熱工程）を行うことは、上記した特開２００１−２４０８６号公報のように、これら両工程を同時に行う場合に比べても、時間的にはほとんど大差なく行うことが可能である。
【００４９】
さらに、電極が形成されていないチップ表面と回路基板表面の樹脂部とを接着することにより、電極接続と同時にチップの樹脂封止を実現できるため、樹脂封止のための樹脂材料が不要となる。従って、本実施形態によれば、製造コストが低減でき、かつ、信頼性の高い電極接続を実現することのできる半導体装置Ｓ１の製造方法を提供することができる。
【００５０】
ここで、上記製造方法において、用いられる半導体基板としては、ウェハ１０でも切断後の半導体チップ１でも良い。本実施形態では、ウェハ単位で組み付けを行うので、ウェハから切り出したチップ単位で回路基板２に組み付ける場合に比べて、半導体装置製造における生産性を向上させることができ、パッケージコストを低減させることができる。
【００５１】
また、上記製造方法において、加圧・加熱工程では、加圧と加熱とを同時に行っても良いが、好ましくは、ウェハ１０と回路基板２とを挟み込んで加圧した後に、この加圧状態を保持しながらウェハ１０と回路基板２の加熱を行うことが望ましい。
【００５２】
これは、室温ではウェハ１０上のチップ側電極３と回路基板２上の回路基板側電極４との位置合わせができていても、加熱した後ではウェハ１０と回路基板２とは線膨張係数が異なるので、チップ側電極３と回路基板側電極４との位置ずれが発生してしまうためである。
【００５３】
その点、室温でウェハ１０と回路基板２を挟み込んで加圧し、互いに拘束された状態とした後に加熱するようにすれば、両基板２、１０の熱による変位の差による位置ずれを、問題ないレベルに抑制することができる。
【００５４】
さらに通常、回路基板２には反りなどによる変形が発生しており、回路基板２上に形成した回路基板側電極４の位置が上下にばらつくことがある。これについても、ウェハ１０と回路基板２を挟み込んで加圧し、この後に加熱することで回路基板２を軟らかくして、反りなどの変形をなくすことができ、チップ側電極３の上の突起電極８と回路基板側電極４との良好な接続を得ることができる。
【００５５】
また、本実施形態では、上記図１に示す様に、少なくとも一面１ａ側に第１の電極３が形成された半導体チップ１と、少なくとも一面２ａ側に第１の電極３に対応する第２の電極４が形成された樹脂よりなる回路基板２とを備え、第１の電極３にはチップ１の一面１ａよりも回路基板２側へ突出する突起電極８が形成されており、突起電極８と第２の電極４とが接触して電気的に接続されており、更に、回路基板２の電極非形成部が、第２の電極４よりも半導体チップ１側へ盛り上がった状態で半導体チップ１の電極非形成部に接着していることを特徴とする半導体装置Ｓ１が提供される。
【００５６】
この半導体装置Ｓ１によれば、半導体チップ１には、その一面１ａより突出する突起電極８が設けられているため、上記製造方法から明らかなように、樹脂よりなる回路基板２と半導体チップ１との接着において、突起電極８と回路基板側電極（第２の電極）４とを接触させた後に、電極非形成部における接着を行うことができる。
【００５７】
そのため、本実施形態によれば、製造コストが低減でき、かつ、信頼性の高い電極接続を実現することのできる半導体装置Ｓ１を提供することもできる。
【図面の簡単な説明】
【図１】本実施形態に係る半導体装置の全体構成を示す図であり、（ａ）は概略断面図、（ｂ）は（ａ）のＡ矢視図である。
【図２】図１に示す半導体装置の製造方法を示す工程図である。
【図３】従来技術の半導体装置の構成を示す断面図である。
【図４】従来技術の半導体装置の構成を示す断面図である。
【符号の説明】
１…半導体チップ、１ａ…半導体チップの一面、２…回路基板、
２ａ…回路基板の一面、３…第１の電極（チップ側電極）、
４…第２の電極（回路基板側電極）、８…突起電極、１０…ウェハ、
１１…ウェハの一面。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor device mounted on a printed circuit board, and particularly to a chip size package (CSP) having almost the same size as a chip.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, there is a CSP having a size substantially equal to or slightly larger than that of a semiconductor chip as a multi-terminal IC package. The CSP is packaged for each chip cut out from the wafer. FIG. 3 shows a schematic cross-sectional configuration of two types of CSPs in a conventional structure, and electrode bonding of the CSP is generally performed by wire bonding shown in FIG. 3 (a) or flip chip shown in FIG. 3 (b). .
[0003]
The manufacturing process of CSP which performs electrode bonding by wire bonding is performed as follows. First, the semiconductor chip J1 formed by cutting the wafer is die-mounted on the circuit board J2, and the chip-side electrode J3 and the circuit board-side electrode J4 are bonded and connected by the Au wire J5. Next, a resin J6 for sealing the chip J1 is applied and cured. Finally, the protruding electrode J8 is formed on the outer electrode J7 opposite to the chip mounting side in the circuit board J2.
[0004]
In addition, the manufacturing process of the CSP that performs electrode bonding by flip chip is performed as follows. First, a wafer on which the protruding electrode J3a is formed in advance on the chip side electrode J3 is cut to form a chip J1, and the protruding electrode J3a and the circuit board side electrode J4 are connected by soldering or the like to connect the chip J1 to the circuit board. Assemble to J2. Next, a resin J6 for sealing the chip J1 is injected between the chip J1 and the circuit board J2 and cured. Finally, the protruding electrode J8 is formed on the outer electrode J7 opposite to the chip mounting side in the circuit board J2.
[0005]
As described above, the conventional CSP requires wire bonding, electrode bonding by flip chip, chip sealing with resin, and the like, and has a problem that the assembly process becomes long and the package cost increases.
[0006]
In addition, there are semiconductor devices described in JP-A-9-82850 and JP-A-10-50772 for the purpose of reducing the cost of CSP. However, in the semiconductor device described in Japanese Patent Application Laid-Open No. 9-82850, the wiring forming process from the surface electrode on the chip to the external connection terminal portion and the process of sealing the chip surface with resin are separated, There is a problem that a process becomes long.
[0007]
Further, in the semiconductor device described in Japanese Patent Laid-Open No. 10-50772, external connection terminals extending outward from the surface electrode on the chip must be formed one by one by wire bonding, and the bonding process takes time. There was a problem.
[0008]
On the other hand, Japanese Patent Application Laid-Open No. 8-335653 describes a semiconductor device that simultaneously performs wiring formation from a surface electrode on a chip to an external connection terminal and resin sealing on the chip surface. The structure of this semiconductor device is shown in FIG.
[0009]
In this semiconductor device, an auxiliary wiring board (circuit board) J2 on which a protruding electrode J4a is formed on a circuit board side electrode J4 and a chip J1 on which a chip side electrode J3 is formed are bonded via a heat-fusible polyimide resin J6. It is configured as follows. Thus, the chip-side electrode J3 and the circuit board-side electrode J4 are connected, and the gap between the chip J1 and the circuit board J2 is sealed with the heat-fusible polyimide resin J6.
[0010]
However, the semiconductor device described in the above-mentioned Japanese Patent Application Laid-Open No. 8-335653 requires a heat-sealable polyimide resin J6 for resin sealing in addition to the circuit board J2, and a semiconductor chip to the circuit board J2. Since bonding of J1 is performed for each chip, there is a problem that productivity is low.
[0011]
A semiconductor device described in Japanese Patent Application Laid-Open No. 2001-24086 has been proposed as a solution to the above-described problems such as process labor and productivity reduction in each of the above conventional publications.
[0012]
For example, a flat electrode is formed on the surface of a circuit board made of, for example, a thermoplastic resin material, and this circuit board is pressed and heated on the wafer, thereby forming a flat electrode formed on each chip on the wafer side. At the same time that the electrode is connected to the electrode on the circuit board side, the chip surface (wafer surface) and the resin part on the surface of the circuit board are bonded to each other at the portion where the electrode is not formed, thereby sealing the resin on the chip surface. It is performed at the same time.
[0013]
[Problems to be solved by the invention]
However, according to the study by the present inventors, in the semiconductor device described in Japanese Patent Laid-Open No. 2001-24086, a portion where no electrode is formed at the same time when the chip side electrode and the circuit board side electrode are in contact with each other. Since the chip surface and the surface of the circuit board come into contact with each other, the softened resin on the circuit board surface may invade between the chip side electrode and the circuit board side electrode, and a good electrode connection may not be possible. all right.
[0014]
In view of the above problems, it can be reduced in manufacturing cost, and aims to provide a method of manufacturing a semiconductor device capable of realizing a highly reliable electrode connection.
[0015]
[Means for Solving the Problems]
In order to achieve the above object, in the first aspect of the present invention, the first electrode (3) is formed on one surface (11), and the protruding electrode (8) protruding from the one surface is formed on the surface of the first electrode. A step of preparing a formed semiconductor substrate (10) and a circuit substrate (2) made of a resin having a second electrode (4) corresponding to the first electrode formed on one surface (2a); A step of making the one surface of the circuit board and the one surface of the circuit board face each other and bringing the protruding electrode and the second electrode into contact with each other, and after this step, heating the semiconductor substrate and the circuit board while applying pressure, thereby forming the protruding electrode And the second electrode are pressure-bonded, and the resin constituting the circuit board is softened so that the first electrode on the one surface of the semiconductor substrate is not formed and the second electrode on the one surface of the circuit board is formed. Glue the parts that are not, the semiconductor And a step of bonding the substrate and the circuit board.
[0016]
According to this, the protruding electrode (8) is formed on the first electrode (3) which is the chip side electrode, and first, the protruding electrode and the second electrode (4) which is the circuit board side electrode are brought into contact with each other. Later, in order to bring the surface (11) of the semiconductor substrate (10) and the surface (2a) of the circuit board (2) into contact with each other at a portion where no electrode is formed, a circuit is formed between the protruding electrode and the second electrode. Intrusion of the softened resin on the substrate surface can be prevented.
[0017]
Further, after the step of bringing the protruding electrode (8) into contact with the second electrode (4) which is the circuit board side electrode, the surface (11) of the semiconductor substrate (10) and the circuit board at a portion where the electrode is not formed. Performing the step of contacting the surface (2a) of (2) can be performed with almost no difference in time as compared with the case where these two steps are performed simultaneously.
[0018]
Therefore, according to the present invention, it is possible to provide a method of manufacturing the semiconductor device (S1) that can reduce the manufacturing cost and realize highly reliable electrode connection.
[0019]
Here, the semiconductor substrate may be a wafer (10) or a chip (1). In the case of a wafer, after bonding the semiconductor substrate and the circuit board, the bonded substrates may be cut into chips.
[0020]
According to the first aspect of the present invention , in the step of bonding the semiconductor substrate (10) and the circuit board (2), after the semiconductor substrate and the circuit board are pressurized, both of them are held while maintaining the pressurized state. have you row the heating of the substrate.
[0021]
When the pressurization and heating are performed simultaneously, the difference in thermal displacement between the two substrates (2, 10) due to the difference in the linear expansion coefficient between the semiconductor substrate (10) and the circuit substrate (2) causes Misalignment is likely to occur.
[0022]
In that respect, according to the present invention, since both the substrates (2, 10) are pressed and pressed to be in a state of being constrained to each other and then heated, the displacement due to the difference in displacement due to the heat of both substrates can be reliably prevented. Can be suppressed.
[0025]
In addition, the code | symbol in the bracket | parenthesis of each said means is an example which shows a corresponding relationship with the specific means as described in embodiment mentioned later.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments shown in the drawings will be described below. 1A and 1B are diagrams illustrating an entire configuration of a semiconductor device S1 according to the present embodiment, where FIG. 1A is a schematic cross-sectional view, and FIG. 1B is a view as viewed from an arrow A in FIG. Stuff). The semiconductor device S1 is of a CSP (chip size package) type.
[0027]
The semiconductor device S1 is formed of a semiconductor chip 1 made of a semiconductor such as silicon and a circuit board 2 made of resin. The semiconductor chip 1 is formed by cutting a wafer 10 (see FIG. 2) described later, and a plurality of first electrodes (chip-side electrodes) 3 are formed on one surface 1a.
[0028]
Here, the chip-side electrode 3 is formed to be flat with respect to the one surface 1 a of the semiconductor chip 1. A plurality of second electrodes (circuit board side electrodes) 4 corresponding to the chip side electrodes 3 are formed on the surface 2a side of the circuit board 2 to which the chip 1 is bonded.
[0029]
Also, a flat outer electrode 5 is formed on the surface 2b of the circuit board 2 opposite to the chip bonding side. In the circuit board 2, the circuit board side electrode 4 and the outer electrode 5 are electrically connected. An internal wiring 6 for connection is formed. The outer electrode 5 is formed with bumps 7 made of solder or the like for connection to a printed circuit board (not shown) which is a mother board.
[0030]
The circuit board 2 is formed from, for example, a thermoplastic resin material, and in this example, is formed from a polyimide resin. The chip side electrode 3 is made of, for example, Al, and the circuit board side electrode 4 is made of, for example, a metal material such as Sn or Au.
[0031]
Here, on the surface of the chip-side electrode (first electrode) 3, a protruding electrode 8 that protrudes toward the circuit board 4 from the one surface 1 a of the semiconductor chip 1 is formed. The protruding electrode 8 can be made of, for example, a Ni—Au bump (Ni is a core material and the Ni surface is coated with Au) formed by electroless plating.
[0032]
The protruding electrode 8 and the circuit board side electrode 4 are in contact with, bonded to, or bonded to each other. In this example, Au constituting the surface of the protruding electrode 8 and Sn or Au constituting the circuit board side electrode 4 are connected by solid phase diffusion.
[0033]
Further, a portion where the chip-side electrode 3 is not formed on the one surface 1 a of the semiconductor chip 1 (hereinafter referred to as an electrode non-forming portion of the semiconductor chip 1) and the circuit board-side electrode 4 on the one surface 2 a of the circuit substrate 2 are not formed. A portion (hereinafter referred to as an electrode non-formation portion of the circuit board 2) is directly bonded, and the semiconductor chip 1 and the circuit board 2 are bonded.
[0034]
The electrode non-formation part of the semiconductor chip 1 is covered with a protective film such as an inorganic substance (nitride film or the like) or an organic substance (not shown). On the other hand, the electrode non-formation part of the circuit board 2 consists of resin materials, such as above-mentioned thermoplastic resin. The resin on the one surface 2a side of the circuit board 2 rises to the chip 1 side from the circuit board side electrode 4 and directly adheres to the electrode non-formation part of the chip 1 at the opposing part of both electrode non-formation parts. 3, 4, and 8 are sealed.
[0035]
Next, a method for manufacturing the semiconductor device S1 having the above configuration will be described with reference to FIG. FIG. 2 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device in the present embodiment. First, as shown in FIG. 2A, the wafer (semiconductor substrate in the present invention) 10 and the circuit board 2 are prepared.
[0036]
The wafer 10 is not cut into chips as the semiconductor chip 1, and a plurality of chip-side electrodes 3 are formed on one surface 11 (corresponding to one surface 1 a of the semiconductor chip 1). Further, the portion of the one surface 11 where the chip-side electrode 3 is not formed (the electrode non-forming portion of the wafer 10) is a portion corresponding to the electrode non-forming portion of the semiconductor chip 1, and the above-described protective film Is provided.
[0037]
In the wafer 10, a protruding electrode 8 protruding from one surface 11 of the wafer 10 is formed on the surface of the chip side electrode 3. On the other hand, a plurality of circuit board side electrodes 4 corresponding to the chip side electrodes 3 are formed on one surface 2 a of the circuit board 2.
[0038]
The wafer 10 can be manufactured through a normal semiconductor process, and the protruding electrodes 8 can be easily formed, for example, as the Ni—Au bumps by the plating process in the semiconductor process.
[0039]
Next, as shown in FIG. 2B, while aligning the positions of the chip side electrode 3 and the circuit board side electrode 4, the one surface 11 of the wafer 10 and the one surface 2a of the circuit board are opposed to each other, The circuit board side electrode 4 is brought into contact (projection electrode contact step).
[0040]
Next, as shown in FIG. 2C, the wafer 10 and the circuit board 2 are pressed so as to be sandwiched therebetween. At this time, since the outer electrode 5 of the circuit board 2 is formed flat as described above, it is easy to perform a pressing operation. And it heats in the state which applied the pressure to the wafer 10 and the circuit board 2 (pressurization and a heating process).
[0041]
By this pressurization and heating, the protruding electrode 8 formed on the chip side electrode 3 in the wafer 10 and the circuit board side electrode 4 formed on the circuit board 2 are pressure-bonded, and both the electrodes 4 and 8 are in contact and bonded. Alternatively, they are electrically connected in the form of bonding. Specifically, as in the present embodiment, if the protruding electrode 8 is a Ni—Au bump having a surface of Au and the circuit board side electrode 4 is a metal material such as Sn or Au, Au and Sn or between Au The connection between the electrodes is formed by solid phase diffusion bonding.
[0042]
Moreover, since the circuit board 2 is formed from a thermoplastic resin, it is softened by the heating. And by pressurization, the resin part of the electrode non-formation part of the circuit board 2 rises to the wafer 10 side, and is directly bonded to the electrode non-formation part of the wafer 10.
[0043]
Here, since the organic substance such as polyimide resin used as the circuit board 2 in this embodiment has a functional group, the functional group is a protective film on the chip surface (wafer surface) when the circuit board 2 is heated. It is thought that it becomes easy to obtain a chemical bond by making a bonded state by approaching this atom.
[0044]
In this way, bonding the circuit board 2 and the wafer 10 results in covering the surface of the chip 1 with resin, and simultaneously connecting the electrodes 4 and 8 and sealing the electrode connection portion with resin. Can be implemented.
[0045]
The heating temperature in the above pressurizing / heating step is 100 to 300 ° C., particularly preferably 150 to 250 ° C., the pressurizing time is 30 seconds to 30 minutes, and the applied pressure is about 500 kPa to 5000 kPa.
[0046]
Thereafter, as shown in FIG. 2D, if necessary for connection to a printed circuit board as a mother board, bumps 7 made of solder or the like are formed on the outer electrode 5 on the circuit board side to which the wafer 10 is not bonded. Form. The bumps 7 are formed using, for example, solder balls. A plurality of CSP type semiconductor devices S1 can be obtained by cutting the wafer 10 and the circuit board 2 in units of chips (broken lines in FIG. 2D).
[0047]
By the way, according to the above manufacturing method, after the protruding electrode 8 formed on the chip side electrode 3 and the circuit board side electrode 4 are brought into contact with each other, the wafer surface and the circuit are formed at the electrode 10 non-formation portion of the wafer 10 and the circuit board 2. Since the substrate surface is brought into contact, the softened resin on the circuit board surface can be prevented from entering between the protruding electrode 8 and the circuit board side electrode 4.
[0048]
In addition, after the step of contacting the protruding electrode 8 and the circuit board side electrode 4 (projecting electrode contact step), the step of bringing the surfaces of both the substrates 2 and 10 into contact with each other at the electrode non-forming portion of both the substrates 2 and 10 ( The pressurization / heating step) can be performed with almost no difference in time as compared with the case where both of these steps are performed simultaneously as in the above-mentioned Japanese Patent Application Laid-Open No. 2001-24086.
[0049]
Further, by bonding the chip surface on which the electrode is not formed and the resin part on the circuit board surface, it is possible to realize the resin sealing of the chip simultaneously with the electrode connection, so that a resin material for resin sealing is not necessary. . Therefore, according to the present embodiment, it is possible to provide a method of manufacturing the semiconductor device S1 that can reduce the manufacturing cost and realize highly reliable electrode connection.
[0050]
Here, in the above manufacturing method, the semiconductor substrate used may be the wafer 10 or the semiconductor chip 1 after cutting. In this embodiment, since the assembly is performed in units of wafers, the productivity in manufacturing the semiconductor device can be improved and the package cost can be reduced as compared with the case of assembling the circuit board 2 in units of chips cut from the wafer. it can.
[0051]
In the above manufacturing method, in the pressurizing / heating step, pressurization and heating may be performed simultaneously. Preferably, after the wafer 10 and the circuit board 2 are sandwiched and pressurized, this pressurized state is changed. It is desirable to heat the wafer 10 and the circuit board 2 while holding them.
[0052]
Even if the chip side electrode 3 on the wafer 10 and the circuit board side electrode 4 on the circuit board 2 can be aligned at room temperature, the linear expansion coefficient between the wafer 10 and the circuit board 2 after heating is increased. This is because the positional deviation between the chip side electrode 3 and the circuit board side electrode 4 occurs.
[0053]
In that respect, if the wafer 10 and the circuit board 2 are sandwiched and pressurized at room temperature and heated after being constrained to each other, there is no problem in misalignment due to the difference in displacement due to the heat of both the boards 2 and 10. Can be suppressed to level.
[0054]
Furthermore, the circuit board 2 is usually deformed due to warpage or the like, and the position of the circuit board side electrode 4 formed on the circuit board 2 may vary vertically. Also in this case, the wafer 10 and the circuit board 2 are sandwiched and pressurized, and then heated, so that the circuit board 2 can be softened and deformation such as warpage can be eliminated, and the protruding electrode 8 on the chip side electrode 3 can be removed. And a good connection between the circuit board side electrodes 4 can be obtained.
[0055]
Further, in the present embodiment, as shown in FIG. 1, the semiconductor chip 1 in which the first electrode 3 is formed on at least one surface 1a side and the second corresponding to the first electrode 3 on at least one surface 2a side. And a circuit board 2 made of resin on which the electrode 4 is formed. The first electrode 3 is provided with a protruding electrode 8 protruding from the one surface 1a of the chip 1 to the circuit board 2 side. The second electrode 4 is in contact with and electrically connected, and further, the electrode non-forming portion of the circuit board 2 is raised to the semiconductor chip 1 side with respect to the second electrode 4. A semiconductor device S1 is provided, which is bonded to an electrode non-forming portion.
[0056]
According to this semiconductor device S1, since the semiconductor chip 1 is provided with the protruding electrodes 8 protruding from the one surface 1a, as is apparent from the manufacturing method, the circuit board 2 made of resin, the semiconductor chip 1, In this bonding, after the protruding electrode 8 and the circuit board side electrode (second electrode) 4 are brought into contact with each other, the bonding in the electrode non-forming portion can be performed.
[0057]
Therefore, according to the present embodiment, it is possible to provide the semiconductor device S1 that can reduce the manufacturing cost and can realize highly reliable electrode connection.
[Brief description of the drawings]
1A and 1B are diagrams illustrating an entire configuration of a semiconductor device according to an embodiment, where FIG. 1A is a schematic cross-sectional view, and FIG. 1B is a view as viewed from an arrow A in FIG.
2 is a process diagram showing a manufacturing method of the semiconductor device shown in FIG. 1; FIG.
FIG. 3 is a cross-sectional view showing a configuration of a conventional semiconductor device.
FIG. 4 is a cross-sectional view showing a configuration of a conventional semiconductor device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Semiconductor chip, 1a ... One surface of a semiconductor chip, 2 ... Circuit board,
2a: one surface of the circuit board, 3 ... first electrode (chip side electrode),
4 ... 2nd electrode (circuit board side electrode), 8 ... Projection electrode, 10 ... Wafer,
11: One side of the wafer.

Claims (2)

一面（１１）に第１の電極（３）が形成され、前記第１の電極の表面に前記一面から突出する突起電極（８）が形成された半導体基板（１０）と、一面（２ａ）に前記第１の電極に対応する第２の電極（４）が形成された樹脂よりなる回路基板（２）とを用意する工程と、
前記半導体基板の前記一面と前記回路基板の前記一面とを対向させ、前記突起電極と前記第２の電極とを接触させる工程と、
この工程の後、前記半導体基板と前記回路基板とを加圧し、この後に、この加圧状態を保持しながら前記半導体基板と前記回路基板との加熱を行うことにより、前記突起電極と前記第２の電極とを圧着するとともに、前記回路基板を構成する前記樹脂を軟化させ、前記半導体基板の前記一面における前記第１の電極が形成されていない部分と前記回路基板の前記一面における前記第２の電極が形成されていない部分とを接着し、前記半導体基板と前記回路基板とを接着する工程と、を備えることを特徴とする半導体装置の製造方法。A semiconductor substrate (10) having a first electrode (3) formed on one surface (11) and a protruding electrode (8) projecting from the one surface on the surface of the first electrode; and a first surface (2a) Preparing a circuit board (2) made of a resin on which a second electrode (4) corresponding to the first electrode is formed;
The one surface of the semiconductor substrate and the one surface of the circuit substrate are opposed to each other, and the protruding electrode and the second electrode are brought into contact with each other;
After this step, the semiconductor substrate and the circuit substrate are pressurized, and then the semiconductor substrate and the circuit substrate are heated while maintaining the pressurized state, whereby the protruding electrode and the second substrate are heated. The resin constituting the circuit board is softened, and the second surface of the one side of the circuit board and the second part of the one side of the circuit board are softened. Adhering a portion where no electrode is formed, and adhering the semiconductor substrate and the circuit board. A method for manufacturing a semiconductor device, comprising: 前記突起電極は表面がＡｕにて被覆された金属材料で形成され、前記第２の電極はＳｎもしくはＡｕの金属材料で形成されており、前記半導体基板と前記回路基板とを接着する工程では、ＡｕとＳｎもしくはＡｕ同士の固相拡散接合により前記突起電極と前記第２の電極とを接続することを特徴とする請求項１に記載の半導体装置の製造方法。The protruding electrode is formed of a metal material whose surface is coated with Au, and the second electrode is formed of a metal material of Sn or Au. In the step of bonding the semiconductor substrate and the circuit substrate, 2. The method of manufacturing a semiconductor device according to claim 1, wherein the protruding electrode and the second electrode are connected by solid phase diffusion bonding of Au and Sn or Au.
JP2001176141A 2001-06-11 2001-06-11 Manufacturing method of semiconductor device Expired - Fee Related JP3705159B2 (en)

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US6962835B2 (en) * 2003-02-07 2005-11-08 Ziptronix, Inc. Method for room temperature metal direct bonding
US7485968B2 (en) 2005-08-11 2009-02-03 Ziptronix, Inc. 3D IC method and device
US9953941B2 (en) 2015-08-25 2018-04-24 Invensas Bonding Technologies, Inc. Conductive barrier direct hybrid bonding
US10840205B2 (en) 2017-09-24 2020-11-17 Invensas Bonding Technologies, Inc. Chemical mechanical polishing for hybrid bonding
US11056348B2 (en) 2018-04-05 2021-07-06 Invensas Bonding Technologies, Inc. Bonding surfaces for microelectronics
US11393779B2 (en) 2018-06-13 2022-07-19 Invensas Bonding Technologies, Inc. Large metal pads over TSV
EP3807927A4 (en) 2018-06-13 2022-02-23 Invensas Bonding Technologies, Inc. Tsv as pad
US11011494B2 (en) 2018-08-31 2021-05-18 Invensas Bonding Technologies, Inc. Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics
US11158573B2 (en) 2018-10-22 2021-10-26 Invensas Bonding Technologies, Inc. Interconnect structures
US11264357B1 (en) 2020-10-20 2022-03-01 Invensas Corporation Mixed exposure for large die

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