KR200179421Y1 - Stack semiconductor package - Google Patents
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- KR200179421Y1 KR200179421Y1 KR2019950034744U KR19950034744U KR200179421Y1 KR 200179421 Y1 KR200179421 Y1 KR 200179421Y1 KR 2019950034744 U KR2019950034744 U KR 2019950034744U KR 19950034744 U KR19950034744 U KR 19950034744U KR 200179421 Y1 KR200179421 Y1 KR 200179421Y1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49572—Lead-frames or other flat leads consisting of thin flexible metallic tape with or without a film carrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
본 고안은 하나의 패캐이지에 2개의 다이를 구성한 적층형 반도체 패캐이지에 관한 것으로, 다이 부착용 패드가 형성되지 않은 리드 프레임을 이용하고, 회로 패턴이 형성된 필름을 리드 프레임의 각 내측 리드 저면에 부착시키고 제1다이를 필름에 부착시켜 제1다이와 내측 리드를 전기적으로 연결시키며, 제2다이를 제1다이 상면에 부착시키고, 제2다이와 내측 리드간을 와이어로 연결하여 구성하므로써, 와이어 변형이 발생하지 않고 패캐이지를 보다 박형으로 구성할 수 있도록 한 적층형 반도체 패캐이지가 개시된다.The present invention relates to a stacked semiconductor package in which two dies are formed in one package, and uses a lead frame in which a die attach pad is not formed, and attaches a film having a circuit pattern to the bottom of each inner lead of the lead frame. By attaching the first die to the film to electrically connect the first die and the inner lead, attaching the second die to the top of the first die, and connecting the second die and the inner lead with wires, no wire deformation occurs. Disclosed is a stacked semiconductor package in which a package can be made thinner without using the same.
Description
제1도는 일반적인 적층형 반도체 패캐이지의 단면도.1 is a cross-sectional view of a general stacked semiconductor package.
제2도는 본 고안에 따른 적층형 반도체 패캐이지의 단면도.2 is a cross-sectional view of a stacked semiconductor package according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 제1다이 12 : 제2다이11: 1st die 12: 2nd die
13 : 내측 리드 14 : 필름13: inner lead 14: film
11A 및 13A : 범프 15 : 와이어11A and 13A: Bump 15: Wire
본 고안은 반도체 패캐이지에 관한 것으로, 특히 패드를 이용하지 않고 2개의 다이를 적층형태로 구성한 적층형 반도체 패캐이지에 관한 것이다.The present invention relates to a semiconductor package, and more particularly, to a stacked semiconductor package in which two dies are formed in a stacked form without using pads.
2개의 다이를 부착시켜 구성한 일반적인 적층형 반도체 패캐이지에서는 리드 프레임의 패드 상면 및 저면에 접착제를 이용하여 제1다이 및 제2다이를 부착시킨 후 제1다이와 내측리드, 제2다이와 내측리드간에 와이어 본딩을 실시하게 된다.In a general stacked semiconductor package formed by attaching two dies, the first die and the second die are attached to the top and bottom surfaces of the lead frame by using an adhesive, and then wire bonding between the first die and the inner lead and the second die and the inner lead. Will be performed.
제1도는 일반적인 적층형 반도체 패캐이지의 단면도로서, 상술한 바와 같은 적층형 패캐이지의 구성을 도시하고 있다.1 is a cross-sectional view of a general stacked semiconductor package, and shows the configuration of the stacked package as described above.
리드 프레임의 구성부분인 패드(2)의 상면 및 저면에 각각 접착제를 사용하여 제2다이(3A) 및 제2다이(3B)를 부착한다. 이후, 와이어 본딩공정에서 제1다이(3A)와 내측 리드(1) 간을 와이어(5)로 연결한 후 제2다이(3B)와 내측 리드(1) 간을 와이(4)로 연결한다.(이러한 와이어 본딩공정 후 몰딩 컴파운드를 이용한 성형(moding) 공정을 실시하므로써 제1도에 도시된 패캐이지의 구성이 이루어진다.)The second die 3A and the second die 3B are attached to the top and bottom surfaces of the pad 2, which are components of the lead frame, respectively using an adhesive. Thereafter, in the wire bonding process, the first die 3A and the inner lead 1 are connected with the wire 5, and then the second die 3B and the inner lead 1 are connected with the wire 4. (The configuration of the package shown in FIG. 1 is achieved by performing a molding process using a molding compound after such a wire bonding process.)
그러나, 상술한 적층형 패캐이지는 패드(2)의 상면 및 저면에 각각 제1 및 제2다이(3A, 3B)를 부착하므로써 다음과 같은 문제점이 발생하게 된다.However, the above-described laminated package attaches the first and second dies 3A and 3B to the top and bottom surfaces of the pad 2, respectively, resulting in the following problems.
(가) 패드(2)의 상면 및 저면에 제1 및 제2다이(3A, 3B)를 부착시킨 상태에서 와이어(4, 5)를 이용하여 제1다이(3A)와 내측 리드(1), 제2다이(3B)와 내측 리드(1)를 순차적으로 연결하므로써, 본딩된 와이어(4, 5)의 상태에 변형이 일어날 우려가 있다. 즉, 제1다이(3A)와 내측 리드(1) 간에 와이어 본딩을 실시한 후 본딩장치 상에서 제2다이(3B)와 내측 리드(1)간에 와이어 본딩을 실시하게 되므로 본딩장치 표면에 이미 본딩된 제1다이(3A)와 내측 리드(1) 간의 와이어(5)가 접촉되므로서 와이어(4, 5)의 변형이 이루어지게 되며, 심한 경우 와이어의 본딩상태가 해제되는 경우도 발생하게 된다.(A) The first die 3A and the inner lead 1 using the wires 4 and 5 in the state where the first and second dies 3A and 3B are attached to the upper and lower surfaces of the pad 2. By connecting the second die 3B and the inner lead 1 sequentially, there is a fear that deformation occurs in the state of the bonded wires 4 and 5. That is, since wire bonding is performed between the first die 3A and the inner lead 1 and then wire bonding is performed between the second die 3B and the inner lead 1 on the bonding apparatus, the first bonding agent is already bonded to the surface of the bonding apparatus. Deformation of the wires 4 and 5 occurs by contacting the wire 5 between the die 1A and the inner lead 1, and in some cases, the bonding state of the wire is released.
(나) 리드 프레임 패드(2) 상면 및 저면에 제1다이(3A) 및 제2다이(3B)를 부착하므로서, 패드(2)로 인하여 패캐이지의 구성 두께가 비교적 두꺼워지며, 이는 패캐이지의 소형화 추세에 바람직하지 않다.(B) By attaching the first die 3A and the second die 3B to the top and bottom surfaces of the lead frame pad 2, the pad 2 makes the package thickness relatively thick, Not desirable for the miniaturization trend.
(다) 다이를 리드 프레임에 부착하기 위해서는 리드 프레임에 패드를 구성하여야 하나, 패드는 몰딩 공정 후 경화된 몰딩 컴파운드에 손상을 발생시키는 원인이 된다. 즉, 패드의 모서리 부분에는 응력이 집중적으로 발생되기 때문에 이와 대응하는 경화된 몰딩 컴파운드에는 크랙(crack)이 발생되어 제품의 신뢰성에 영향을 미치게 된다. 또한, 칩과 패드는 그 열팽창 계수가 서로 다르며, 따라서 몰딩 공정시 고온의 몰딩 컴파운드와 접촉할 때 각 다이와 패드는 그 이완 정도가 서로 달라지는 문제점도 예상할 수 있다.(C) In order to attach the die to the lead frame, a pad must be formed in the lead frame, but the pad may cause damage to the hardened molding compound after the molding process. That is, since stress is concentrated at the edges of the pad, cracks are generated in the corresponding hardened molding compound, which affects the reliability of the product. In addition, chips and pads have different coefficients of thermal expansion, and thus, each die and pad may have a different degree of relaxation when contacted with a high temperature molding compound during a molding process.
따라서, 본 고안은 다이 부착용 패드를 형성하지 않은 리드 프레임을 이용하고, 제1다이와 내측 리드는 회로패턴이 형성된 필름을 이용하여 연결하고, 제2다이와 내측 리드는 와이어를 통하여 연결하므로써 상술한 문제점들을 해결할 수 있는 적층형 반도체 패캐이지를 제공하는데 그 목적이 있다.Accordingly, the present invention uses a lead frame that does not form a die attach pad, connects the first die and the inner lead by using a film having a circuit pattern, and connects the second die and the inner lead through a wire to solve the above-mentioned problems. The purpose is to provide a stacked semiconductor package that can be solved.
상술한 목적을 실현하기 위한 본 고안은 2개의 다이를 부착시켜 구성하는 적층형 반도체 패캐이지에 있어서, 회로 패턴이 형성된 필름을 리드 프레임의 각 내측 리드 저면에 부착시키고, 제1다이를 상기 회로패턴이 형성된 필름에 부착시켜 상기 제1다이와 상기 내측 리드를 전기적으로 연결시키며, 상기 제1다이 상부면에 제2다이를 부착시키고, 상기 제2다이와 내측 리드간을 와이어로 연결하여 구성한 것을 특징으로 한다.The present invention for realizing the above object is a laminated semiconductor package formed by attaching two dies, wherein a film having a circuit pattern is attached to the bottom surface of each inner lead of the lead frame, and the first die is attached to the circuit pattern. Attaching to the formed film to electrically connect the first die and the inner lead, attaching a second die to the upper surface of the first die, and connecting the second die and the inner lead with wires.
이하, 본 고안을 첨부한 도면을 참고하여 상세히 설명한다.Hereinafter, with reference to the accompanying drawings of the present invention will be described in detail.
제2도는 본 고안에 따른 적층형 반도체 패캐이지의 단면도로서, 본 고안에 따른 적층형 반도체 패캐이지의 가장 큰 특징은 다이 부착용 패드가 형성되어 있지 않은 리드 프레임에 회로 패턴이 형성된 필름(14)을 이용하여 제1다이(11)를 부착시키고 와이어를 이용하여 제2다이(12)를 부착시킨다는 점이다. 상세히 설명하면 다음과 같다.2 is a cross-sectional view of the stacked semiconductor package according to the present invention. The biggest feature of the stacked semiconductor package according to the present invention is that the circuit pattern is formed on the lead frame in which the pad for attaching the die is not formed. The first die 11 is attached and the second die 12 is attached using a wire. It will be described in detail as follows.
회로 패턴이 형성된 필름(14)을 리드 프레임의 하부에 위치시킨 뒤 각 내측 리드(13)의 저면이 필름(14)의 회로 패턴과 접촉되도록 부착시킨다. 즉, 제1다이(11) 저면에 형성된 각 본딩 패드와 필름(14)의 회로 패턴을 대응시킨 상태에서 제1다이(11)를 필름(14)에 부착시키는 것이다. 여기에서, 제1다이(11)의 각 본딩 패드에는 백금(Au) 등의 도전성이 우수한 재질을 이용하여 범프(11A;bump)가 형성되어 있는데, 이 각 범프(11A)를 필름(14)의 회로 패턴에 부착시키므로써 제1다이(11)의 부착공정이 완료된다. 한편, 내측 리드(13)의 저면에도 도전성 재질의 범프(13A)를 형성하여 필름(14)의 회로 패턴에 부착시키므로써 제1다이(11)와 내측 리드는 전기적으로 연결된다.The film 14 on which the circuit pattern is formed is positioned below the lead frame, and then the bottom surface of each inner lead 13 is attached to contact the circuit pattern of the film 14. That is, the first die 11 is attached to the film 14 in a state where the bonding pads formed on the bottom surface of the first die 11 and the circuit pattern of the film 14 correspond to each other. Here, bumps 11A (bump) are formed on each bonding pad of the first die 11 by using a material having excellent conductivity such as platinum (Au), and each of the bumps 11A is formed of the film 14. By attaching to the circuit pattern, the attaching process of the first die 11 is completed. Meanwhile, the first die 11 and the inner lead are electrically connected to each other by forming a bump 13A of a conductive material on the bottom surface of the inner lead 13 and attaching the bump 13A to the circuit pattern of the film 14.
상술한 바와 같이 회로 패턴이 형성된 필름(14)을 이용하여 제1다이(11)와 내측 리드(13)간을 연결시킨 후 제2다이(22)를 에폭시 수지 등의 접착제(16)를 이용하여 제1다이(11) 상부면에 부착시킨다. 이후, 제2다이(12) 표면에 형성된 본딩 패드와 내측 리드(13) 간을 와이어(15)로 연결하므로써, 각 다이(11 및 12)와 내측 리드(13) 간의 접속공정은 종료된다. (이때, 제1다이(11)와 이미 연결된 내측 리드(13)에는 제2다이(12)가 와이어(15)로 연결될 수 없음은 물론이다.)As described above, the first die 11 and the inner lead 13 are connected to each other using the film 14 having the circuit pattern formed thereon, and the second die 22 is then bonded using an adhesive 16 such as an epoxy resin. It is attached to the upper surface of the first die (11). Thereafter, by connecting the bonding pad formed on the surface of the second die 12 and the inner lead 13 with the wire 15, the connection process between the dies 11 and 12 and the inner lead 13 is completed. (At this time, it is a matter of course that the second die 12 cannot be connected to the inner lead 13 already connected to the first die 11 by the wire 15.)
이상과 같은 본 고안의 사용상 효과는 다음과 같다.Effects of the present invention as described above are as follows.
(가) 회로 패턴이 형성된 필름을 이용하여 제1다이를 리드 프레임의 내측 리드에 고정시킨 후 제2다이를 제1다이에 부착시켜 제2다이와 내측 리드를 와이어로 본딩, 접속하므로써 제1다이에 대한 와이어 본딩 공정이 필요없게 되어, 본딩 다이에 와이어가 접촉되므로 인하여 발생되는 와이어의 변형이 발생하지 않게 된다.(A) After fixing the first die to the inner lead of the lead frame using the film on which the circuit pattern is formed, attaching the second die to the first die and bonding and connecting the second die and the inner lead with wires to the first die. There is no need for a wire bonding process, so that deformation of the wire caused by contacting the wire to the bonding die does not occur.
(나) 다이 부착용 패드가 형성되지 않은 리드 프레임을 이용하므로써, 패드만큼의 두께가 감소되어 보다 박형의 패캐이지 형성이 가능하다.(B) By using a lead frame in which no die attach pad is formed, the thickness of the pad can be reduced to form a thinner package.
(다) 다이 부착용 패드가 형성되지 않은 리드 프레임을 이용하기 때문에, 패드 모서리 부분에 응력이 집중되는 것을 사전에 예방할 수 있어 몰딩 컴파운드의 손상을 방지할 수 있다.(C) Since a lead frame without a die attach pad is used, stress concentration at the edge of the pad can be prevented in advance, and damage to the molding compound can be prevented.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019950034744U KR200179421Y1 (en) | 1995-11-22 | 1995-11-22 | Stack semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019950034744U KR200179421Y1 (en) | 1995-11-22 | 1995-11-22 | Stack semiconductor package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970025857U KR970025857U (en) | 1997-06-20 |
| KR200179421Y1 true KR200179421Y1 (en) | 2000-05-01 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019950034744U KR200179421Y1 (en) | 1995-11-22 | 1995-11-22 | Stack semiconductor package |
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| Country | Link |
|---|---|
| KR (1) | KR200179421Y1 (en) |
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1995
- 1995-11-22 KR KR2019950034744U patent/KR200179421Y1/en not_active IP Right Cessation
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| Publication number | Publication date |
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| KR970025857U (en) | 1997-06-20 |
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