JP2007042827A - Power semiconductor device - Google Patents

Power semiconductor device Download PDF

Info

Publication number
JP2007042827A
JP2007042827A JP2005224828A JP2005224828A JP2007042827A JP 2007042827 A JP2007042827 A JP 2007042827A JP 2005224828 A JP2005224828 A JP 2005224828A JP 2005224828 A JP2005224828 A JP 2005224828A JP 2007042827 A JP2007042827 A JP 2007042827A
Authority
JP
Japan
Prior art keywords
semiconductor device
power semiconductor
metal
cooling plate
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2005224828A
Other languages
Japanese (ja)
Other versions
JP4375299B2 (en
Inventor
Yukio Kamida
行雄 紙田
Seiichi Hayakawa
誠一 早川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2005224828A priority Critical patent/JP4375299B2/en
Publication of JP2007042827A publication Critical patent/JP2007042827A/en
Application granted granted Critical
Publication of JP4375299B2 publication Critical patent/JP4375299B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power semiconductor device which reduces heat resistance and is excellent in heat dissipation characteristics. <P>SOLUTION: The device is an internally insulated semiconductor device includes: a metal support substrate at the bottom; an insulating substrate mounted through brazing filler metal on the metal support substrate; a power semiconductor device mounted in the insulating substrate through another brazing filler metal and an another metal layer; and a cooling metal plate arranged through insulating resin on the power semiconductor device. Both sides of the upper surface and the under surface are equipped with heat dissipation surfaces, the thermal conductivity of the insulating resin is 5 W/mK or more, and the thickness is 0.2 mm to 2 mm. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は内部絶縁型のパワー半導体装置に係り、特に大電流容量のパッケージ型パワー半導体モジュールに好適なパワー半導体装置に関する。   The present invention relates to an internal insulation type power semiconductor device, and more particularly to a power semiconductor device suitable for a package type power semiconductor module having a large current capacity.

従来技術のパワー半導体モジュールの断面構造を図２に示す。図２において、符号１は半導体素子、２ａ、２ｂ、２ｃはソルダー、３は絶縁基板、４ａ、４ｂは金属層、５ａ、５ｂはろう材、６は支持基板、７はゲル、８は金属ワイヤ、９ａ、９ｂ、９ｃは配線端子、１０は樹脂体、１１は空隙部、１２は接着剤である。   A cross-sectional structure of a power semiconductor module of the prior art is shown in FIG. In FIG. 2, reference numeral 1 is a semiconductor element, 2a, 2b and 2c are solders, 3 is an insulating substrate, 4a and 4b are metal layers, 5a and 5b are brazing materials, 6 is a support substrate, 7 is a gel, and 8 is a metal wire. , 9a, 9b, 9c are wiring terminals, 10 is a resin body, 11 is a gap, and 12 is an adhesive.

図２の絶縁基板３は、アルミナ、窒化珪素などの電気絶縁材で作られ、その一方の面には、配線パターンが形成された金属層４ａがろう材５ａにより接合され、他方の面には、半田などによる接合を可能とするための金属層４ｂが、ろう材５ｂにより接合されている。半導体素子１は、絶縁基板３の一方の面に形成されている金属層４ａの所定の部分にソルダー２ａにより接合され、絶縁基板３のもう一方の面に形成されている金属層４ｂが支持基板６にソルダー２ｂにより積層される。そして、これらの半導体素子１は、金属ワイヤ８により、金属層４ａの所定の部分に対して配線が施されている。   The insulating substrate 3 in FIG. 2 is made of an electrical insulating material such as alumina or silicon nitride. A metal layer 4a on which a wiring pattern is formed is bonded to one surface by a brazing material 5a, and the other surface is connected to the other surface. A metal layer 4b for enabling bonding by solder or the like is bonded by a brazing material 5b. The semiconductor element 1 is joined to a predetermined portion of the metal layer 4a formed on one surface of the insulating substrate 3 by a solder 2a, and the metal layer 4b formed on the other surface of the insulating substrate 3 is supported on the support substrate. 6 is laminated by the solder 2b. These semiconductor elements 1 are wired with a metal wire 8 to a predetermined portion of the metal layer 4a.

支持基板６は、半導体素子１で発生した熱を拡散させるヒートシンクを兼ねており銅などの熱伝導率の高い物質で作られる。ゲル７は半導体素子１を外部雰囲気から遮断するとともに、電位の異なる配線端子９ａと配線端子９ｂとの絶縁を保つ役目もする。   The support substrate 6 also serves as a heat sink for diffusing heat generated in the semiconductor element 1 and is made of a material having high thermal conductivity such as copper. The gel 7 blocks the semiconductor element 1 from the external atmosphere and also serves to maintain insulation between the wiring terminals 9a and 9b having different potentials.

電流入出力用の電位の異なる配線端子９ａおよび配線端子９ｂと電流制御用の信号入力用の配線端子９ｃは、支持基板６と接着剤１２により固着されている樹脂体１０内部に埋め込まれており、金属層４ａに形成されている配線パターンの所定の部分とソルダー２ｃにより接続され、外部装置との電流、電圧の入出力を行う。空隙部１１は半導体素子１の通電時の発熱によるゲル７の膨張による応力を緩和するものである。このような従来技術のパワー半導体モジュールの例が特許文献１に開示されている。   The wiring terminals 9a and 9b having different potentials for current input / output and the wiring terminals 9c for signal input for current control are embedded in the resin body 10 fixed by the support substrate 6 and the adhesive 12. A predetermined portion of the wiring pattern formed on the metal layer 4a is connected to the solder 2c to input / output current and voltage to / from an external device. The gap 11 relieves stress due to expansion of the gel 7 due to heat generated when the semiconductor element 1 is energized. An example of such a conventional power semiconductor module is disclosed in Patent Document 1.

特開２００３−６８９７９号公報（図１、（００１３）段落から（００１５）段落の記載。）Japanese Patent Laid-Open No. 2003-68979 (Description of paragraphs (0013) to (0015) in FIG. 1)

従来技術の半導体装置では、半導体素子に流れる電流は、ＯＮ／ＯＦＦ制御され、ＯＮ時には温度上昇、ＯＦＦ時には温度低下を繰り返すが、この温度サイクルにより、半導体モジュールに内蔵したソルダーや金属ワイヤが疲労し、最終的には、断線などが生じるといった問題がある。   In the semiconductor device of the prior art, the current flowing through the semiconductor element is ON / OFF controlled, and the temperature rises at the time of ON and the temperature decreases at the time of OFF. This temperature cycle causes the solder and metal wires built in the semiconductor module to be fatigued. Finally, there is a problem that disconnection or the like occurs.

このため、この種の半導体装置では、温度上昇を低く抑えて長寿命化を図ることが重要な課題である。半導体素子のサイズを大きくすることにより、熱抵抗を低くし、温度上昇を低く抑えることが考えられるが、半導体モジュールの形状が大きくなり実用的ではない。   For this reason, in this type of semiconductor device, it is an important issue to keep the temperature rise low and to extend the life. Although it is conceivable to increase the size of the semiconductor element to reduce the thermal resistance and to suppress the temperature rise, the shape of the semiconductor module increases and is not practical.

また、前記の従来技術の半導体装置では、半導体素子から発生される熱は半導体素子を接着しているソルダー、絶縁基板、支持基板を介し、下方向に放熱されるが、半導体素子上部からの放熱は、半導体素子を覆っているゲル（樹脂）の熱伝導率が低いために期待ができない問題もある。   In the semiconductor device of the above prior art, the heat generated from the semiconductor element is radiated downward through the solder, the insulating substrate, and the support substrate to which the semiconductor element is bonded. Has a problem that cannot be expected because the thermal conductivity of the gel (resin) covering the semiconductor element is low.

本発明の目的は、放熱性に優れたパワー半導体装置を提供することである。   An object of the present invention is to provide a power semiconductor device excellent in heat dissipation.

本発明のパワー半導体装置は、半導体素子上部に電極配線を配置し、高放熱樹脂を介してその上部に金属製冷却板を配置し、パワー半導体装置の上面と下面の両面に放熱面を備えている。   The power semiconductor device of the present invention has an electrode wiring arranged on the upper part of the semiconductor element, a metal cooling plate is arranged on the upper part via a high heat radiating resin, and a heat radiating surface is provided on both the upper and lower surfaces of the power semiconductor device. Yes.

本発明のパワー半導体装置は、半導体素子上部に電極配線を配置し、高放熱樹脂を介してその上部に金属製冷却板を配置し、この金属製冷却板がモジュール上面から半導体素子部に向けて突き出るようにその板厚が厚くなっている。   In the power semiconductor device of the present invention, the electrode wiring is arranged on the upper part of the semiconductor element, and the metal cooling plate is arranged on the upper part through the high heat radiation resin, and the metal cooling plate is directed from the upper surface of the module toward the semiconductor element part. The plate is thick so that it sticks out.

本発明のパワー半導体装置によれば、パワー半導体装置の上面と下面の両面から内部の半導体素子の発熱を放熱できる。   According to the power semiconductor device of the present invention, the heat generated by the internal semiconductor elements can be radiated from both the upper and lower surfaces of the power semiconductor device.

本発明のパワー半導体モジュールの詳細を図面を用いながら説明する。   Details of the power semiconductor module of the present invention will be described with reference to the drawings.

本実施例のパワー半導体モジュールを図１を用いて説明する。図１は本発明のパワー半導体モジュールの断面模式図である。この図１において、符号１はシリコン半導体基板に形成したＩＧＢＴやパワーＭＯＳＦＥＴ、電力用ダイオードや還流用ダイオードなどの半導体素子、２ａ、２ｂ、２ｃ、２ｄはソルダー、３は絶縁基板、４ａ、４ｂは金属層、５ａ、５ｂはろう材、６は支持基板、７ａは高放熱樹脂、８は金属ワイヤ、８ａは電極配線、９ａ、９ｂ、９ｃは配線端子、１０は樹脂体、１２は接着剤、１３は金属製冷却板である。   The power semiconductor module of the present embodiment will be described with reference to FIG. FIG. 1 is a schematic cross-sectional view of a power semiconductor module of the present invention. In FIG. 1, reference numeral 1 denotes an IGBT or power MOSFET formed on a silicon semiconductor substrate, a semiconductor element such as a power diode or a reflux diode, 2a, 2b, 2c, 2d is a solder, 3 is an insulating substrate, 4a, 4b are Metal layers, 5a and 5b are brazing materials, 6 is a support substrate, 7a is a high heat dissipation resin, 8 is a metal wire, 8a is an electrode wiring, 9a, 9b and 9c are wiring terminals, 10 is a resin body, 12 is an adhesive, Reference numeral 13 denotes a metal cooling plate.

絶縁基板３は、窒化珪素、アルミナなどの電気絶縁材で作られ、その一方の面には、配線パターンが形成された金属層４ａがろう材５ａにより接合され、他方の面には、半田などによる接合を可能とするための金属層４ｂがろう材５ｂにより接合されている。   The insulating substrate 3 is made of an electrical insulating material such as silicon nitride or alumina, and a metal layer 4a on which a wiring pattern is formed is bonded to one surface by a brazing material 5a, and solder or the like is connected to the other surface. The metal layer 4b for enabling the joining by the brazing material 5b is joined.

そして、複数個の半導体素子１は、絶縁基板３の一方の面に形成されている金属層４ａの所定の部分にソルダー２ａにより接合され、絶縁基板３のもう一方の面に形成されている金属層４ｂが支持基板６にソルダー２ｂにより積層される。そして、これらの半導体素子１の制御信号用配線は、金、アルミニウム、アルミ合金などの材質の金属ワイヤ８により、金属層４ａの所定の部分に対して配線が施されている。また、半導体素子１の主電流用配線はソルダー２ｄにより接着された電極配線８ａ（図１ではリードフレーム。）を介し、金属層４ａの所定の部分に対して配線が施されている。本実施例でこのようにリードフレームを介して配線してあるのは、金属ワイヤで配線する場合よりも、パワー半導体モジュールの高さを低く抑えることができるためである。支持基板６は、銅や銅合金などの金属で作られ、半導体素子１で発生した熱を拡散させるヒートシンクを兼ねている。   The plurality of semiconductor elements 1 are bonded to a predetermined portion of the metal layer 4a formed on one surface of the insulating substrate 3 by a solder 2a, and the metal formed on the other surface of the insulating substrate 3 The layer 4b is laminated on the support substrate 6 by the solder 2b. The control signal wirings of these semiconductor elements 1 are wired to predetermined portions of the metal layer 4a by metal wires 8 made of gold, aluminum, aluminum alloy or the like. The main current wiring of the semiconductor element 1 is wired to a predetermined portion of the metal layer 4a through an electrode wiring 8a (a lead frame in FIG. 1) bonded by a solder 2d. The reason why the wiring is provided through the lead frame in this embodiment is that the height of the power semiconductor module can be suppressed to be lower than that in the case of wiring with a metal wire. The support substrate 6 is made of a metal such as copper or a copper alloy, and also serves as a heat sink that diffuses the heat generated in the semiconductor element 1.

本実施例の半導体モジュールの特徴である高放熱樹脂７ａは、半導体素子１で発生した熱を拡散させるとともに、電位の異なる配線端子９ａと配線端子９ｂとの絶縁を保つ役目もする。   The high heat dissipation resin 7a, which is a feature of the semiconductor module of this embodiment, diffuses the heat generated in the semiconductor element 1 and also serves to maintain insulation between the wiring terminals 9a and 9b having different potentials.

電流入出力用の電位の異なる配線端子９ａおよび配線端子９ｂと電流制御用の信号を入力する配線端子９ｃは、支持基板６と接着剤１２により固着されている樹脂体１０内部に埋め込まれており、その一端を金属層４ａに形成されている配線パターンの所定の部分とソルダー２ｃにより接続され、他端を図１に示すように、樹脂体１０の側面から突き出している。   The wiring terminals 9a and 9b having different potentials for current input / output and the wiring terminal 9c for inputting a current control signal are embedded in the resin body 10 fixed by the support substrate 6 and the adhesive 12. One end thereof is connected to a predetermined portion of the wiring pattern formed on the metal layer 4a by the solder 2c, and the other end protrudes from the side surface of the resin body 10 as shown in FIG.

金属製冷却板１３は樹脂体１０で囲んだ半導体モジュールの上面に配置し、樹脂体１０の内側に、図１に示すよう設けた段差部に設置することにより、その高さを制御することができる。また、金属製冷却板１３には１つ或いは複数の貫通穴を設けてあり、貫通穴から高放熱樹脂７ａの充填を可能とする。   The metal cooling plate 13 is disposed on the upper surface of the semiconductor module surrounded by the resin body 10, and the height of the metal cooling plate 13 can be controlled by installing it on the step portion provided as shown in FIG. it can. Further, the metal cooling plate 13 is provided with one or a plurality of through holes, and the high heat radiation resin 7a can be filled from the through holes.

また、本実施例の半導体モジュールでは、図１に示すように半導体モジュール上面に露出した金属製冷却板１３の面積が絶縁基板３の面積より広く、支持基板６の面積より狭くして放熱を促進しているが、金属製冷却板１３の面積を支持基板６の面積と同じかそれより広くしてさらに放熱を促進してもよい。   Further, in the semiconductor module of this embodiment, as shown in FIG. 1, the area of the metal cooling plate 13 exposed on the upper surface of the semiconductor module is larger than the area of the insulating substrate 3 and smaller than the area of the support substrate 6 to promote heat dissipation. However, the area of the metal cooling plate 13 may be the same as or larger than the area of the support substrate 6 to further promote heat dissipation.

本実施例の半導体モジュールに充填する高放熱樹脂７ａは、熱伝導率１０Ｗ／ｍＫの樹脂である。本実施例の半導体モジュールでは、半導体素子１上部の電極配線８ａ（リードフレーム）と上部の金属製冷却板１３とに挟まれた高放熱樹脂７ａの厚みを０.４mm とすることにより、全体の発熱量の３０％程度を上部の金属製冷却板１３から放熱することが可能となる。高放熱樹脂７ａの厚さは薄い程熱抵抗が小さくなって、上部の金属製冷却板１３からの放熱効果は高いが、０.２mm 〜２mmが好ましい。すなわち、電極配線８ａと上部の金属冷却板１３の絶縁のため少なくとも０.２mm 以上は必要であり、また、高放熱樹脂７ａの厚みを２mm以上とすると熱抵抗が大きくなって、上部の金属製冷却板１３から放熱することが可能な熱が全体の発熱量の１０％以下となる。   The high heat radiation resin 7a filled in the semiconductor module of this embodiment is a resin having a thermal conductivity of 10 W / mK. In the semiconductor module of this embodiment, the thickness of the high heat radiation resin 7a sandwiched between the electrode wiring 8a (lead frame) on the semiconductor element 1 and the metal cooling plate 13 on the upper side is set to 0.4 mm. About 30% of the heat generation amount can be radiated from the upper metal cooling plate 13. The thinner the high heat radiation resin 7a, the smaller the thermal resistance, and the higher the heat radiation effect from the upper metal cooling plate 13, but 0.2 mm to 2 mm is preferable. That is, at least 0.2 mm or more is necessary for insulation between the electrode wiring 8a and the upper metal cooling plate 13, and if the thickness of the high heat dissipation resin 7a is 2 mm or more, the thermal resistance increases, and the upper metal plate is made of metal. The heat that can be dissipated from the cooling plate 13 is 10% or less of the total calorific value.

本実施例での半導体モジュールに適用できる高放熱樹脂７ａは、熱伝導率が５Ｗ／ｍＫ以上であればよく、好ましくは１０Ｗ／ｍＫ以上であればよい。高放熱樹脂７ａは、樹脂単体であっても良いし、例えば、樹脂に電気絶縁性のフィラを配合した樹脂組成物であっても良い。また、高放熱樹脂７ａがトランスファ成型できる材質であれば、図１の樹脂体１０を省いた一体成型した半導体モジュールとしても良い。   The high heat dissipation resin 7a applicable to the semiconductor module in the present embodiment may have a thermal conductivity of 5 W / mK or more, preferably 10 W / mK or more. The high heat dissipation resin 7a may be a single resin or may be a resin composition in which an electrically insulating filler is blended with a resin, for example. Further, as long as the high heat dissipation resin 7a is a material that can be transfer molded, an integrally molded semiconductor module that omits the resin body 10 of FIG. 1 may be used.

なお、本実施例の半導体モジュールは内部で半導体素子１や電極配線８ａと支持基板６や金属製冷却板１３とが絶縁されているので、半導体モジュールの上面や下面に金属製の冷却フィンなどを絶縁材を介さずにそのまま設置できる。   In the semiconductor module of the present embodiment, the semiconductor element 1 and the electrode wiring 8a are insulated from the support substrate 6 and the metal cooling plate 13 inside, so that a metal cooling fin or the like is provided on the upper or lower surface of the semiconductor module. It can be installed as it is without any insulating material.

本実施例を図３を用いて説明する。本実施例の半導体モジュールでは、実施例１の半導体モジュールの上部に配置した金属製冷却板１３を、半導体モジュール上面全体を覆うように配置するのではなく、発熱量が大きな半導体素子１の上面を含む一部分に配置し、この金属製冷却板１３の断面形状を板厚が異なるニ段以上の段差がある図３に示すような凸形状にした。金属製冷却板１３は上部蓋１４の穴部に埋め込まれる構成となる。この部分以外は実施例１と同じ構成である。   This embodiment will be described with reference to FIG. In the semiconductor module of the present embodiment, the metal cooling plate 13 disposed on the upper portion of the semiconductor module of the first embodiment is not disposed so as to cover the entire upper surface of the semiconductor module, but the upper surface of the semiconductor element 1 that generates a large amount of heat. The metal cooling plate 13 was arranged in a part including the convex shape as shown in FIG. 3 with a step difference of two or more steps having different plate thicknesses. The metal cooling plate 13 is embedded in the hole of the upper lid 14. Except this part, the configuration is the same as that of the first embodiment.

本実施例の半導体モジュール内では、金属ワイヤ８及び電極配線８ａはその接合部の温度変化により発生する応力を緩和するために、半導体モジュールの高さ方向にループを形成してある。そのためにこのループ部分の絶縁を確保するために、このループ部分では高放熱樹脂７ａを厚くし、金属製冷却板１３を離して配置しなければならない。   In the semiconductor module of the present embodiment, the metal wire 8 and the electrode wiring 8a are formed with a loop in the height direction of the semiconductor module in order to relieve the stress generated by the temperature change at the junction. Therefore, in order to ensure the insulation of the loop portion, it is necessary to increase the thickness of the high heat-dissipating resin 7a and dispose the metal cooling plate 13 apart from the loop portion.

金属製冷却板１３を、図３に示すような発熱源の半導体素子１側に向けて凸の形状で、モジュール上面側に露出した面が平坦な形状とすることにより、金属ワイヤ８及び電極配線８ａの半導体モジュール内の配置に伴う高さ方向の制限を受けずに半導体素子１上部の電極配線８ａと金属製冷却板１３に挟まれる高放熱樹脂７ａの厚さを最小に抑えることができ、かつ放熱効果を高めることが可能となる。   The metal cooling plate 13 is formed in a convex shape toward the semiconductor element 1 side of the heat source as shown in FIG. 3, and the surface exposed on the module upper surface side is flat so that the metal wire 8 and the electrode wiring are formed. The thickness of the high heat radiation resin 7a sandwiched between the electrode wiring 8a on the semiconductor element 1 and the metal cooling plate 13 without being restricted in the height direction due to the arrangement in the semiconductor module 8a can be minimized. And it becomes possible to raise the heat dissipation effect.

本実施例の半導体モジュールに適用できる高放熱樹脂７ａは、実施例１と同様に熱伝導率が５Ｗ／ｍＫ以上であればよく、好ましくは１０Ｗ／ｍＫ以上であればよい。高放熱樹脂７ａは、樹脂単体であっても良いし、例えば、樹脂に電気絶縁性のフィラを配合した樹脂組成物であっても良い。また、高放熱樹脂７ａがトランスファ成型できる材質であれば、図３の樹脂体１０を省いた一体成型した半導体モジュールとしても良い。   The high heat dissipation resin 7a applicable to the semiconductor module of the present embodiment may have a thermal conductivity of 5 W / mK or more, preferably 10 W / mK or more, as in the first embodiment. The high heat dissipation resin 7a may be a single resin or may be a resin composition in which an electrically insulating filler is blended with a resin, for example. Further, as long as the high heat dissipation resin 7a is a material that can be transfer-molded, an integrally molded semiconductor module that omits the resin body 10 of FIG. 3 may be used.

図３では、半導体素子１と金属製冷却板１３とがそれぞれ１つの場合を示しているが、半導体素子１が複数個モジュールに搭載されている場合には、各半導体素子１に対応した位置に金属製冷却板１３を配置するとよい。また、例えば複数のＩＧＢＴ半導体チップと、複数の還流ダイオードチップとが搭載されて半導体モジュールの場合に発熱量の大きな半導体素子１、すなわち複数のＩＧＢＴ半導体チップに対応した位置にだけ金属製冷却板１３を配置してもよい。   FIG. 3 shows a case where there is one semiconductor element 1 and one metal cooling plate 13. However, when a plurality of semiconductor elements 1 are mounted on a module, the semiconductor element 1 is placed at a position corresponding to each semiconductor element 1. A metal cooling plate 13 may be disposed. Further, for example, in the case of a semiconductor module in which a plurality of IGBT semiconductor chips and a plurality of free-wheeling diode chips are mounted, the metal cooling plate 13 is provided only at a position corresponding to the semiconductor element 1 having a large calorific value, that is, the plurality of IGBT semiconductor chips. May be arranged.

なお、本実施例の半導体モジュールも実施例１の半導体モジュールと同様に、内部で半導体素子１や電極配線８ａ、８ｂと支持基板６や金属製冷却板１３とが絶縁されているので、半導体モジュールの上面や下面に金属製の冷却フィンなどを絶縁材を介さずにそのまま設置できる。   In addition, since the semiconductor element 1 and the electrode wirings 8a and 8b and the support substrate 6 and the metal cooling plate 13 are insulated inside the semiconductor module of the present embodiment as well as the semiconductor module of the first embodiment, the semiconductor module A metal cooling fin or the like can be directly installed on the upper and lower surfaces of the glass without using an insulating material.

実施例１の半導体モジュールの断面模式図である。1 is a schematic cross-sectional view of a semiconductor module of Example 1. FIG. 従来技術の半導体モジュールの断面模式図である。It is a cross-sectional schematic diagram of the semiconductor module of a prior art. 実施例２の半導体モジュールの断面模式図である。6 is a schematic cross-sectional view of a semiconductor module of Example 2. FIG.

符号の説明Explanation of symbols

１…半導体素子、２ａ、２ｂ、２ｃ、２ｄ…ソルダー、３…絶縁基板、４ａ、４ｂ…金属層、５ａ、５ｂ…ろう材、６…支持基板、７…ゲル、７ａ…高放熱樹脂、８…金属ワイヤ、８ａ…電極配線、９ａ、９ｂ、９ｃ…配線端子、１０…樹脂体、１１…空隙部、１２…接着剤、１３…金属製冷却板、１４…上部蓋。   DESCRIPTION OF SYMBOLS 1 ... Semiconductor element, 2a, 2b, 2c, 2d ... Solder, 3 ... Insulating substrate, 4a, 4b ... Metal layer, 5a, 5b ... Brazing material, 6 ... Support substrate, 7 ... Gel, 7a ... High heat dissipation resin, 8 DESCRIPTION OF SYMBOLS ... Metal wire, 8a ... Electrode wiring, 9a, 9b, 9c ... Wiring terminal, 10 ... Resin body, 11 ... Gap part, 12 ... Adhesive, 13 ... Metal cooling plate, 14 ... Top lid.

Claims (8)

底面の金属支持基板と、該金属支持基板にろう材を介して搭載した絶縁基板と、該絶縁基板に別のろう材と金属層とを介して搭載した半導体素子と、該半導体素子の上に絶縁樹脂を介して配置した金属製冷却板とを備えたパワー半導体装置において、
前記絶縁樹脂が、熱伝導率が５Ｗ／ｍＫ以上の絶縁樹脂であることを特徴とするパワー半導体装置。 A metal support substrate on a bottom surface, an insulating substrate mounted on the metal support substrate via a brazing material, a semiconductor element mounted on the insulating substrate via another brazing material and a metal layer, and on the semiconductor element In a power semiconductor device comprising a metal cooling plate disposed via an insulating resin,
The power semiconductor device, wherein the insulating resin is an insulating resin having a thermal conductivity of 5 W / mK or more. 請求項１に記載のパワー半導体装置において、前記半導体素子と金属冷却板との間に配置した絶縁樹脂の厚さが０.２mmから２mmであることを特徴とするパワー半導体装置。   2. The power semiconductor device according to claim 1, wherein the insulating resin disposed between the semiconductor element and the metal cooling plate has a thickness of 0.2 mm to 2 mm. 請求項１に記載のパワー半導体装置において、前記パワー半導体装置上面に露出した前記金属冷却板の面積が前記半導体素子を搭載した絶縁基板の面積より広いことを特徴とするパワー半導体装置。   2. The power semiconductor device according to claim 1, wherein an area of the metal cooling plate exposed on an upper surface of the power semiconductor device is larger than an area of an insulating substrate on which the semiconductor element is mounted. 請求項３に記載のパワー半導体装置において、前記絶縁基板に搭載された半導体素子が、シリコンチップに形成したＩＧＢＴであることを特徴とするパワー半導体装置。   4. The power semiconductor device according to claim 3, wherein the semiconductor element mounted on the insulating substrate is an IGBT formed on a silicon chip. 請求項１に記載のパワー半導体装置において、前記金属製冷却板が前記半導体素子に向かって凸の形状であって、パワー半導体装置上面に露出した前記金属冷却板が平坦であることを特徴とするパワー半導体装置。   2. The power semiconductor device according to claim 1, wherein the metal cooling plate has a convex shape toward the semiconductor element, and the metal cooling plate exposed on the upper surface of the power semiconductor device is flat. Power semiconductor device. 請求項５に記載のパワー半導体装置において、前記パワー半導体装置上面に露出した前記金属冷却板の面積が前記半導体素子を搭載した絶縁基板の面積より小さいことを特徴とするパワー半導体装置。   6. The power semiconductor device according to claim 5, wherein an area of the metal cooling plate exposed on an upper surface of the power semiconductor device is smaller than an area of an insulating substrate on which the semiconductor element is mounted. 請求項６に記載のパワー半導体装置において、前記パワー半導体装置が複数個の半導体素子と、複数個の前記金属製冷却板を備えていることを特徴とするパワー半導体装置。   The power semiconductor device according to claim 6, wherein the power semiconductor device includes a plurality of semiconductor elements and a plurality of the metal cooling plates. 請求項６に記載のパワー半導体装置において、前記絶縁基板に搭載された半導体素子が、シリコンチップに形成したＩＧＢＴであることを特徴とするパワー半導体装置。
7. The power semiconductor device according to claim 6, wherein the semiconductor element mounted on the insulating substrate is an IGBT formed on a silicon chip.
JP2005224828A 2005-08-03 2005-08-03 Power semiconductor device Expired - Fee Related JP4375299B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005224828A JP4375299B2 (en) 2005-08-03 2005-08-03 Power semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005224828A JP4375299B2 (en) 2005-08-03 2005-08-03 Power semiconductor device

Publications (2)

Publication Number Publication Date
JP2007042827A true JP2007042827A (en) 2007-02-15
JP4375299B2 JP4375299B2 (en) 2009-12-02

Family

ID=37800540

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005224828A Expired - Fee Related JP4375299B2 (en) 2005-08-03 2005-08-03 Power semiconductor device

Country Status (1)

Country Link
JP (1) JP4375299B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1961375A1 (en) 2007-02-22 2008-08-27 Alps Electric Co., Ltd. Vibration detecting device
JP2013149760A (en) * 2012-01-18 2013-08-01 Fuji Electric Co Ltd Semiconductor device
US10658261B2 (en) 2018-01-30 2020-05-19 Denso Corporation Semiconductor device
CN112771665A (en) * 2020-04-16 2021-05-07 华为技术有限公司 Packaging structure, electric vehicle and electronic device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1961375A1 (en) 2007-02-22 2008-08-27 Alps Electric Co., Ltd. Vibration detecting device
JP2013149760A (en) * 2012-01-18 2013-08-01 Fuji Electric Co Ltd Semiconductor device
US10658261B2 (en) 2018-01-30 2020-05-19 Denso Corporation Semiconductor device
CN112771665A (en) * 2020-04-16 2021-05-07 华为技术有限公司 Packaging structure, electric vehicle and electronic device
CN112771665B (en) * 2020-04-16 2024-05-24 华为数字能源技术有限公司 Packaging structure, electric vehicle and electronic device

Also Published As

Publication number Publication date
JP4375299B2 (en) 2009-12-02

Similar Documents

Publication Publication Date Title
JP4007304B2 (en) Semiconductor device cooling structure
KR100752239B1 (en) Power module package structure
JP4262453B2 (en) Power semiconductor device
WO2016174899A1 (en) Semiconductor device
JPH09139461A (en) Semiconductor power module
JP6813259B2 (en) Semiconductor device
JP2020072106A (en) Semiconductor device
JP2017108130A (en) Semiconductor module
JP2018133527A (en) Semiconductor device and semiconductor device manufacturing method
US11195775B2 (en) Semiconductor module, semiconductor device, and manufacturing method of semiconductor module
JP5222838B2 (en) Control device
CN107452688B (en) Semiconductor device with a plurality of semiconductor chips
JP2016004941A (en) Semiconductor device and power module
JP5301497B2 (en) Semiconductor device
JP4367376B2 (en) Power semiconductor device
JP4375299B2 (en) Power semiconductor device
JP2011199148A (en) Semiconductor device
CN107611111B (en) Semiconductor module and power conversion device
JP4046623B2 (en) Power semiconductor module and fixing method thereof
JPH10247702A (en) Ball grid array package and printed board
JP3855726B2 (en) Power module
JP2009231685A (en) Power semiconductor device
JP7170614B2 (en) semiconductor equipment
JP2007288044A (en) Semiconductor device
US20200120825A1 (en) Power electronic module

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070606

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20090529

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090609

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090727

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20090818

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20090831

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120918

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120918

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130918

Year of fee payment: 4

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

LAPS Cancellation because of no payment of annual fees