TW508778B - Package structure of semiconductor chip - Google Patents

Package structure of semiconductor chip Download PDF

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Publication number
TW508778B
TW508778B TW090125728A TW90125728A TW508778B TW 508778 B TW508778 B TW 508778B TW 090125728 A TW090125728 A TW 090125728A TW 90125728 A TW90125728 A TW 90125728A TW 508778 B TW508778 B TW 508778B
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TW
Taiwan
Prior art keywords
heat sink
heat
package structure
semiconductor wafer
semiconductor chip
Prior art date
Application number
TW090125728A
Other languages
Chinese (zh)
Inventor
Meng-Jen Wang
Chun-Jen Tseng
Tsung-Ming Pai
Wann-Lung Chien
Original Assignee
Advanced Semiconductor Eng
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Priority to TW090125728A priority Critical patent/TW508778B/en
Application granted granted Critical
Publication of TW508778B publication Critical patent/TW508778B/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

A package structure of semiconductor chip is disclosed, which comprises a substrate, a semiconductor chip, and a heat spreader. The semiconductor chip is electricaly connected to the substrate, the heat spreader is disposed on the semiconductor chip, and the heat spreader has the first heat sink part and the second heat sink part, the second heat sink part is disposed by extending from both opposing sides of the first heat sink part. With the heat spreader, the heat dissipation characteristics of the package structure of the semiconductor chip is even better, so as to achieve the purpose of fast heat dissipation.

Description

508778 五、發明說明（1) 【發明領域】 本發明係有關於一種半導體晶片封裝構造，尤關於一 種具有散熱片的半導體晶片封裝構造。 【習知技術】 近年來，電子產品係已朝向輕、薄、短、小及多功能 的方向發展，為因應此種發展趨勢，電子元件亦發展出高 I /0數的封裝型態。如高I / 0密度的覆晶（F 1 i p- Ch i P)封裝 技術’其係將半導體晶片的接合面翻覆朝下，利用如锡球 (solder bal 1 )之導體，使半導體晶片上之接點與基板之 接點電連接。由於覆晶接合技術具有接合引線短，傳輸延 遲低、高頻雜訊易於控制、及封裝體積縮小等優點，故係 已被廣泛地應用。 在半導體晶片高度集積化，且封裝構造尺寸的縮小情 況下’封裝構造之熱流密度（h e a t f 1 u X d e n s i t y )亦會隨 著提高。為有效地提高封裝構造的散熱速率，覆晶式的封 裝構造亦係具有多種型態，如圖1所示，係HFC —BGA(High performance Flip Chip Ball Grid Array)，該半導體晶 片封裝構造主要包括一基板11、一半導體晶片12、一散熱 片15(heat spreader)、及'一導献膠17。丰暮轉日Η 19夕 ^ t I, Τ ^ ^ ,；,(mentat t ； 接於基板11上，其中，此金屬凸塊13可為錫球（s〇lder ball)。此外，於幾何不連續處，亦即金屬凸塊^與半導 體晶片12，或金屬凸塊13與基板n的連接處，填充底膠508778 V. Description of the invention (1) [Field of the invention] The present invention relates to a semiconductor wafer package structure, and more particularly to a semiconductor wafer package structure with a heat sink. [Knowledge technology] In recent years, electronic products have been developed in the direction of light, thin, short, small, and multifunctional. In response to this development trend, electronic components have also developed high I / 0 package types. Such as high I / 0 density flip-chip (F 1 i p-Ch i P) packaging technology 'It is to flip the junction of the semiconductor wafer face down, using a conductor such as solder bal (solder bal 1), The contacts are electrically connected to the contacts of the substrate. The flip-chip bonding technology has been widely used because it has the advantages of short bonding wires, low transmission delay, easy control of high-frequency noise, and reduction in package size. When the semiconductor wafer is highly integrated and the package structure is reduced in size, the heat flow density (h e a t f 1 u X d en s i t y) of the package structure will also increase. In order to effectively improve the heat dissipation rate of the package structure, the flip-chip package structure also has a variety of types, as shown in Figure 1. It is HFC-BGA (High performance Flip Chip Ball Grid Array). The semiconductor chip package structure mainly includes A substrate 11, a semiconductor wafer 12, a heat spreader 15, and a guide adhesive 17. Twilight to the sun 19 t ^ t I, Τ ^ ^,;, (mentat t) is connected to the substrate 11, wherein the metal bump 13 may be a solder ball. In addition, The continuous place, that is, the connection between the metal bump ^ and the semiconductor wafer 12, or the connection between the metal bump 13 and the substrate n, is filled with primer.

第4頁 508778Page 4 508778

(underfill)14 ’進而免除封裝構造受力時，產生應力集 中之現象。 ^ 錫球（solder bal 1)19係植於連接半導體晶片12之基 板11面的相對面上，以訊號連接電路板或其他之電子元 件。散熱片1 5係以導熱膠1 7黏著於半導體晶片1 2上，故藉 著散熱片15可使半導體晶片12所產生之熱量，傳導至半導 體晶片封裝構造1外。 然而’如圖1所示，散熱片1 5係以導熱膠1 7黏著於半 導體晶片12上，亦即採用DLA(direct lid attach)技術來 貼附散熱片1 7，其中，散熱片1 5與半導體晶片i 2之間的間 距稱作BLT(bond line thickness) °BLT係越小越佳，因 為若BLT太大，則填充於BLT間之導熱膠1 7太厚，將導致導 熱性不佳的問題，亦即無法達到良好之散熱效果；但若 BLT太小，則導熱膠17太薄，容易造成散熱片15與半導體 晶片1 2間黏著強度不足之問題。 此外，散熱片1 5係以導熱膠1 7直接黏著於半導體晶片 11上，容易產生散熱片1 5傾斜的問題，在此種狀況下，將 導致導熱膠17產生孔洞（void)或脫層（delamination)現 象，以致於降低半導體晶片封裝構造1之散熱效果。 因此，如何製作出定位容易、散熱效果佳之散熱片， 據以提昇半導體晶片封裝構造散熱速率實為一重要的課 題。 【發明概要】(underfill) 14 'further eliminates the phenomenon of stress concentration when the package structure is stressed. ^ Solder bal 1 19 is planted on the opposite side of the substrate 11 to which the semiconductor wafer 12 is connected, and connects to the circuit board or other electronic components with signals. The heat sink 15 is adhered to the semiconductor wafer 12 with a thermally conductive adhesive 17. Therefore, the heat generated by the semiconductor wafer 12 can be conducted to the outside of the semiconductor chip packaging structure 1 through the heat sink 15. However, as shown in FIG. 1, the heat sink 15 is adhered to the semiconductor wafer 12 with a thermally conductive adhesive 17, that is, the DLA (direct lid attach) technology is used to attach the heat sink 17. Among them, the heat sink 15 and The distance between semiconductor wafers i 2 is called BLT (bond line thickness) ° The smaller the BLT, the better, because if the BLT is too large, the thermally conductive adhesive 17 filled between the BLTs is too thick, which will lead to poor thermal conductivity. The problem is that a good heat dissipation effect cannot be achieved; however, if the BLT is too small, the thermal conductive adhesive 17 is too thin, which may easily cause the problem of insufficient adhesion strength between the heat sink 15 and the semiconductor wafer 12. In addition, the heat sink 15 is directly adhered to the semiconductor wafer 11 with a thermally conductive adhesive 17, which tends to cause the tilting of the heat sink 15. Under this condition, the thermally conductive adhesive 17 will cause voids or delamination ( delamination) phenomenon, so that the heat dissipation effect of the semiconductor chip package structure 1 is reduced. Therefore, how to make a heat sink with easy positioning and good heat dissipation effect to improve the heat dissipation rate of the semiconductor chip package structure is an important issue. [Summary of Invention]

第5頁 屬778 五、發明說明（3) 有鑑於上述的課題，故 散熱效率高之半導體晶片封 又，本發明之另一目的 定位容易之散熱片。 而，本發明之特徵係藉 提昇散熱片之散熱速率、及 因此，為達上述目的， 封裝構造’包括一基板、一 中，該散熱片係具有一第一 第二散熱部係分別自第一散 由該散熱片之第二散熱部則 藉由該第〆散熱部及第二散 可於一方向上具有開放之構 承上所述，藉由本發明 散熱片係以第一散熱部兩側 可避免散熱片傾斜等定位性 明之半導體晶片封裝構造， 來散逸熱量，故可提升半導 本發明之目的係在於提供一種 裝構造。 係在於提供一種散熱效果佳、 由提供特殊型態之散熱片，以 達到其容易定位之目的。 本發明係提供一種半導體晶片 半導體晶片、及一散熱片。其 散熱部及一對第二散熱部，該 熱部相對之兩側彎延設置。藉 可使散熱片之定位容易，同時 熱部連續延設，因此該散熱片 成，所以可以提高散熱效率。 之半導體晶片封裝構造，由於 之第一散熱部定位於基板’故 不佳之問題。此外，藉由本發 由於散熱片可利用開放之雨側 體晶片封裝構造之散熱效率。 【較佳實施例之詳細說明】 以下將爹考相關圖式，來說明本發明較佳實施例之半 導體晶片的封裝構造。 如圖2所不，本發明之半導體封裝構造2主要包括一基 板21、一半導體晶片22、及一散熱片25。半導體晶片22係Page 5 778 V. Description of the invention (3) In view of the above-mentioned problems, a semiconductor wafer with high heat dissipation efficiency is sealed. Another object of the present invention is a heat sink with easy positioning. However, the feature of the present invention is to increase the heat dissipation rate of the heat sink, and therefore, in order to achieve the above-mentioned purpose, the package structure includes a substrate and a heat sink, and the heat sink has a first and a second heat sink respectively from the first The second heat dissipating part of the heat dissipating fin is described by the first heat dissipating part and the second dispersing structure which can be opened in one direction. The heat dissipating fin of the present invention can be avoided on both sides of the first heat dissipating part A semiconductor chip package structure with a well-defined positioning such as a heat sink is used to dissipate heat, so the semiconductor can be improved. The object of the present invention is to provide a mounting structure. It is to provide a heat sink with good heat dissipation effect, and provide a special type of heat sink to achieve its purpose of easy positioning. The invention provides a semiconductor wafer, a semiconductor wafer, and a heat sink. The heat radiating portion and a pair of second heat radiating portions are arranged on opposite sides of the heat portion. The positioning of the heat sink can be made easier, and the heating section can be continuously extended. Therefore, the heat sink is formed, and the heat dissipation efficiency can be improved. The semiconductor chip package structure has a problem in that the first heat radiation portion is positioned on the substrate '. In addition, the heat sink can utilize the heat dissipation efficiency of the open rain side chip package structure. [Detailed description of the preferred embodiment] The related drawings will be used to explain the packaging structure of the semiconductor wafer according to the preferred embodiment of the present invention. As shown in FIG. 2, the semiconductor package structure 2 of the present invention mainly includes a substrate 21, a semiconductor wafer 22, and a heat sink 25. Semiconductor wafer 22 series

508778 五、發明說明（4) 將接合面翻覆朝下，以金屬凸塊23使半導體晶片22上之接 點與基板21的接點電連接，其中，金屬凸塊23為錫球 (Solder Ball)。此外，為避免封裝構造受力時，應力集 中於幾何不，連續處，亦即金屬凸塊23與半導體晶片22，或 金屬凸塊23與基板21的連接處，填充底膠（underfiU)24 或其他具相同作用之填充體，以使受力能夠均勻分布，避 免應力集中造成之破壞。再者，於連接半導體晶片22之基 板2/面的相對面上植上錫球29或其他之凸塊（bump)，據以 訊唬連接電路板或其他之電子元件。散熱片25係以銀膠 28 (silver epoxy)定位於基板21上，且以導熱膠μ填充於 半導體晶片22與散熱片25間的間隙，以使半導體晶片22的 熱量能夠藉由導熱膠27傳導至半導體封裝構造2之外。 如圖3所示，係本發明較佳實施例之散熱片的立體 圖。散熱片2 5具有第一散熱部2 5 j及一對第二散熱部2 5 2， 其中1该等第二散熱部2 5 2係分別自第一散熱部2 5 1相對之 兩側★延设置。為明瞭起見，請再參照圖4及圖5。 圖6所示者係散熱片25安裝於基板21時之狀態，且散 f片25係以銀膠28(請參照圖2)黏著於基板21上。在本實 施例中’半導體晶片22之尺寸係可朝圖6中X方向延伸，直 至基板21之端緣。因為，於前述方向上，散熱片25係具開 t性開口 ’也由於此開口係位於散熱片相對之兩側，故熱 量亦可自此兩側迅速散逸。 ^ 7為本發明較佳實施例之散熱片的第二實施態樣， 於本貫施例中’散熱片3 5係包括一第一散熱部3 5 1、及一508778 V. Description of the invention (4) Turn the joint surface downward, and use metal bumps 23 to electrically connect the contacts on the semiconductor wafer 22 and the contacts of the substrate 21, wherein the metal bumps 23 are solder balls. . In addition, in order to avoid stress when the package structure is stressed, the stress is concentrated on the geometric discontinuity, that is, the connection between the metal bump 23 and the semiconductor wafer 22 or the connection between the metal bump 23 and the substrate 21 is filled with an underfiber 24 or Other fillers with the same effect, so that the force can be evenly distributed to avoid damage caused by stress concentration. Furthermore, solder balls 29 or other bumps are planted on the opposite side of the substrate 2 / side connected to the semiconductor wafer 22 to connect the circuit board or other electronic components accordingly. The heat sink 25 is positioned on the substrate 21 with silver epoxy 28, and the gap between the semiconductor wafer 22 and the heat sink 25 is filled with a heat conductive glue μ so that the heat of the semiconductor wafer 22 can be conducted by the heat conductive glue 27 Outside the semiconductor package structure 2. As shown in FIG. 3, it is a perspective view of a heat sink of a preferred embodiment of the present invention. The heat sink 25 has a first heat sink 2 5 j and a pair of second heat sinks 2 5 2, among which the second heat sinks 2 5 2 are respectively extended from opposite sides of the first heat sink 2 5 1 Settings. For clarity, please refer to FIG. 4 and FIG. 5 again. The heat sink 25 shown in FIG. 6 is a state when the heat sink 25 is mounted on the substrate 21, and the heat sink 25 is adhered to the substrate 21 with a silver paste 28 (see FIG. 2). In this embodiment, the size of the 'semiconductor wafer 22 can be extended in the X direction in FIG. 6 to the edge of the substrate 21. Because, in the aforementioned direction, the heat sink 25 has a t-shaped opening ′. Since this opening is located on two opposite sides of the heat sink, the heat can also be quickly dissipated from the two sides. ^ 7 is the second embodiment of the heat sink of the preferred embodiment of the present invention. In this embodiment, the heat sink 3 5 includes a first heat sink 3 5 1 and a

第7頁 508778 五、發明說明（5) 對第二散熱部3 5 2，其中，第二散熱部3 5 2係分別自第一散 熱部3 5 1相對之兩侧垂直延伸設置。圖8為散熱片3 5之俯視 圖。圖9為散熱片3 5之側視圖。 綜上所述，由於半導體晶片可藉由導熱膠以將熱量傳 導至散熱片，且此散熱片之相對兩側為開放性的，故更可 增加散熱速率。此外，散熱片之相對兩側為開放性的，因 此半導體晶片係可自散熱片開放性之相對兩端延展，故此 散熱片係能配合多種尺寸之半導體晶片。再者，由於此散 熱片定位容易，故可解決前述BLT控制困難、及散熱片傾 斜之問題。 ”、 於本實施例之詳細說明中所提出之具體的實施 了易於說明本發明之技術内容，而並非將本笋 … 制於該實施例，在不超出本發明之精神及以^ 、丨限 圍之情況，可作種種變化實施。 明專利範Page 7 508778 V. Description of the invention (5) For the second heat radiating portion 3 5 2, the second heat radiating portion 3 5 2 is vertically extended from the opposite sides of the first heat radiating portion 3 5 1 respectively. Fig. 8 is a plan view of the heat sink 35. Fig. 9 is a side view of the heat sink 35. In summary, since the semiconductor wafer can conduct heat to the heat sink through a thermally conductive adhesive, and the opposite sides of the heat sink are open, the heat dissipation rate can be increased. In addition, the opposite sides of the heat sink are open, so the semiconductor chip can extend from the opposite ends of the openness of the heat sink, so the heat sink can be used with semiconductor wafers of various sizes. Furthermore, since the positioning of the heat sink is easy, the problems of difficult BLT control and tilt of the heat sink can be solved. ", The specific implementation proposed in the detailed description of this embodiment is easy to explain the technical content of the present invention, rather than the bamboo shoots ... made in this embodiment, without exceeding the spirit of the present invention and the ^, 丨 limit Circumstances can be implemented in various changes.

508778 圖式簡單說明 【圖式之簡單說明】 圖1為一示意圖，顯示習知HFC-BGA型之半導體晶片封 裝構造。 圖2為一示意圖，顯示本發明較佳實施例之半導體晶 片封裝構造。 圖3為一立體圖，顯示本發明較佳實施例之散熱片。 圖4為一俯視圖，顯示本發明較佳實施例之散熱片。 圖5為一側視圖，顯示本發明較佳實施例之散熱片。 圖6為一示意圖，顯示發明較佳實施例之散熱片安裝 之狀態。 圖7為一立體圖，顯示本發明較佳實施例之散熱片另 一實施態樣。 圖8為一俯視圖，顯示本發明較佳實施例之散熱片另 一實施態樣。 圖9為一側視圖，顯示本發明較佳實施例之散熱片另 - 實 施 態 樣 0 [ 圖 式 符 號 說 明 ] 1 半 導 體 晶 片封裝構造 11 基 板 12 半 導 體 晶 片 13 金 屬 凸 塊 14 底 膠 15 散 孰 片508778 Brief description of the drawings [Simplified description of the drawings] Fig. 1 is a schematic diagram showing a conventional HFC-BGA type semiconductor wafer package structure. FIG. 2 is a schematic diagram showing a semiconductor wafer package structure according to a preferred embodiment of the present invention. FIG. 3 is a perspective view showing a heat sink of a preferred embodiment of the present invention. FIG. 4 is a top view showing a heat sink of a preferred embodiment of the present invention. FIG. 5 is a side view showing a heat sink of a preferred embodiment of the present invention. Fig. 6 is a schematic view showing a state in which a heat sink is installed according to a preferred embodiment of the present invention. Fig. 7 is a perspective view showing another embodiment of the heat sink of the preferred embodiment of the present invention. Fig. 8 is a plan view showing another embodiment of the heat sink of the preferred embodiment of the present invention. FIG. 9 is a side view showing another embodiment of the heat sink of the present invention-the implementation state 0 [illustration of the symbol] 1 semiconductor chip packaging structure 11 base plate 12 semiconductor chip 13 metal bumps 14 primer 15 scatter sheet

508778508778

第ίο頁 圖式簡單說明 17 導熱膠 19 錫球 2 半導體封裝構造 21 基板 22 半導體晶片 23 金屬凸塊 24 底膠 25 散熱片 251 第一散熱部 252 第二散熱部 27 導熱膠 28 銀膠 29 錫球 35 散熱片 351 第一散熱部 352 第二散熱部Brief description of the drawings on page ο 17 Thermal conductive adhesive 19 Solder ball 2 Semiconductor package structure 21 Substrate 22 Semiconductor wafer 23 Metal bump 24 Primer 25 Heat sink 251 First heat sink 252 Second heat sink 27 Thermal paste 28 Silver paste 29 Tin Ball 35 heat sink 351 first heat sink 352 second heat sink

Claims (1)

508778 六、申請專利範圍 1. 一種半導體晶片封裝構造，包含： 一基板； 一半導體晶片，係電連接於該基板上；及 一散熱片，係設於該半導體晶片上，其具有一第一散 熱部及一對第二散熱部，其中，該等第二散熱部係分別自 該第一散熱部相對之兩側彎延設置。 2. 申請專利範圍第1項之半導體晶片封裝構造，其中該第 一散熱部及該第二散熱部係一體成型。 、508778 6. Scope of patent application 1. A semiconductor wafer package structure, comprising: a substrate; a semiconductor wafer electrically connected to the substrate; and a heat sink provided on the semiconductor wafer, which has a first heat sink And a pair of second heat radiating portions, wherein the second heat radiating portions are respectively bent and disposed from opposite sides of the first heat radiating portion. 2. The semiconductor chip package structure of the first scope of the patent application, wherein the first heat radiation part and the second heat radiation part are integrally formed. , 3. 如申請專利範圍第1項之半導體晶片封裝構造，其中該 半導體晶片係以覆晶型態與該基板電連接。 4. 如申請專利範圍第1項之半導體晶片封裝構造，更包 含： 一填充體，其係填充於該基板與該半導體晶片之間。3. The semiconductor wafer package structure according to item 1 of the patent application scope, wherein the semiconductor wafer is electrically connected to the substrate in a flip-chip type. 4. The semiconductor chip package structure according to item 1 of the patent application scope further includes: a filler body which is filled between the substrate and the semiconductor wafer. 5. 如申請專利範圍第1項之半導體晶片封裝構造，更包 含： 複數個凸塊，其係置於該基板與該半導體晶片電連接 之一面的相對面上。 6.如申請專利範圍第5項之半導體晶片封裝構造，其中該 凸塊係錫球。5. The semiconductor chip package structure according to item 1 of the scope of patent application, further comprising: a plurality of bumps, which are disposed on the opposite side of one side of the substrate and the semiconductor wafer which is electrically connected. 6. The semiconductor chip package structure according to item 5 of the patent application scope, wherein the bump is a solder ball. 第11頁 508778 六、申請專利範圍 * 7. —種用於半導體晶片封裝構造之散熱片，包含： 一第一散熱部；及 一對第二散熱部，其係分別自該第一散熱部相對之兩 側彎延設置。 8. 申請專利範圍第7項之用於半導體晶片封裝構造之散熱 片，其中該第一散熱部及該第二散熱部係一體成型。Page 11 508778 6. Scope of patent application * 7. A heat sink for semiconductor chip package structure, including: a first heat sink; and a pair of second heat sinks, which are opposed to the first heat sink respectively. Curved on both sides. 8. The heat sink for a semiconductor chip package structure according to item 7 of the patent application, wherein the first heat sink and the second heat sink are integrally formed. 第12頁Page 12
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6747350B1 (en) 2003-06-06 2004-06-08 Silicon Integrated Systems Corp. Flip chip package structure
US7015577B2 (en) 2004-07-21 2006-03-21 Advanced Semiconductor Engineering, Inc. Flip chip package capable of measuring bond line thickness of thermal interface material

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6747350B1 (en) 2003-06-06 2004-06-08 Silicon Integrated Systems Corp. Flip chip package structure
US7015577B2 (en) 2004-07-21 2006-03-21 Advanced Semiconductor Engineering, Inc. Flip chip package capable of measuring bond line thickness of thermal interface material

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