JP3922809B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP3922809B2
JP3922809B2 JP19351698A JP19351698A JP3922809B2 JP 3922809 B2 JP3922809 B2 JP 3922809B2 JP 19351698 A JP19351698 A JP 19351698A JP 19351698 A JP19351698 A JP 19351698A JP 3922809 B2 JP3922809 B2 JP 3922809B2
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Prior art keywords
heat
semiconductor chip
radiating plate
heat radiating
semiconductor device
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JP2000031351A (en
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敏郎 久保田
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Toshiba Corp
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Toshiba Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73207—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、放熱効果の高い半導体装置に関する。
【０００２】
【従来の技術】
集積回路（ＩＣ）の中でも、特にパワーＩＣの分野においては、樹脂封止したＩＣの発熱を効率的に放熱させるため、放熱板の一方の面上にチップを装着し、さらに放熱板のもう一方の面を樹脂封止後も露出させることによって、放熱効果を高め、熱抵抗を低減していた。
【０００３】
図４は、従来技術による半導体装置の断面図である。放熱板２１の一方の面に半導体チップ２２が装着され、半導体チップ２２の各々の電極は、ボンディングワイヤ２４により対応したリードフレーム２３の各々に電気的に接続され、放熱板２１、半導体チップ２２、リードフレーム２３およびボンディングワイヤ２４は、樹脂２５によって封止されている。放熱板２１の一方の面は露出されている。
【０００４】
【発明が解決しようとする課題】
このように従来技術では、半導体チップの裏面に装着された放熱板によって、半導体チップから出る熱を半導体チップの裏面から放熱板に伝えて発散させていたが、半導体チップの裏面からの熱の発散では十分ではない。また、半導体装置の小型化により、放熱板の大きさも小さくなるので、半導体チップの裏面に装着された放熱板からのみでは、熱の発散の効率が悪くなる。
本発明の目的は、放熱効果の高い半導体装置を提供するものである。
【０００７】
【課題を解決するための手段】
本発明の半導体装置は、半導体チップと、前記半導体チップの一方の面に装着された第１の放熱板と、前記半導体チップのもう一方の面である能動素子面側に形成されたバンプと、前記バンプを介して前記半導体チップと電気的に接続されたベース基板と、前記ベース基板に形成され且つ前記バンプに装着されている第２の放熱板とを具備している。本発明によれば、半導体チップの能動素子面側に放熱板を装着させることにより、半導体チップから出る熱を効率的に発散することができる。
【０００８】
【発明の実施の形態】
以下、図面を参照しながら本発明の実施の形態について説明する。
図１は、本発明による第１の実施の形態の半導体装置における断面図である。第１の放熱板１１に半導体チップ１２が装着されている。半導体チップ１２の各々の電極は、ボンディングワイヤ１４により対応したリードフレーム１３の各々の電極に電気的に接続されている。第１の放熱板１１は、銅またはその他の金属である。半導体チップ１２の最も熱を放出するパワートランジスタ領域１２ａにバンプ１６が形成されている。例えば半田であるバンプ１６を介してパワートランジスタ領域１２ａ上に、第２の放熱板１７が直接装着されている。第２の放熱板１７は、銅あるいはその他の金属で、ボンディングワイヤ１４とは接触していない。第１の放熱板１１、半導体チップ１２、リードフレーム１３、ボンディングワイヤ１４、バンプ１６および第２の放熱板１７は、樹脂１５で被覆されている。第１の放熱板１１および第２の放熱板１７の一方の面は、露出されている。
【０００９】
パワートランジスタ領域１２ａの能動素子面側にバンプ１６を介して直接第２の放熱板１７を装着させることにより、放熱面積が増え、パワートランジスタ領域１２ａから出る熱を第２の放熱板１７で効率的に発散させることができる。
【００１０】
図２は、本発明による第２の実施の形態の半導体装置における断面図である。第１の放熱板１１に半導体チップ１２が装着されている。半導体チップ１２の各々の電極は、ボンディングワイヤ１４により対応したリードフレーム１３の各々の電極に電気的に接続されている。第１の放熱板１１は、銅あるいはその他の金属である。半導体チップ１２のパワートランジスタ領域１２ａにバンプ１６が形成されている。第２の放熱板１７は、例えば半田であるバンプ１６を介してパワートランジスタ領域１２ａ上に直接装着され、且つ第１の放熱板１１と接触させている。銅あるいはその他の金属である第２の放熱板１７は、ボンディングワイヤ１４とは接触していない。第１の放熱板１１、半導体チップ１２、リードフレーム１３、ボンディングワイヤ１４、バンプ１６および第２の放熱板１７は、樹脂１５で封止されている。第１の放熱板１１の一方の面および第２の放熱板１７の一方の少なくとも一部の面は、露出されている。
【００１１】
パワートランジスタ領域１２ａの能動素子面側にバンプ１６を介して第２の放熱板１７を直接装着させることにより、放熱面積が増え、パワートランジスタ領域１２ａから出る熱を第２の放熱板１７で効率的に発散させることができる。また、第１の放熱板１１の方が第２の放熱板１７よりも面積が大きくとれる場合、第２の放熱板１７の一部を第１の放熱板１１に接触させることにより、第２の放熱板１７に伝わった熱を第１の放熱板１１から発散することができる。
【００１２】
尚、図１および図２において、第２の放熱板１７はボンディングワイヤ１４の領域上には形成されていないが、ボンディングワイヤ１４に接触しなければ、第２の放熱板１７の大きさは問わない。また、第２の放熱板１７を第１の放熱板１１に接触させるのは、樹脂よりも熱伝導率がいい放熱路を介してもよい。
【００１３】
図３は、本発明による第３の実施の形態の半導体装置における断面図である。第１の放熱板１１に半導体チップ１２が装着されている。第１の放熱板１１は、銅あるいはその他の金属である。半導体チップ１２およびパワートランジスタ領域１２ａにバンプ１６が形成されている。バンプ１６を介してＣＳＰ（ＣｈｉｐＳｉｚｅ Ｐａｃｋａｇｅ）基板１８が装着されている。ＣＳＰ基板１８上に半田ボール１９が形成されている。半導体チップ１２および半田ボール１９は、電気的に接続されている。半導体チップ１２にバンプ１６を介してＣＳＰ基板１８の第２の放熱板１８ａが直接装着されている。第１の放熱板１１、半導体チップ１２、パンプ１６およびＣＳＰ基板１８は、樹脂１５で封止されている。第１の放熱板１１およびＣＳＰ基板１８の一方の面は、露出されている。
【００１４】
パワートランジスタ領域１２ａの能動素子面側にバンプ１６を介してＣＳＰ基板１８に形成された第２の放熱板１８ａを直接装着させることにより、放熱面積が増え、パワートランジスタ領域１２ａから出る熱をＣＳＰ基板１８の第２の放熱板１８ａから効率的に放熱ができる。
【００１５】
尚、図１、図２および図３では、第１の放熱板１１は、一方の面を露出して樹脂１５で封止されているが、第１の放熱板１１は封止している樹脂１５より突出していてもよい。
【００１６】
本発明の実施の形態では、第２の放熱板の接続はパワートランジスタ領域としているが、半導体チップの放熱する領域ならパワートランジスタ領域以外でもよい。
【００１７】
【発明の効果】
最も熱を放出するパワートランジスタの能動素子面側にバンプを介して第２の放熱板を装着させることにより、放熱面積が増え、直接第２の放熱板に熱を伝えられるため、パワートランジスタ領域から出る熱を第２の放熱板から効率的に発散することができる。
【図面の簡単な説明】
【図１】本発明による第１の実施の形態の半導体装置における断面図
【図２】本発明による第２の実施の形態の半導体装置における断面図
【図３】本発明による第３の実施の形態の半導体装置における断面図
【図４】従来技術による半導体装置における断面図
【符号の説明】
１１…第１の放熱板
１２…半導体チップ
１２ａ…パワートランジスタ領域
１３…リードフレーム
１４…ボンディングワイヤ
１５…樹脂
１６…バンプ
１７…第２の放熱板
１８…ＣＳＰ基板
１８ａ…第２の放熱板
１９…半田ボール
２１…放熱板
２２…半導体チップ
２３…リードフレーム
２４…ボンディングワイヤ
２５…樹脂[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a high heat dissipation effect.
[0002]
[Prior art]
Among the integrated circuits (ICs), particularly in the field of power ICs, in order to efficiently dissipate the heat generated by the resin-sealed IC, a chip is mounted on one side of the heat sink and the other side of the heat sink. The surface was exposed even after resin sealing, thereby increasing the heat dissipation effect and reducing the thermal resistance.
[0003]
FIG. 4 is a cross-sectional view of a conventional semiconductor device. A semiconductor chip 22 is mounted on one surface of the heat sink 21, and each electrode of the semiconductor chip 22 is electrically connected to each corresponding lead frame 23 by a bonding wire 24, and the heat sink 21, the semiconductor chip 22, The lead frame 23 and the bonding wire 24 are sealed with a resin 25. One surface of the heat sink 21 is exposed.
[0004]
[Problems to be solved by the invention]
As described above, in the conventional technique, the heat radiating plate mounted on the back surface of the semiconductor chip transmits heat from the semiconductor chip to the heat radiating plate from the back surface of the semiconductor chip, but the heat is radiated from the back surface of the semiconductor chip. Is not enough. Further, since the size of the heat sink is reduced due to the miniaturization of the semiconductor device, the efficiency of heat dissipation is deteriorated only from the heat sink attached to the back surface of the semiconductor chip.
An object of the present invention is to provide a semiconductor device having a high heat dissipation effect.
[0007]
[Means for Solving the Problems]
The semiconductor device of the present invention includes a semiconductor chip, a first heat dissipation plate mounted on one surface of the semiconductor chip, a bump formed on the active element surface side which is the other surface of the semiconductor chip, A base substrate electrically connected to the semiconductor chip via the bumps; and a second heat radiating plate formed on the base substrate and attached to the bumps. According to the present invention, the heat emitted from the semiconductor chip can be efficiently dissipated by mounting the heat sink on the active element surface side of the semiconductor chip.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a cross-sectional view of the semiconductor device according to the first embodiment of the present invention. A semiconductor chip 12 is attached to the first heat radiating plate 11. Each electrode of the semiconductor chip 12 is electrically connected to each electrode of the corresponding lead frame 13 by a bonding wire 14. The 1st heat sink 11 is copper or another metal. Bumps 16 are formed in the power transistor region 12 a that emits the most heat of the semiconductor chip 12. For example, the second heat radiating plate 17 is directly mounted on the power transistor region 12a via bumps 16 that are solder. The second heat radiating plate 17 is made of copper or other metal and is not in contact with the bonding wire 14. The first heat radiating plate 11, the semiconductor chip 12, the lead frame 13, the bonding wires 14, the bumps 16, and the second heat radiating plate 17 are covered with a resin 15. One surface of the first heat radiating plate 11 and the second heat radiating plate 17 is exposed.
[0009]
By attaching the second heat radiating plate 17 directly to the active element surface side of the power transistor region 12a via the bump 16, the heat radiating area is increased, and the heat radiated from the power transistor region 12a is efficiently generated by the second heat radiating plate 17. Can be diverged.
[0010]
FIG. 2 is a cross-sectional view of the semiconductor device according to the second embodiment of the present invention. A semiconductor chip 12 is attached to the first heat radiating plate 11. Each electrode of the semiconductor chip 12 is electrically connected to each electrode of the corresponding lead frame 13 by a bonding wire 14. The 1st heat sink 11 is copper or another metal. Bumps 16 are formed in the power transistor region 12 a of the semiconductor chip 12. The second heat radiating plate 17 is directly mounted on the power transistor region 12 a via bumps 16 made of, for example, solder, and is in contact with the first heat radiating plate 11. The second heat radiating plate 17 made of copper or other metal is not in contact with the bonding wire 14. The first heat radiation plate 11, the semiconductor chip 12, the lead frame 13, the bonding wires 14, the bumps 16, and the second heat radiation plate 17 are sealed with a resin 15. One surface of the first heat radiating plate 11 and at least a part of one surface of the second heat radiating plate 17 are exposed.
[0011]
By directly attaching the second heat radiating plate 17 to the active element surface side of the power transistor region 12a via the bump 16, the heat radiating area is increased, and the heat radiated from the power transistor region 12a is efficiently generated by the second heat radiating plate 17. Can be diverged. Further, when the area of the first heat radiating plate 11 can be larger than that of the second heat radiating plate 17, a part of the second heat radiating plate 17 is brought into contact with the first heat radiating plate 11. The heat transmitted to the heat sink 17 can be dissipated from the first heat sink 11.
[0012]
In FIG. 1 and FIG. 2, the second heat radiating plate 17 is not formed on the area of the bonding wire 14, but if it does not contact the bonding wire 14, the size of the second heat radiating plate 17 is not limited. Absent. Further, the second heat radiating plate 17 may be brought into contact with the first heat radiating plate 11 through a heat radiating path having better thermal conductivity than the resin.
[0013]
FIG. 3 is a sectional view of the semiconductor device according to the third embodiment of the present invention. A semiconductor chip 12 is attached to the first heat radiating plate 11. The 1st heat sink 11 is copper or another metal. Bumps 16 are formed on the semiconductor chip 12 and the power transistor region 12a. A CSP (Chip Size Package) substrate 18 is mounted via the bumps 16. Solder balls 19 are formed on the CSP substrate 18. The semiconductor chip 12 and the solder ball 19 are electrically connected. The second heat radiating plate 18 a of the CSP substrate 18 is directly attached to the semiconductor chip 12 via the bumps 16. The first heat radiation plate 11, the semiconductor chip 12, the pump 16, and the CSP substrate 18 are sealed with a resin 15. One surface of the first heat radiation plate 11 and the CSP substrate 18 is exposed.
[0014]
By directly mounting the second heat radiating plate 18a formed on the CSP substrate 18 via the bumps 16 on the active element surface side of the power transistor region 12a, the heat radiating area is increased, and the heat generated from the power transistor region 12a is transferred to the CSP substrate. Heat can be efficiently radiated from the 18 second heat radiating plates 18a.
[0015]
In FIG. 1, FIG. 2 and FIG. 3, the first heat radiating plate 11 is sealed with resin 15 with one surface exposed, but the first heat radiating plate 11 is sealed resin. It may protrude from 15.
[0016]
In the embodiment of the present invention, the connection of the second heat radiating plate is in the power transistor region, but it may be other than the power transistor region as long as it is a region where the semiconductor chip dissipates heat.
[0017]
【The invention's effect】
By mounting the second heat sink on the active element side of the power transistor that emits the most heat via bumps, the heat dissipation area increases and heat can be directly transferred to the second heat sink. The emitted heat can be efficiently dissipated from the second heat sink.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view of a semiconductor device according to a second embodiment of the present invention. FIG. 4 is a cross-sectional view of a conventional semiconductor device.
DESCRIPTION OF SYMBOLS 11 ... 1st heat sink 12 ... Semiconductor chip 12a ... Power transistor area | region 13 ... Lead frame 14 ... Bonding wire 15 ... Resin 16 ... Bump 17 ... 2nd heat sink 18 ... CSP board | substrate 18a ... 2nd heat sink 19 ... Solder balls 21 ... heat sink 22 ... semiconductor chip 23 ... lead frame 24 ... bonding wire 25 ... resin

Claims (5)

半導体チップと、
前記半導体チップの一方の面に装着された第１の放熱板と、
前記半導体チップのもう一方の面である能動素子面側に形成されたバンプと、
前記バンプを介して前記半導体チップと電気的に接続されたベース基板と、
前記ベース基板に形成され且つ前記バンプに装着されている第２の放熱板と
を具備することを特徴とする半導体装置。A semiconductor chip;
A first heat sink mounted on one surface of the semiconductor chip;
Bumps formed on the active element surface side which is the other surface of the semiconductor chip,
A base substrate electrically connected to the semiconductor chip via the bumps;
And a second heat radiating plate formed on the base substrate and attached to the bump. 前記ベース基板上に形成され、前記半導体チップと電気的に接続される半田ボールを備えることを特徴とする請求項１記載の半導体装置。  The semiconductor device according to claim 1, further comprising a solder ball formed on the base substrate and electrically connected to the semiconductor chip. 前記ベース基板は、ＣＳＰ（Chip Size Package）基板であることを特徴とする請求項１又は請求項２記載の半導体装置。  The semiconductor device according to claim 1, wherein the base substrate is a CSP (Chip Size Package) substrate. 前記半導体チップ、前記第1の放熱板及び前記ベース基板が封止された樹脂を備えることを特徴とする請求項１又は請求項２記載の半導体装置。  3. The semiconductor device according to claim 1, further comprising a resin in which the semiconductor chip, the first heat radiation plate, and the base substrate are sealed. 前記第1の放熱板及び前記第２の放熱板の一方の面は、前記樹脂から露出されていることを特徴とする請求項４記載の半導体装置。  The semiconductor device according to claim 4, wherein one surface of the first heat radiating plate and the second heat radiating plate is exposed from the resin.
JP19351698A 1998-07-09 1998-07-09 Semiconductor device Expired - Fee Related JP3922809B2 (en)

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US6693350B2 (en) 1999-11-24 2004-02-17 Denso Corporation Semiconductor device having radiation structure and method for manufacturing semiconductor device having radiation structure
US6703707B1 (en) 1999-11-24 2004-03-09 Denso Corporation Semiconductor device having radiation structure
JP4479121B2 (en) 2001-04-25 2010-06-09 株式会社デンソー Manufacturing method of semiconductor device
JP3580293B2 (en) * 2002-03-26 2004-10-20 株式会社デンソー Method for manufacturing semiconductor device
US7145254B2 (en) 2001-07-26 2006-12-05 Denso Corporation Transfer-molded power device and method for manufacturing transfer-molded power device
JP4899481B2 (en) * 2006-01-10 2012-03-21 サンケン電気株式会社 Manufacturing method of resin-encapsulated semiconductor device having a heat radiator exposed outside
JP5126278B2 (en) 2010-02-04 2013-01-23 株式会社デンソー Semiconductor device and manufacturing method thereof
JP5454438B2 (en) * 2010-09-27 2014-03-26 株式会社デンソー Semiconductor module
JP6135501B2 (en) * 2013-12-26 2017-05-31 トヨタ自動車株式会社 Semiconductor device
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