JP2007036035A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2007036035A
JP2007036035A JP2005219224A JP2005219224A JP2007036035A JP 2007036035 A JP2007036035 A JP 2007036035A JP 2005219224 A JP2005219224 A JP 2005219224A JP 2005219224 A JP2005219224 A JP 2005219224A JP 2007036035 A JP2007036035 A JP 2007036035A
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semiconductor element
semiconductor device
bonding wire
wiring board
heat
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Toru Suda
亨 須田
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Toshiba Corp
Kioxia Advanced Package Corp
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Toshiba Corp
Toshiba LSI Package Solutions Corp
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Priority to JP2005219224A priority Critical patent/JP2007036035A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

<P>PROBLEM TO BE SOLVED: To provide a structure that efficiently dissipates heat generated from a semiconductor device in a planar direction in a resin-sealed BGA semiconductor device. <P>SOLUTION: The semiconductor device has a wiring substrate 2 on which the semiconductor device 1 is loaded, an annular dissipation plate 3 mounted on the principal surface of the wiring substrate along the periphery at the principal surface of the wiring substrate, a first bonding wire 4 that electrically connects a connection electrode 1a of the semiconductor device and a connection electrode 2a formed on the principal surface of the wiring substrate, a second bonding wire 5 that connects a dummy electrode 1b of the semiconductor device and a radiation plate, and a resin sealant 9 that seals the semiconductor device, at least a part of the radiation plate and the first and the second bonding wires. Heat is dissipated from a mounted substrate via the wiring substrate and a solder ball, after the heat generated by the semiconductor device is transmitted to the bonding wire and spread to the radiation plate. Radiation is more improved than in a conventional technology by efficiently diffusing the heat in the planar direction. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、樹脂封止型ＢＧＡ（Ball Grid Array ）タイプの半導体装置の構造に関するものである。   The present invention relates to the structure of a resin-encapsulated BGA (Ball Grid Array) type semiconductor device.

半導体装置の高消費電力化及び高集積化が進むにつれ動作時の発熱量が大きくなり、半導体装置の内部温度が高くなるようになってきている。これにより半導体素子の誤動作や寿命の低下を招いている。
この問題を解決するための従来技術を説明する。半導体装置は、パッケージ基板もしくはインターポーザ（以下、配線基板という）、パッケージ基板に搭載された半導体チップ及び半導体チップを封止する樹脂封止体から構成されている。配線基板にはプリント基板などが用いられる。 As the power consumption and integration of semiconductor devices increase, the amount of heat generated during operation increases, and the internal temperature of the semiconductor device increases. As a result, malfunction of the semiconductor element and a decrease in the lifetime are caused.
A conventional technique for solving this problem will be described. The semiconductor device includes a package substrate or an interposer (hereinafter referred to as a wiring substrate), a semiconductor chip mounted on the package substrate, and a resin sealing body that seals the semiconductor chip. A printed circuit board etc. are used for a wiring board.

配線基板は、主面及び裏面に接続電極（パッド）が形成されている。主面及び裏面のパッド間は、配線基板内部に埋め込まれた多層配線層（図示しない）を介して適宜電気的に接続されている。従来、配線基板は、半導体装置用プリント基板に放熱用のスルーホールを設けたり、そのスルーホールの直下にはんだボールを搭載している。これにより実装基板への放熱が効果的に行われる。その他には半導体装置に外付けの放熱フィンを搭載したり、強制空冷により冷却している。しかしながら、上記のような、半導体装置用基板にスルーホールを設けたり、放熱用はんだボールを搭載しても熱的な飽和状態となっている。また外付けの放熱フィンを搭載すると、半導体装置の上方に、フィンを搭載するための空間が必要となるが、実装基板を組み込む筐体は一般的に狭いため、そのような空間を空けておくことは難しい。また同様の理由により、雰囲気に強制対流を起こさせることも困難である。
従来技術が開示された特許文献１には、ストリップ又はリール形態のメタルキャリヤフレームにユニットＰＣＢ基板を付着し、メタルキャリヤフレームの一部を半導体パッケージのヒートスプレッダとして構成して半導体パッケージを製造する。ヒートスプレッダは、ＰＣＢ基板の周辺に配置されており、ＢＧＡパッケージの熱放出を容易にすることが記載されている。
特開平１０−８４０５７号公報 The wiring substrate has connection electrodes (pads) formed on the main surface and the back surface. The pads on the main surface and the back surface are appropriately electrically connected via a multilayer wiring layer (not shown) embedded in the wiring board. Conventionally, wiring boards are provided with through holes for heat dissipation in printed circuit boards for semiconductor devices, and solder balls are mounted directly under the through holes. This effectively dissipates heat to the mounting board. In addition, an external radiating fin is mounted on the semiconductor device or cooled by forced air cooling. However, even if a through hole is provided in the substrate for a semiconductor device as described above or a solder ball for heat dissipation is mounted, the semiconductor device is in a thermal saturation state. In addition, when an external radiating fin is mounted, a space for mounting the fin is required above the semiconductor device. However, since a housing for mounting a mounting board is generally narrow, leave such a space. It ’s difficult. For the same reason, it is difficult to cause forced convection in the atmosphere.
In Patent Document 1 in which the prior art is disclosed, a unit PCB substrate is attached to a metal carrier frame in a strip or reel form, and a part of the metal carrier frame is configured as a heat spreader of the semiconductor package to manufacture a semiconductor package. It is described that the heat spreader is arranged around the PCB substrate and facilitates heat release of the BGA package.
JP-A-10-84057

樹脂封止型ＢＧＡ（Ball Grid Array ）タイプの半導体装置において、半導体素子から発生した熱を放散させる、とくに平面方向に熱を効率良く放散させる構造を提供する。   In a resin-encapsulated BGA (Ball Grid Array) type semiconductor device, there is provided a structure that dissipates heat generated from a semiconductor element, particularly efficiently dissipates heat in a planar direction.

本発明の半導体装置の一態様は、主面に内部回路と電気的に接続された複数の接続電極及び前記内部回路とは電気的に接続されていない複数のダミー電極とを備えた半導体素子と、前記半導体素子が搭載された配線基板と、前記配線基板主面の周辺部に沿って前記配線基板主面上に取り付けられた環状の放熱板と、前記半導体素子の接続電極と前記配線基板の主面上に形成された接続電極とを電気的に接続する第１のボンディングワイヤと、前記半導体素子のダミー電極と前記放熱板とを接続する第２のボンディングワイヤと、前記半導体素子、前記配線基板の一部、前記放熱板の少なくとも一部及び前記第１及び第２のボンディングワイヤとを封止する樹脂封止体とを備えたことを特徴としている。   One aspect of the semiconductor device of the present invention includes a semiconductor element including a plurality of connection electrodes electrically connected to an internal circuit on a main surface and a plurality of dummy electrodes not electrically connected to the internal circuit. A wiring board on which the semiconductor element is mounted, an annular heat sink attached to the main surface of the wiring board along a peripheral portion of the main surface of the wiring board, connection electrodes of the semiconductor element, and the wiring board A first bonding wire for electrically connecting the connection electrode formed on the main surface; a second bonding wire for connecting the dummy electrode of the semiconductor element and the heat sink; the semiconductor element; and the wiring. A resin sealing body for sealing a part of the substrate, at least a part of the heat radiating plate, and the first and second bonding wires is provided.

また、本発明の半導体装置の一態様は、表面に内部回路と電気的に接続された複数の接続電極及び前記内部電極とは電気的に接続されていない複数のダミー電極とを備えた半導体素子と、前記半導体素子が搭載されたリードフレームの素子搭載部と、前記素子搭載部を支持する前記リードフレームの吊りピン部に前記半導体素子及び前記素子搭載部を囲むように取り付けられた環状の放熱板と、前記半導体素子の接続電極と前記リードフレームのリードとを電気的に接続する第１のボンディングワイヤと、前記半導体素子のダミー電極と前記放熱板とを接続する第２のボンディングワイヤと、前記半導体素子、前記素子搭載部、前記放熱板の少なくとも一部、前記リードフレームのリードの一部、前記第１のボンディングワイヤ及び第２のボンディングワイヤとを封止する樹脂封止体とを備えたことを特徴としている。   Another embodiment of the semiconductor device of the present invention is a semiconductor element including a plurality of connection electrodes electrically connected to an internal circuit on a surface and a plurality of dummy electrodes not electrically connected to the internal electrodes. An element mounting portion of a lead frame on which the semiconductor element is mounted, and an annular heat dissipation attached to a suspension pin portion of the lead frame that supports the element mounting portion so as to surround the semiconductor element and the element mounting portion A first bonding wire that electrically connects the connection electrode of the semiconductor element and the lead of the lead frame; a second bonding wire that connects the dummy electrode of the semiconductor element and the heat sink; The semiconductor element, the element mounting portion, at least a part of the heat sink, a part of the lead of the lead frame, the first bonding wire, and the second It is characterized by comprising a resin sealing body which seals the loading wire.

本発明は、以上の構成により、半導体素子における発熱がボンディングワイヤを伝って放熱板に広がった後、配線基板とはんだボールを経由して実装基板から放熱されるようになる。従来技術のような半導体素子直下の方向への放熱だけでは熱的に飽和していたが、平面方向にも熱を拡散することによって従来技術よりも放熱性を向上させることができる。   According to the present invention, the heat generated in the semiconductor element spreads to the heat dissipation plate through the bonding wire and then is radiated from the mounting substrate via the wiring substrate and the solder balls. Although heat was saturated only by heat radiation in the direction directly below the semiconductor element as in the prior art, heat dissipation can be improved as compared with the prior art by diffusing heat in the planar direction.

本発明は、樹脂封止型ＢＧＡタイプの構造を有する半導体装置に関するもので、配線基板周辺に設けた放熱板と半導体素子とをボンディングワイヤにより接続することにより、半導体素子の発熱を効率よく平面方向にも放散させることを特徴とする。
以下、実施例を参照して発明の実施の形態を説明する。 The present invention relates to a semiconductor device having a resin-encapsulated BGA type structure. By connecting a heat sink and a semiconductor element provided around a wiring board with a bonding wire, the heat generation of the semiconductor element is efficiently performed in a planar direction. It is also characterized by being dissipated.
Hereinafter, embodiments of the invention will be described with reference to examples.

まず、図１及び図２を参照して実施例１を説明する。
図１は、半導体装置が搭載された実装基板の部分透視平面図、図２は、図１の半導体装置が搭載された実装基板の断面図である。
実装基板１０には、半導体装置が搭載されている。実装基板１０には、主面に銅などからなる接続電極（パッド）１０ａを含む配線パターンが形成されている。半導体装置は、半導体素子（チップ）１と、これが搭載される配線基板２と、配線基板主面に取り付けられた放熱板３とを備えている。半導体素子１は、例えば、シリコン半導体などからなり、主面には複数のアルミニウムなどの接続電極（パッド）１ａ及びアルミニウムなどのダミー電極１ｂが形成されている。接続電極１ａは、半導体素子１に形成された内部回路に電気的に接続され、ダミー電極１ｂは半導体素子１に形成された内部回路とは電気的に接続されていない。配線基板２は、主面に銅などからなる接続電極（パッド）２ａ及び素子搭載部２ｂを含む配線パターンを有しており、裏面に銅などからなる接続電極（パッド）２ｃを含む配線パターンが形成されている。配線基板２の主面及び裏面の配線パターンは、配線基板２に埋め込み形成された銅などからなるビア７により電気的に接続されている。また、配線基板２の裏面に形成された接続電極２ｃには、例えば、はんだボール８のような外部接続端子が接合される。 First, Embodiment 1 will be described with reference to FIGS.
1 is a partially transparent plan view of a mounting substrate on which a semiconductor device is mounted, and FIG. 2 is a cross-sectional view of the mounting substrate on which the semiconductor device of FIG. 1 is mounted.
A semiconductor device is mounted on the mounting substrate 10. A wiring pattern including connection electrodes (pads) 10 a made of copper or the like is formed on the main surface of the mounting substrate 10. The semiconductor device includes a semiconductor element (chip) 1, a wiring board 2 on which the semiconductor element (chip) 1 is mounted, and a heat radiating plate 3 attached to the main surface of the wiring board. The semiconductor element 1 is made of, for example, a silicon semiconductor, and a plurality of connection electrodes (pads) 1a such as aluminum and a dummy electrode 1b such as aluminum are formed on the main surface. The connection electrode 1 a is electrically connected to the internal circuit formed in the semiconductor element 1, and the dummy electrode 1 b is not electrically connected to the internal circuit formed in the semiconductor element 1. The wiring substrate 2 has a wiring pattern including a connection electrode (pad) 2a made of copper or the like on the main surface and an element mounting portion 2b, and a wiring pattern containing a connection electrode (pad) 2c made of copper or the like on the back surface. Is formed. The wiring patterns on the main surface and the back surface of the wiring board 2 are electrically connected by vias 7 made of copper or the like embedded in the wiring board 2. Further, an external connection terminal such as a solder ball 8 is bonded to the connection electrode 2 c formed on the back surface of the wiring board 2.

配線基板２主面には半導体素子１及び放熱板３が搭載されている。半導体素子１は、配線パターンの素子搭載部２ｂ上にエポキシ樹脂などの接着剤（ダイアタッチ材）６により接合されている。また、配線基板２上には半導体素子１を囲むように環状の放熱板３が配線基板２の周辺部に沿って配置されている。放熱板３は、銅、銅合金、アルミニウム、シリコンを含むアルミニウム合金、高熱伝導セラミックなどの高熱伝導材料を用いる。
半導体素子１と外部接続端子であるはんだボール８とは第１のボンディングワイヤ４により電気的に接続される。第１のボンディングワイヤ４は、配線基板２主面の接続電極２ａ及び半導体素子１主面の接続電極１ａにボンディングされる。半導体素子１から発生した熱の放熱経路は、第２のボンディングワイヤ５により構成される。第２のボンディングワイヤ５は、放熱板３上面の任意の位置と半導体素子１のダミー電極１ｂとに接続される。勿論、第２のボンディングワイヤは、放熱特性を損ねなければ、ダミー電極に接続せず、半導体素子１主面の電極部分以外の部分に接続することができる。また、ボンディングワイヤは、２０〜３０μｍ径の金を材料としている。放熱性を高めるために、第２のボンディングワイヤは太いほど良い（例えば、５０μｍ径のワイヤを用いることができる）が、第１及び第２のボンディングワイヤを同じ太さの金ワイヤを用いれば、ボンディング工程を１回にすることができ、工程を短縮させることができる。 A semiconductor element 1 and a heat sink 3 are mounted on the main surface of the wiring board 2. The semiconductor element 1 is bonded onto the element mounting portion 2b of the wiring pattern by an adhesive (die attach material) 6 such as an epoxy resin. An annular heat sink 3 is arranged on the wiring board 2 along the peripheral portion of the wiring board 2 so as to surround the semiconductor element 1. The heat radiating plate 3 uses a high heat conductive material such as copper, a copper alloy, aluminum, an aluminum alloy containing silicon, or a high heat conductive ceramic.
The semiconductor element 1 and the solder ball 8 that is an external connection terminal are electrically connected by the first bonding wire 4. The first bonding wire 4 is bonded to the connection electrode 2 a on the main surface of the wiring board 2 and the connection electrode 1 a on the main surface of the semiconductor element 1. A heat dissipation path for heat generated from the semiconductor element 1 is constituted by the second bonding wires 5. The second bonding wire 5 is connected to an arbitrary position on the upper surface of the heat sink 3 and the dummy electrode 1 b of the semiconductor element 1. Of course, the second bonding wire can be connected to a portion other than the electrode portion of the main surface of the semiconductor element 1 without being connected to the dummy electrode as long as the heat dissipation characteristics are not impaired. The bonding wire is made of gold having a diameter of 20 to 30 μm. In order to improve heat dissipation, the second bonding wire is preferably as thick as possible (for example, a wire having a diameter of 50 μm can be used). If gold wires having the same thickness are used for the first and second bonding wires, The bonding process can be performed once, and the process can be shortened.

配線基板２上に形成された半導体素子１、放熱板３、第１のボンディングワイヤ４及び第２のボンディングワイヤ５は、例えば、トランスファモールド法などにより、樹脂封止体９に封止される。実装基板１０は、複数の接続電極１０ａに各はんだボール８を接合させて、半導体装置を主面に搭載している。
以上のように構成されることによって半導体素子で生じた熱は、高熱伝導材料である金のボンディングワイヤから放熱板に伝わり、平面方向に熱を拡散することが効率良くできる。 The semiconductor element 1, the heat radiating plate 3, the first bonding wire 4 and the second bonding wire 5 formed on the wiring board 2 are sealed in the resin sealing body 9 by, for example, a transfer molding method. The mounting substrate 10 has a semiconductor device mounted on the main surface by bonding each solder ball 8 to a plurality of connection electrodes 10a.
With the configuration described above, heat generated in the semiconductor element is transferred from the gold bonding wire, which is a high thermal conductivity material, to the heat radiating plate, and the heat can be efficiently diffused in the plane direction.

次に、図３及び図４を参照して実施例２を説明する。
図３は、リードフレームを用いた半導体装置の樹脂封止体部分を透視した平面図、図４は、図３のＡ−Ａ′線に沿う部分の断面図である。図３は、リードフレームを用いた半導体装置である。この半導体装置は、次のような構造を有している。ＣｕやＦｅ−４２Ｎｉなどを材料とするリードフレーム２２上にエポキシ樹脂などを材料とする絶縁性の接着剤（ダイアタッチ材）２６を用いて固定されたシリコンなどの半導体基板に形成した半導体素子２１が搭載されている。リードフレーム２２は、素子搭載部２２ａ、リード２２ｂ及び素子搭載部２２ａを支持する吊りピン部２２ｃを備えている。半導体素子２１の裏面は、前記ダイアタッチ材２６を介して素子搭載部２２ａ表面に接合されている。また、半導体素子２１表面には、アルミニウムなどからなる複数の接続電極２１ａ及びダミー電極２１ｂが設けられている。半導体素子２１表面に形成された接続電極２１ａとリード２２ｂの素子搭載部２２ａと対向する先端部とは金などから構成された第１のボンディングワイヤ２４により接続されて半導体素子２１とリードフレーム２２とが電気的に接続されている。リードフレーム２２のリード２２ｂ及び吊りピン部２２ｃに環状の放熱板２３がエポキシ樹脂などを材料とする絶縁性接着剤２７により接合されている。 Next, Embodiment 2 will be described with reference to FIGS.
FIG. 3 is a plan view of a semiconductor device using a lead frame as seen through a resin sealing body portion, and FIG. 4 is a cross-sectional view taken along the line AA ′ of FIG. FIG. 3 shows a semiconductor device using a lead frame. This semiconductor device has the following structure. Semiconductor element 21 formed on a semiconductor substrate such as silicon fixed on lead frame 22 made of Cu, Fe-42Ni or the like using an insulating adhesive (die attach material) 26 made of epoxy resin or the like. Is installed. The lead frame 22 includes an element mounting portion 22a, a lead 22b, and a suspension pin portion 22c that supports the element mounting portion 22a. The back surface of the semiconductor element 21 is bonded to the surface of the element mounting portion 22a via the die attach material 26. A plurality of connection electrodes 21 a and dummy electrodes 21 b made of aluminum or the like are provided on the surface of the semiconductor element 21. The connection electrode 21a formed on the surface of the semiconductor element 21 and the tip of the lead 22b facing the element mounting portion 22a are connected by a first bonding wire 24 made of gold or the like, and the semiconductor element 21 and the lead frame 22 are connected. Are electrically connected. An annular heat sink 23 is joined to the lead 22b and the suspension pin portion 22c of the lead frame 22 by an insulating adhesive 27 made of an epoxy resin or the like.

第１のボンディングワイヤ２４が半導体素子２１の接続電極２１ａとリードフレーム２２のリード２２ｂとにボンディングされる。半導体素子２１から発生した熱の放熱経路は、第２のボンディングワイヤ２５により構成される。第２のボンディングワイヤ２５は、放熱板２３上面の任意の位置と半導体素子２１のダミー電極２１ｂとに接続される。勿論、第２のボンディングワイヤは、放熱特性を損ねなければ、ダミー電極に接続せず、半導体素子１主面の電極部分以外の部分に接続することができる。ボンディングワイヤは、２０〜３０μｍ径の金を材料としている。放熱性を高めるために、第２のボンディングワイヤは太いほど良いが、第１及び第２のボンディングワイヤを同じ太さの金ワイヤとすれば、ボンディング工程を１回にすることができ、工程を短縮させることができる。   The first bonding wire 24 is bonded to the connection electrode 21 a of the semiconductor element 21 and the lead 22 b of the lead frame 22. A heat dissipation path for heat generated from the semiconductor element 21 is configured by the second bonding wire 25. The second bonding wire 25 is connected to an arbitrary position on the upper surface of the heat sink 23 and the dummy electrode 21 b of the semiconductor element 21. Of course, the second bonding wire can be connected to a portion other than the electrode portion of the main surface of the semiconductor element 1 without being connected to the dummy electrode as long as the heat dissipation characteristics are not impaired. The bonding wire is made of gold having a diameter of 20 to 30 μm. In order to enhance heat dissipation, the thicker the second bonding wire, the better. However, if the first and second bonding wires are gold wires having the same thickness, the bonding process can be performed once, It can be shortened.

半導体素子２１、素子搭載部２２ａ、リード２２ｂの一部、吊りピン部２２ｃの一部、第１及び第２のボンディングワイヤ２４、２５等は、エポキシ樹脂等を材料とする樹脂封止体２９により封止されている。放熱板２３は、銅、銅合金、アルミニウム、シリコンを含むアルミニウム合金、高熱伝導セラミックなどの高熱伝導材料を用いる。
以上のように構成されることによって半導体素子で生じた熱は、高熱伝導材料である金のボンディングワイヤから放熱板に伝わり、平面方向に熱を拡散することが効率良くできる。 The semiconductor element 21, the element mounting portion 22a, a part of the lead 22b, a part of the suspension pin part 22c, the first and second bonding wires 24, 25, and the like are formed by a resin sealing body 29 made of an epoxy resin or the like. It is sealed. The heat sink 23 uses a high heat conductive material such as copper, copper alloy, aluminum, an aluminum alloy containing silicon, or a high heat conductive ceramic.
With the configuration described above, heat generated in the semiconductor element is transferred from the gold bonding wire, which is a high thermal conductivity material, to the heat radiating plate, and the heat can be efficiently diffused in the plane direction.

まず、図５を参照して実施例３を説明する。
図５は、半導体装置が搭載された実装基板の部分透視断面図である。
実装基板３０には、半導体装置が搭載され、主面に銅などの接続電極３０ａを含む配線パターンが形成されている。半導体装置は、半導体素子３１と、これが搭載された配線基板３２と、配線基板３２主面上の放熱板３３とを備えている。半導体素子３１は、主面に複数の接続電極３１ａ及びダミー電極３１ｂが形成されている。接続電極３１ａは、半導体素子３１に形成された内部回路に電気的に接続され、ダミー電極３１ｂは、この内部回路とは電気的に接続されていない。配線基板３２は、主面に接続電極３２ａ及び素子搭載部３２ｂを含む配線パターンを有し、裏面に接続電極３２ｃを含む配線パターンが形成されている。配線基板３２両面の配線パターンは、配線基板３２に埋め込まれたビア３７により電気的に接続されている。また、配線基板３２の裏面に形成された接続電極３２ｃには、はんだボール３８のような外部接続端子が接合されている。 First, Embodiment 3 will be described with reference to FIG.
FIG. 5 is a partially transparent sectional view of a mounting substrate on which a semiconductor device is mounted.
A semiconductor device is mounted on the mounting substrate 30, and a wiring pattern including connection electrodes 30 a such as copper is formed on the main surface. The semiconductor device includes a semiconductor element 31, a wiring board 32 on which the semiconductor element 31 is mounted, and a heat dissipation plate 33 on the main surface of the wiring board 32. The semiconductor element 31 has a plurality of connection electrodes 31a and dummy electrodes 31b formed on the main surface. The connection electrode 31a is electrically connected to an internal circuit formed in the semiconductor element 31, and the dummy electrode 31b is not electrically connected to the internal circuit. The wiring board 32 has a wiring pattern including the connection electrode 32a and the element mounting portion 32b on the main surface, and a wiring pattern including the connection electrode 32c is formed on the back surface. The wiring patterns on both surfaces of the wiring board 32 are electrically connected by vias 37 embedded in the wiring board 32. An external connection terminal such as a solder ball 38 is joined to the connection electrode 32 c formed on the back surface of the wiring board 32.

配線基板３２主面には半導体素子３１及び放熱板３３が搭載されている。半導体素子３１は、素子搭載部３２ｂ上に接着剤（ダイアタッチ材）３６により接合されている。また、配線基板３２上には半導体素子３１を囲むように環状の放熱板３３が配線基板３２の周辺部に沿って配置されている。
半導体素子３１と外部接続端子であるはんだボール３８とは第１のボンディングワイヤ３４により電気的に接続される。第１のボンディングワイヤ３４は、配線基板３２主面の接続電極３２ａ及び半導体素子３１主面の接続電極３１ａにボンディングされる。半導体素子３１から発生した熱の放熱経路は、第２のボンディングワイヤ３５により構成される。第２のボンディングワイヤ３５は、放熱板３３上面の任意の位置と半導体素子３１のダミー電極３１ｂとに接続される。配線基板３２に搭載された半導体素子３１、放熱板３３の一部、第１のボンディングワイヤ３４及び第２のボンディングワイヤ３５は、樹脂封止体３９により封止される。放熱板３３は、外周側面が樹脂封止体３９から露出している。実装基板３０は、複数の接続電極３０ａに各はんだボール３８を接合させて、半導体装置を主面に搭載している。 A semiconductor element 31 and a heat sink 33 are mounted on the main surface of the wiring board 32. The semiconductor element 31 is bonded to the element mounting portion 32b by an adhesive (die attach material) 36. An annular heat sink 33 is disposed on the wiring board 32 along the periphery of the wiring board 32 so as to surround the semiconductor element 31.
The semiconductor element 31 and the solder ball 38 which is an external connection terminal are electrically connected by a first bonding wire 34. The first bonding wire 34 is bonded to the connection electrode 32 a on the main surface of the wiring substrate 32 and the connection electrode 31 a on the main surface of the semiconductor element 31. A heat dissipation path for heat generated from the semiconductor element 31 is configured by the second bonding wire 35. The second bonding wire 35 is connected to an arbitrary position on the upper surface of the heat radiating plate 33 and the dummy electrode 31 b of the semiconductor element 31. The semiconductor element 31 mounted on the wiring substrate 32, a part of the heat dissipation plate 33, the first bonding wire 34 and the second bonding wire 35 are sealed with a resin sealing body 39. The heat radiating plate 33 has an outer peripheral side surface exposed from the resin sealing body 39. The mounting substrate 30 has the semiconductor device mounted on the main surface by bonding the solder balls 38 to the plurality of connection electrodes 30a.

以上のように構成されることによって半導体素子で生じた熱は、高熱伝導材料である金のボンディングワイヤから放熱板に伝わり、平面方向に熱を拡散することが効率良くできる。また、この実施例では放熱板は、半導体装置の樹脂封止体外形寸法と同等またはそれ以上の大きさである。そのため樹脂封止体は、放熱板の環状体の上に成型されることになる（図５参照）。そのため放熱板の側面が雰囲気に露出されるので放熱効果が上昇する。   With the configuration described above, heat generated in the semiconductor element is transferred from the gold bonding wire, which is a high thermal conductivity material, to the heat radiating plate, and the heat can be efficiently diffused in the plane direction. In this embodiment, the heat radiating plate is equal to or larger than the outer dimension of the resin sealing body of the semiconductor device. Therefore, the resin sealing body is molded on the annular body of the heat sink (see FIG. 5). Therefore, since the side surface of the heat sink is exposed to the atmosphere, the heat dissipation effect is increased.

まず、図６を参照して実施例４を説明する。
図６は、半導体装置が搭載された実装基板の部分透視断面図である。
実装基板４０には、半導体装置が搭載され、主面に接続電極４０ａを含む配線パターンが形成されている。半導体装置は、半導体素子４１と、これが搭載された配線基板４２と、配線基板４２主面上の放熱板４３とを備えている。半導体素子４１は、主面に複数の接続電極４１ａ及びダミー電極４１ｂが形成されている。接続電極４１ａは、半導体素子４１に形成された内部回路に電気的に接続され、ダミー電極４１ｂは、この内部回路とは電気的に接続されていない。配線基板４２は、主面に接続電極４２ａ及び素子搭載部４２ｂを含む配線パターンを有し、裏面に接続電極４２ｃを含む配線パターンが形成されている。配線基板４２の主面及び裏面の配線パターンは、配線基板４２に埋め込まれたビア４７により電気的に接続されている。また、配線基板４２の裏面に形成された接続電極４２ｃには、はんだボール４８のような外部接続端子が接合されている。 First, Embodiment 4 will be described with reference to FIG.
FIG. 6 is a partially transparent sectional view of a mounting substrate on which a semiconductor device is mounted.
A semiconductor device is mounted on the mounting substrate 40, and a wiring pattern including the connection electrode 40a is formed on the main surface. The semiconductor device includes a semiconductor element 41, a wiring board 42 on which the semiconductor element 41 is mounted, and a heat dissipation plate 43 on the main surface of the wiring board 42. The semiconductor element 41 has a plurality of connection electrodes 41a and dummy electrodes 41b formed on the main surface. The connection electrode 41a is electrically connected to an internal circuit formed in the semiconductor element 41, and the dummy electrode 41b is not electrically connected to the internal circuit. The wiring substrate 42 has a wiring pattern including the connection electrode 42a and the element mounting portion 42b on the main surface, and a wiring pattern including the connection electrode 42c is formed on the back surface. The wiring patterns on the main surface and the back surface of the wiring substrate 42 are electrically connected by vias 47 embedded in the wiring substrate 42. An external connection terminal such as a solder ball 48 is bonded to the connection electrode 42 c formed on the back surface of the wiring board 42.

配線基板４２主面には半導体素子４１及び放熱板４３が搭載されている。半導体素子４１は、素子搭載部４２ｂ上に接着剤（ダイアタッチ材）４６により接合されている。また、配線基板４２上には半導体素子４１を囲むように環状の放熱板４３が配線基板４２の周辺部に沿って配置されている。
半導体素子４１と外部接続端子であるはんだボール４８とは第１のボンディングワイヤ４４により電気的に接続される。第１のボンディングワイヤ４４は、配線基板４２主面の接続電極４２ａ及び半導体素子４１主面の接続電極４１ａにボンディングされる。半導体素子４１から発生した熱の放熱経路は、第２のボンディングワイヤ４５により構成される。第２のボンディングワイヤ４５は、放熱板４３上面の任意の位置と半導体素子４１のダミー電極４１ｂとに接続される。配線基板４２に搭載された半導体素子４１、放熱板４３の一部、第１のボンディングワイヤ４４及び第２のボンディングワイヤ４５は、樹脂封止体４９により封止される。放熱板４３は、外周側面及び上面の外周部分が樹脂封止体４９から露出している。実装基板４０は、複数の接続電極４０ａに各はんだボール４８を接合させて、半導体装置を主面に搭載している。 A semiconductor element 41 and a heat sink 43 are mounted on the main surface of the wiring board 42. The semiconductor element 41 is bonded to the element mounting portion 42b by an adhesive (die attach material) 46. An annular heat sink 43 is disposed on the wiring board 42 along the periphery of the wiring board 42 so as to surround the semiconductor element 41.
The semiconductor element 41 and the solder ball 48 which is an external connection terminal are electrically connected by a first bonding wire 44. The first bonding wire 44 is bonded to the connection electrode 42 a on the main surface of the wiring board 42 and the connection electrode 41 a on the main surface of the semiconductor element 41. A heat dissipation path for heat generated from the semiconductor element 41 is configured by the second bonding wire 45. The second bonding wire 45 is connected to an arbitrary position on the upper surface of the heat sink 43 and the dummy electrode 41 b of the semiconductor element 41. The semiconductor element 41 mounted on the wiring substrate 42, a part of the heat radiating plate 43, the first bonding wire 44 and the second bonding wire 45 are sealed with a resin sealing body 49. As for the heat sink 43, the outer peripheral side and the outer peripheral part of the upper surface are exposed from the resin sealing body 49. The mounting substrate 40 has the semiconductor device mounted on the main surface by bonding the solder balls 48 to the plurality of connection electrodes 40a.

以上のように構成されることによって半導体素子で生じた熱は、高熱伝導材料である金のボンディングワイヤから放熱板に伝わり、平面方向に熱を拡散することが効率良くできる。また、この実施例では放熱板は、半導体装置の樹脂封止体外形寸法以上の大きさである。そのために樹脂封止体は、実施例３と同様に放熱板の環状体の上に成型されることになる。すなわち、樹脂封止体エリアを実施例３よりさらに狭くすると放熱板の環状体上面が雰囲気中に露出される（図６参照）ため放熱効果が上昇する。さらに、露出した環状体表面には外付けのヒートシンクや放熱フィン、筐体などを接続することによりさらに放熱効果を上げることが可能となる。   With the configuration described above, heat generated in the semiconductor element is transferred from the gold bonding wire, which is a high thermal conductivity material, to the heat radiating plate, and the heat can be efficiently diffused in the plane direction. Further, in this embodiment, the heat radiating plate is larger than the outer dimension of the resin sealing body of the semiconductor device. Therefore, the resin sealing body is molded on the annular body of the heat sink as in the third embodiment. That is, if the resin sealing body area is made narrower than that of the third embodiment, the upper surface of the annular body of the heat radiating plate is exposed to the atmosphere (see FIG. 6), so that the heat radiation effect is increased. Furthermore, by connecting an external heat sink, heat radiating fin, housing, etc. to the exposed annular body surface, it is possible to further increase the heat radiating effect.

まず、図７を参照して実施例５を説明する。
図７は、半導体装置が搭載された実装基板の部分透視断面図である。
実装基板５０には、半導体装置が搭載され、主面に接続電極５０ａを含む配線パターンが形成されている。半導体装置は、半導体素子５１と、これが搭載された配線基板５２と、配線基板５２主面上の放熱板５３とを備えている。
半導体素子５１は、主面に複数の接続電極５１ａ及びダミー電極５１ｂが形成されている。接続電極５１ａは、半導体素子５１に形成された内部回路に電気的に接続され、ダミー電極５１ｂは、この内部回路とは電気的に接続されていない。配線基板５２は、主面に接続電極５２ａ及び素子搭載部５２ｂを含む配線パターンを有し、裏面に接続電極５２ｃを含む配線パターンが形成されている。配線基板５２両面の配線パターンは、配線基板５２に埋め込まれたビア５７により電気的に接続されている。また、配線基板５２の裏面に形成された接続電極５２ｃには、はんだボール５８のような外部接続端子が接合されている。 First, Embodiment 5 will be described with reference to FIG.
FIG. 7 is a partially transparent sectional view of a mounting substrate on which a semiconductor device is mounted.
A semiconductor device is mounted on the mounting substrate 50, and a wiring pattern including the connection electrode 50a is formed on the main surface. The semiconductor device includes a semiconductor element 51, a wiring board 52 on which the semiconductor element 51 is mounted, and a heat dissipation plate 53 on the main surface of the wiring board 52.
The semiconductor element 51 has a plurality of connection electrodes 51a and dummy electrodes 51b formed on the main surface. The connection electrode 51a is electrically connected to an internal circuit formed in the semiconductor element 51, and the dummy electrode 51b is not electrically connected to this internal circuit. The wiring substrate 52 has a wiring pattern including the connection electrode 52a and the element mounting portion 52b on the main surface, and a wiring pattern including the connection electrode 52c is formed on the back surface. The wiring patterns on both surfaces of the wiring board 52 are electrically connected by vias 57 embedded in the wiring board 52. An external connection terminal such as a solder ball 58 is joined to the connection electrode 52 c formed on the back surface of the wiring board 52.

配線基板５２主面には半導体素子５１及び放熱板５３が搭載されている。半導体素子５１は、素子搭載部５２ｂ上に接着剤（ダイアタッチ材）５６により接合されている。また、配線基板５２上には半導体素子５１を囲むように環状の放熱板５３が配線基板５２の周辺部に沿って配置されている。
半導体素子５１と外部接続端子であるはんだボール５８とは第１のボンディングワイヤ５４により電気的に接続される。第１のボンディングワイヤ５４は、配線基板５２主面の接続電極５２ａ及び半導体素子５１主面の接続電極５１ａにボンディングされる。半導体素子５１から発生した熱の放熱経路は、第２のボンディングワイヤ５５により構成される。第２のボンディングワイヤ５５は、放熱板５３上面の任意の位置と半導体素子５１のダミー電極５１ｂとに接続される。配線基板５２に搭載された半導体素子５１、放熱板５３の一部、第１のボンディングワイヤ５４及び第２のボンディングワイヤ５５は、樹脂封止体５９により封止される。放熱板５３は、外周側面及び上面の外周部分が樹脂封止体５９から露出している。放熱板５３の樹脂封止体５９から露出している上面には凹凸加工５３ａが施されている。実装基板５０は、複数の接続電極５０ａに各はんだボール５８を接合させて、半導体装置を主面に搭載している。 A semiconductor element 51 and a heat sink 53 are mounted on the main surface of the wiring board 52. The semiconductor element 51 is bonded to the element mounting portion 52b by an adhesive (die attach material) 56. An annular heat sink 53 is disposed on the wiring board 52 along the periphery of the wiring board 52 so as to surround the semiconductor element 51.
The semiconductor element 51 and the solder ball 58 which is an external connection terminal are electrically connected by a first bonding wire 54. The first bonding wire 54 is bonded to the connection electrode 52 a on the main surface of the wiring substrate 52 and the connection electrode 51 a on the main surface of the semiconductor element 51. A heat dissipation path for heat generated from the semiconductor element 51 is configured by the second bonding wire 55. The second bonding wire 55 is connected to an arbitrary position on the upper surface of the heat dissipation plate 53 and the dummy electrode 51 b of the semiconductor element 51. The semiconductor element 51 mounted on the wiring substrate 52, a part of the heat dissipation plate 53, the first bonding wire 54 and the second bonding wire 55 are sealed with a resin sealing body 59. As for the heat sink 53, the outer peripheral side and the outer peripheral part of the upper surface are exposed from the resin sealing body 59. An uneven surface 53a is provided on the upper surface of the heat radiating plate 53 exposed from the resin sealing body 59. The mounting substrate 50 has the semiconductor device mounted on the main surface by bonding the solder balls 58 to the plurality of connection electrodes 50a.

以上のように構成されることによって半導体素子で生じた熱は、高熱伝導材料である金のボンディングワイヤから放熱板に伝わり、平面方向に熱を拡散することが効率良くできる。また、この実施例では放熱板は、半導体装置の樹脂封止体外形寸法以上の大きさである。そのために樹脂封止体は、実施例３、４と同様に放熱板の環状体の上に成型されることになる。すなわち、樹脂封止体エリアを放熱板よりさらに狭くすると放熱板の環状体上面の一部が雰囲気中に露出され、そこに形成された凹凸加工が放熱フィンとしての機能を果たす（図７参照）ために放熱効果が上昇する。   With the configuration described above, heat generated in the semiconductor element is transferred from the gold bonding wire, which is a high thermal conductivity material, to the heat radiating plate, and the heat can be efficiently diffused in the plane direction. Further, in this embodiment, the heat radiating plate is larger than the outer dimension of the resin sealing body of the semiconductor device. Therefore, the resin sealing body is molded on the annular body of the heat sink similarly to the third and fourth embodiments. That is, when the resin sealing body area is made narrower than the heat sink, a part of the upper surface of the annular body of the heat sink is exposed to the atmosphere, and the uneven processing formed therein functions as a heat sink (see FIG. 7). Therefore, the heat dissipation effect increases.

本発明の一実施例である実施例１に係る半導体装置が搭載された実装基板の部分透視平面図。1 is a partial perspective plan view of a mounting board on which a semiconductor device according to a first embodiment which is an embodiment of the present invention is mounted. 図１の半導体装置が搭載された実装基板の断面図。FIG. 2 is a cross-sectional view of a mounting substrate on which the semiconductor device of FIG. 1 is mounted. 本発明の一実施例である実施例２に係るリードフレームを用いた半導体装置の樹脂封止体部分を透視した平面図。The top view which saw through the resin sealing body part of the semiconductor device using the lead frame which concerns on Example 2 which is one Example of this invention. 図３のＡ−Ａ′線に沿う部分の断面図。Sectional drawing of the part which follows the AA 'line of FIG. 本発明の一実施例である実施例３に係る半導体装置が搭載された実装基板の部分透視断面図。FIG. 10 is a partial perspective cross-sectional view of a mounting board on which a semiconductor device according to a third embodiment which is an embodiment of the present invention is mounted. 本発明の一実施例である実施例４に係る半導体装置が搭載された実装基板の部分透視断面図。FIG. 10 is a partial perspective cross-sectional view of a mounting board on which a semiconductor device according to a fourth embodiment which is an embodiment of the present invention is mounted. 本発明の一実施例である実施例５に係る半導体装置が搭載された実装基板の部分透視断面図。FIG. 10 is a partial perspective cross-sectional view of a mounting board on which a semiconductor device according to a fifth embodiment which is an embodiment of the present invention is mounted.

符号の説明Explanation of symbols

１、２１、３１、４１、５１・・・半導体素子（チップ）
１ａ、２１ａ、３１ａ、４１ａ、５１ａ・・・半導体素子の接続電極
１ｂ、２１ｂ、３１ｂ、４１ｂ、５１ｂ・・・半導体素子のダミー電極
２、３２、４２、５２・・・配線基板
２ａ、２ｃ、３２ａ、３２ｃ、４２ａ、４２ｃ、５２ａ、５２ｃ・・・配線基板の接続電極
２ｂ、３２ｂ、４２ｂ、５２ｂ・・・配線基板の素子搭載部
３、２３、３３、４３、５３・・・放熱板
４、２４、３４、４４、５４・・・第１のボンディングワイヤ
５、２５、３５、４５、５５・・・第２のボンディングワイヤ
６、２６、２７、３６、４６、５６・・・接着剤（ダイアタッチ材）
７、３７、４７、５７・・・ビア
８、３８、４８、５８・・・はんだボール
９、２９、３９、４９、５９・・・樹脂封止体
１０、３０、４０、５０・・・実装基板
１０ａ、３０ａ、４０ａ、５０ａ・・・実装基板の接続電極
２２・・・リードフレーム
２２ａ・・・リードフレームの素子搭載部
２２ｂ・・・リードフレームのリード
２２ｃ・・・リードフレームのつりピン部

1, 21, 31, 41, 51... Semiconductor element (chip)
1a, 21a, 31a, 41a, 51a ... Semiconductor device connection electrodes 1b, 21b, 31b, 41b, 51b ... Semiconductor device dummy electrodes 2, 32, 42, 52 ... Wiring substrates 2a, 2c, 32a, 32c, 42a, 42c, 52a, 52c... Connection electrode of wiring board 2b, 32b, 42b, 52b... Element mounting portion of wiring board 3, 23, 33, 43, 53. 24, 34, 44, 54 ... first bonding wire 5, 25, 35, 45, 55 ... second bonding wire 6, 26, 27, 36, 46, 56 ... adhesive ( Die attach material)
7, 37, 47, 57 ... Via 8, 38, 48, 58 ... Solder ball 9, 29, 39, 49, 59 ... Resin encapsulant 10, 30, 40, 50 ... Mounting Substrate 10a, 30a, 40a, 50a ... Connecting electrode on mounting board 22 ... Lead frame 22a ... Lead frame element mounting part 22b ... Lead frame lead 22c ... Lead frame suspension pin part

Claims (5)

主面に内部回路と電気的に接続された複数の接続電極及び前記内部回路とは電気的に接続されていない複数のダミー電極とを備えた半導体素子と、
前記半導体素子が搭載された配線基板と、
前記配線基板主面の周辺部に沿って前記配線基板主面上に取り付けられた環状の放熱板と、
前記半導体素子の接続電極と前記配線基板上に形成された接続電極とを電気的に接続する第１のボンディングワイヤと、
前記半導体素子のダミー電極と前記放熱板とを接続する第２のボンディングワイヤと、
前記半導体素子、前記配線基板の一部、前記放熱板の少なくとも一部及び前記第１及び第２のボンディングワイヤとを封止する樹脂封止体とを備えたことを特徴とする半導体装置。 A semiconductor element comprising a plurality of connection electrodes electrically connected to an internal circuit on a main surface and a plurality of dummy electrodes not electrically connected to the internal circuit;
A wiring board on which the semiconductor element is mounted;
An annular heat sink attached on the main surface of the wiring board along the periphery of the main surface of the wiring board;
A first bonding wire for electrically connecting the connection electrode of the semiconductor element and the connection electrode formed on the wiring board;
A second bonding wire connecting the dummy electrode of the semiconductor element and the heat sink;
A semiconductor device comprising: the semiconductor element; a part of the wiring substrate; at least a part of the heat dissipation plate; and a resin sealing body that seals the first and second bonding wires. 前記配線基板上に取り付けられた前記放熱板は、前記樹脂封止体によって露出部分が被覆されていることを特徴とする請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein an exposed portion of the heat radiating plate attached on the wiring board is covered with the resin sealing body. 前記配線基板上に取り付けられた前記放熱板は、前記樹脂封止体によって一部被覆されており、被覆されずに前記樹脂封止体から露出している部分には、表面に凹凸が形成されていることを特徴とする請求項１に記載の半導体装置。 The heat radiating plate attached on the wiring board is partially covered with the resin sealing body, and unevenness is formed on the surface of a portion exposed from the resin sealing body without being covered. The semiconductor device according to claim 1, wherein: 前記第１のボンディングワイヤと第２のボンディングワイヤとは、形状及び材料が同じであることを特徴とする請求項１乃至請求項３のいづれかに記載の半導体装置。 4. The semiconductor device according to claim 1, wherein the first bonding wire and the second bonding wire have the same shape and material. 表面に内部回路と電気的に接続された複数の接続電極及び前記内部電極とは電気的に接続されていない複数のダミー電極とを備えた半導体素子と、
前記半導体素子が搭載されたリードフレームの素子搭載部と、
前記素子搭載部を支持する前記リードフレームの吊りピン部に前記半導体素子及び前記素子搭載部を囲むように取り付けられた環状の放熱板と、
前記半導体素子の接続電極と前記リードフレームのリードとを電気的に接続する第１のボンディングワイヤと、
前記半導体素子のダミー電極と前記放熱板とを接続する第２のボンディングワイヤと、
前記半導体素子、前記素子搭載部、前記放熱板の少なくとも一部、前記リードフレームのリードの一部、前記第１のボンディングワイヤ及び第２のボンディングワイヤとを封止する樹脂封止体とを備えたことを特徴とする半導体装置。


A semiconductor element comprising a plurality of connection electrodes electrically connected to an internal circuit on the surface and a plurality of dummy electrodes not electrically connected to the internal electrodes;
An element mounting portion of a lead frame on which the semiconductor element is mounted;
An annular heat sink attached to the suspension pin portion of the lead frame that supports the element mounting portion so as to surround the semiconductor element and the element mounting portion;
A first bonding wire for electrically connecting the connection electrode of the semiconductor element and the lead of the lead frame;
A second bonding wire connecting the dummy electrode of the semiconductor element and the heat sink;
A resin sealing body for sealing the semiconductor element, the element mounting portion, at least a part of the heat dissipation plate, a part of the lead of the lead frame, and the first bonding wire and the second bonding wire; A semiconductor device characterized by the above.


JP2005219224A 2005-07-28 2005-07-28 Semiconductor device Pending JP2007036035A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8115290B2 (en) 2008-02-29 2012-02-14 Kabushiki Kaisha Toshiba Storage medium and semiconductor package
JPWO2013057861A1 (en) * 2011-10-20 2015-04-02 パナソニック株式会社 Semiconductor device
US9093393B2 (en) 2012-11-19 2015-07-28 J-Devices Corporation Semiconductor device and method for producing the same
KR20220001676A (en) * 2020-06-30 2022-01-06 하나 마이크로일렉트로닉스 퍼블릭 씨오.,엘티디. Current power module package with dual side cooling without spacer with wire bonding

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8115290B2 (en) 2008-02-29 2012-02-14 Kabushiki Kaisha Toshiba Storage medium and semiconductor package
USRE48110E1 (en) 2008-02-29 2020-07-21 Toshiba Memory Corporation Storage medium and semiconductor package
USRE49332E1 (en) 2008-02-29 2022-12-13 Kioxia Corporation Storage medium and semiconductor package
JPWO2013057861A1 (en) * 2011-10-20 2015-04-02 パナソニック株式会社 Semiconductor device
US9093393B2 (en) 2012-11-19 2015-07-28 J-Devices Corporation Semiconductor device and method for producing the same
KR20220001676A (en) * 2020-06-30 2022-01-06 하나 마이크로일렉트로닉스 퍼블릭 씨오.,엘티디. Current power module package with dual side cooling without spacer with wire bonding
KR102484544B1 (en) * 2020-06-30 2023-01-04 파워마스터반도체 주식회사 Current power module package with dual side cooling without spacer with wire bonding

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