TWI710032B - Package stack structure and manufacturing method thereof and package structure - Google Patents

Abstract

This invention provides a package stack structure and manufacturing method thereof, wherein firstly a circuit structure with a carrier and a load-bearing structure with electronic components are provided, and further the circuit structure is coupled to the load-bearing structure by a plurality of conductive components. In addition, a package layer is formed between the circuit structure and the load-bearing structure, so that the package layer encloses the conductive elements and the electronic components, and the carrier is then removed to strengthen the structural strength of the circuit structure by the configuration of the carrier, so that the problem of warpage of the circuit structure can be avoided before stacking the circuit structure to the load-bearing structure.

Description

Package stack structure and its manufacturing method and package structure

The present invention relates to a semiconductor packaging process, in particular to a packaging stack structure and its manufacturing method and packaging structure.

With the evolution of semiconductor packaging technology, semiconductor devices have developed different packaging types. In order to improve electrical functions and save packaging space, the industry has developed a stack of multiple packaging structures to form a package on Package, referred to as POP) package type, this package type can play a system of package (SiP) heterogeneous integration characteristics, can be different functions of electronic components, such as: memory, central processing unit, graphics processor, image application processing The stacking design achieves system integration and is suitable for various light, thin, short and small electronic products.

FIG. 1 is a schematic cross-sectional view of the conventional package stack structure 1. As shown in FIG. 1, the package stack structure 1 includes a first semiconductor element 10, a first packaging substrate 11, a second packaging substrate 12, a plurality of solder balls 13, a second semiconductor element 14 and a packaging glue 15. The first packaging substrate 11 has a core layer 110 and a plurality of circuit layers 111, and the second packaging substrate 12 has a core layer 120 and a plurality of circuit layers 121. The first semiconductor element 10 is provided on the first packaging substrate 11 in a flip chip manner, and the second semiconductor element 14 is also provided on the second packaging substrate 12 in a flip chip manner. The solder balls 13 are used to connect and electrically couple the first packaging substrate 11 and the second packaging substrate 12. The packaging compound 15 covers the solder balls 13 and the first semiconductor element 10. Optionally, a primer 16 is formed between the first semiconductor element 10 and the first packaging substrate 11.

However, in the aforementioned conventional package stack structure 1, both the first package substrate 11 and the second package substrate 12 have core layers 110, 120, resulting in high manufacturing costs, and the thickness H of the package stack structure 1 is approximately 620 microns, which is not consistent with the current The demand for lighter, thinner and shorter products.

Therefore, how to overcome the above-mentioned problems of the conventional technology has actually become a problem that the industry urgently needs to overcome.

In view of the deficiencies of the above-mentioned conventional technology, the present invention provides a package stack structure, which includes: a supporting structure defined with a first side and a second side opposite to each other, wherein the first side of the supporting structure is provided with at least one electronic component And the circuit structure, which has a first surface and a second surface opposite to each other, and the first surface is provided with a supporting member, and the second surface is bonded to the first side of the supporting structure with a plurality of conductive elements.

The aforementioned package stack structure further includes a package layer formed between the circuit structure and the carrying structure to cover the conductive elements and the electronic element.

The present invention also provides a manufacturing method of a package stack structure, which includes: providing a circuit structure provided with a bearing member and a bearing structure, wherein the bearing structure is defined with a first side and a second side opposite to each other, and the bearing structure The first side is provided with at least one electronic element; the circuit structure is combined with a plurality of conductive elements on the first side of the carrying structure, and an encapsulation layer is formed between the circuit structure and the carrying structure, so that the encapsulation layer Covering the conductive elements and the electronic element; and removing the carrier.

In the aforementioned manufacturing method, the conductive elements are first arranged on the circuit structure, and then the circuit structure is bonded to the supporting structure with the conductive elements.

In the aforementioned manufacturing method, the conductive elements are first arranged on the supporting structure, and then the circuit structure is bonded to the supporting structure with the conductive elements.

In the aforementioned manufacturing method, the circuit structure is cut into a single shape before being combined with the load-bearing structure, and the load-bearing structure is a full-page type before being combined with the circuit structure.

In the aforementioned manufacturing method, the circuit structure is in a full-page configuration before being combined with the carrying structure, and the supporting structure is in a full-page configuration before being combined with the circuit structure.

In the aforementioned manufacturing method, the circuit structure is in a full-page form before the load-bearing structure is combined, and the load-bearing structure is in a cut single form before the circuit structure is combined.

In the aforementioned manufacturing method, after removing the carrier, the cut sheet is performed.

In the aforementioned manufacturing method, the circuit structure is cut into a single type before being combined with the carrying structure, and the supporting structure is cut into a single type before being combined with the wiring structure.

In the aforementioned package stack structure and its manufacturing method, the carrier is a silicon wafer, which contacts the dielectric material that combines the circuit structure. For example, the carrier is removed by grinding.

In the aforementioned package stack structure and its manufacturing method, the circuit structure is a circuit redistribution layer structure.

In the aforementioned package stack structure and its manufacturing method, the circuit structure has a first surface and a second surface opposite to each other, and the first surface is bonded to the carrier, and the second surface is configured with a plurality of stacked contacts, In order to combine these conductive elements.

In the aforementioned package stack structure and its manufacturing method, the carrier is made of glass, and a bonding layer is used to contact and bond the dielectric material of the circuit structure. For example, the carrier and the bonding layer are removed by peeling.

In the aforementioned package stack structure and its manufacturing method, the circuit structure has a first surface and a second surface opposite to each other, and the second surface is bonded to the carrier, and the first surface is configured with a plurality of stack contacts, In order to combine these conductive elements.

In the aforementioned package stack structure and its manufacturing method, the conductive element is a solder ball, a metal pillar or a metal bump covered with an insulating block.

The present invention also provides a package structure, which includes: a circuit structure having two opposite sides; a bearing member disposed on one side of the circuit structure; and a conductive element disposed on the other side of the circuit structure. The circuit structure is electrically connected.

In the aforementioned package structure, the carrier is a silicon wafer, which contacts and combines the dielectric material of the circuit structure.

In the aforementioned packaging structure, the carrier is made of glass, and a bonding layer is used to contact and bond the dielectric material of the circuit structure.

In the aforementioned package structure, the circuit structure is a circuit redistribution layer structure.

In the aforementioned package structure, the conductive element is a solder ball, a metal pillar, or a metal bump coated with an insulating block.

It can be seen from the above that the package stack structure of the present invention and its manufacturing method and package structure mainly rely on the configuration of the carrier to strengthen the structural strength of the circuit structure. Therefore, compared with the conventional technology, if the circuit structure of the present invention is The coreless layer design can not only greatly reduce the overall thickness of the package stack structure, but also avoid the problem of warping of the circuit structure before stacking the circuit structure to the carrying structure.

1,2,2’,4,4’,4”‧‧‧Package stack structure

10‧‧‧The first semiconductor device

11‧‧‧The first package substrate

110,120‧‧‧Core layer

111,121‧‧‧Line layer

12‧‧‧Second package substrate

13‧‧‧Solder ball

14‧‧‧Second semiconductor element

15‧‧‧Packaging gel

16‧‧‧ Primer

2"‧‧‧Packaging structure

2a,2a’‧‧‧Line structure

20‧‧‧First carrier

20’‧‧‧Second Carrier

20a‧‧‧Release layer

20b‧‧‧Combination layer

200‧‧‧Dielectric layer

200’‧‧‧Groove

21‧‧‧Line Department

21a‧‧‧First surface

21b‧‧‧Second surface

210‧‧‧Dielectric

211‧‧‧Line layer

212,212’‧‧‧Stacking contacts

212a‧‧‧Conductive layer

212b‧‧‧金‧‧‧genus block

22‧‧‧Metal layer

29,29’,29”‧‧‧Metal structure

29a‧‧‧First metal layer

29b‧‧‧Second metal layer

29c‧‧‧The third metal layer

290‧‧‧Stacking contacts

3,3’‧‧‧Packaging components

3a,3a’‧‧‧Bearing structure

30a‧‧‧First side

30b‧‧‧Second side

32‧‧‧Insulation layer

33‧‧‧Wiring layer

330‧‧‧Electrical connection pad

34‧‧‧Insulation protection layer

35‧‧‧Conductive bump

40,44‧‧‧Electronic components

40a‧‧‧working surface

40b‧‧‧Inactive surface

400‧‧‧electrode pad

41‧‧‧Packaging layer

42‧‧‧External components

43‧‧‧Solder material

45‧‧‧Conductive element

H,L,T‧‧‧Thickness

S,D‧‧‧cutting path

Figure 1 is a schematic cross-sectional view of a conventional package stack structure.

2A to 2F are schematic cross-sectional views of the first embodiment of the manufacturing method of the package stack structure of the present invention.

Figures 2A' and 2A" are partial enlarged schematic diagrams of different embodiments of Figure 2A.

Figure 2B' is a partial enlarged schematic view of another embodiment of Figure 2B.

Figures 2C' to 2E' are another embodiment of Figures 2C to 2E.

3A to 3E are schematic cross-sectional views of the second embodiment of the manufacturing method of the package stack structure of the present invention.

Figures 3B' and 3B" are different embodiments of Figure 3B.

Figures 3C' to 3D' are the subsequent processes of Figure 3B'.

4A to 4D are schematic cross-sectional views of the third embodiment of the manufacturing method of the package stack structure of the present invention.

5A to 5C are schematic cross-sectional views of the fourth embodiment of the manufacturing method of the package stack structure of the present invention.

The following specific examples illustrate the implementation of the present invention. Those familiar with the art can easily understand the other advantages and effects of the present invention from the contents disclosed in this specification.

It should be noted that the structures, proportions, sizes, etc. shown in the drawings in this manual are only used to match the contents disclosed in the manual for the understanding and reading of those familiar with the art, and are not intended to limit the implementation of the present invention Therefore, it does not have any technical significance. Any structural modification, proportional relationship change, or size adjustment should still fall within the scope of the present invention without affecting the effects and objectives that can be achieved. The technical content disclosed by the invention can be covered. At the same time, the terms such as "first", "second", "上", and "一" cited in this specification are only for ease of description and are not used to limit the scope of the present invention. , The change or adjustment of the relative relationship shall be regarded as the scope of the implementation of the present invention without substantial changes to the technical content.

Please refer to FIGS. 2A to 2F, which are schematic cross-sectional views of the first embodiment of the manufacturing method of the package stack structure 2, 2'of the present invention.

As shown in FIG. 2A, a dielectric layer 200 is formed on a first carrier 20, and then a plurality of metal structures 29 are formed on the dielectric layer 200.

In this embodiment, the first carrier 20 is a semiconductor board, such as a temporary full-page silicon wafer (Si wafer).

As shown in Figure 2A', the metal structure 29 may include multiple metal layers. For example, a dielectric layer 200 with a plurality of openings is formed on the first carrier 20, and then the first metal layer 29a is formed on the dielectric layer. On the electrical layer 200 and in the openings, a second metal layer 29b is then formed on a portion of the first metal layer 29a, and then the portion of the first metal layer 29a not covered with the second metal layer 29b is removed to overlap The first and second metal layers 29a, 29b serve as the metal structure 29'. Or, as shown in FIG. 2A", after removing the portion of the first metal layer 29a that is not covered with the second metal layer 29b, a third metal layer 29c is formed on the second metal layer 29b to make phase The stacked first to third metal layers 29a, 29b, 29c serve as the metal structure 29".

As shown in FIG. 2B, a circuit portion 21 is formed on the dielectric layer 200 and the metal structure 29, so that the circuit portion 21, the dielectric layer 200 and the metal structure 29 constitute a full-page circuit structure 2a.

In this embodiment, the circuit portion 21 has a first surface 21a and a second surface 21b opposite to each other. The first surface 21a combines the dielectric layer 200 and the metal structure 29, and the circuit portion 21 has The dielectric body 210 and the circuit layer 211 that combines the dielectric body 210 and is electrically connected to the metal structure 29, and the outermost circuit layer 211 may be formed with an under bump metallurgy (UBM) to As a stacked contact 212; or, the outermost circuit layer 211 forms a BOT (Bump on trace) type metal bump to serve as a stacked contact 212', as shown in the conductive layer 212a and the metal block 212b in Figure 2B' constitute.

Furthermore, the circuit part 21 can be completed by a redistribution layer (RDL) process. For example, since the dielectric layer used to form the circuit layer in the wafer process needs to be formed by chemical vapor deposition (CVD) to form silicon nitride or silicon oxide, the cost is relatively high, so general non-wafer can be used The circuit is formed by the process method, that is, the low-cost polymer dielectric layer, such as polyimide (PI) and polybenzoxazole (PBO), is formed between the circuit layers by coating Insulate.

As shown in FIG. 2C, the conductive element 45 is bonded to the stack contact 212 of the circuit structure 2a of the entire layout to form a package structure 2", and a package assembly 3 is provided, which includes a carrier structure 3a of the entire layout and bonding The electronic component 40 of the supporting structure 3a, and the supporting structure 3a is defined with a first side 30a and a second side 30b opposite to each other.

In this embodiment, the carrying structure 3a is a circuit structure with a core layer or a coreless layer, such as a package substrate (substrate), which has a fan-out type redistribution layer (redistribution layer). , Referred to as RDL) line configuration. Specifically, the carrying structure 3a includes a plurality of insulating layers 32 and a wiring layer 33 disposed on the insulating layer 32, and the insulating layer 32 is formed of a material such as prepreg, molding compound, or A photosensitive dielectric layer, but not limited thereto, and an insulating protective layer 34 such as a solder resist layer can be formed on the first side 30a of the supporting structure 3a, so that part of the surface of the wiring layer 33 is exposed to the insulating protective layer 34, as an electrical connection pad 330. It should be understood that the supporting structure 3a can also be other chip-carrying plates, such as leadframes, wafers, or other carriers with metal routing, etc., and is not limited to the above.

Furthermore, the electronic component 40 is an active component, a passive component, or a combination of both, wherein the active component is a semiconductor chip, and the passive component is a resistor, a capacitor, and an inductor. For example, the electronic component 40 is a semiconductor chip, which has an active surface 40a and a non-active surface 40b opposite to each other. The active surface 40a has a plurality of electrode pads 400, and the electrode pad 400 uses a plurality of conductive bumps 35 in a flip chip manner. It is arranged on the first side 30a of the supporting structure 3a and electrically connected to a portion of the wiring layer 33.

Alternatively, the electronic component 40 can be electrically connected to the supporting structure 3a by wire bonding through a plurality of bonding wires (the figure is omitted); or, the electronic component 40 can directly contact the circuit of the supporting structure 3a, as the electronic component 40 is embedded Buried in the supporting structure 3a.

It should be understood that there are many ways in which the electronic component 40 is electrically connected to the supporting structure 3a, which is not limited to the above.

As shown in FIG. 2D, the circuit structure 2a of the entire layout is bonded to the electrical connection pads 330 of the supporting structure 3a of the entire layout with the stack contacts 212 through the conductive elements 45. Next, an encapsulation layer 41 is formed between the circuit structure 2a of the entire page and the carrying structure 3a of the entire page, so that the encapsulation layer 41 covers the electronic component 40, the conductive elements 45 and the conductive bumps 35.

In this embodiment, the conductive element 45 is a metal bump coated with an insulating block, a metal pillar such as a copper pillar, a solder ball, or a solder ball with a core copper ball, etc. The shape is not particularly limited, and it can be a cylinder, an elliptic cylinder, or a polygonal cylinder.

Furthermore, in other embodiments, the conductive element 45 may be formed on the supporting structure 3a first, and then combined with the circuit structure 2a; or, another conductive element may be formed on the supporting structure 3a, and then The conductive element 45 of the package structure 2" is combined with the conductive element of the carrying structure 3a.

Moreover, the encapsulation layer 41 is an insulating material, such as an epoxy resin encapsulant, and is not particularly limited.

In addition, before combining the circuit structure 2a and the supporting structure 3a, a primer (not shown) may be formed between the electronic component 40 and the supporting structure 3a to cover the conductive bumps 35.

As shown in Figure 2E, the first carrier 20 is removed through a process such as grinding to expose the metal structure 29 and the dielectric layer 200, and a plurality of external components 42 are formed on the second side 30b of the carrier structure 3a The wiring layer 33 is electrically connected.

In this embodiment, the external component 42 is, for example, a solder ball or other metal body for connecting to an electronic device such as a circuit board in the subsequent manufacturing process (the figure is omitted).

As shown in Fig. 2F, the singulation process is performed along the cutting path S shown in Fig. 2E to obtain the package stack structure 2', and the metal structure 29 is combined with a conductive material such as a solder material 43 to join another Such as the electronic component 44 of the memory chip (see Figure 2F).

In another embodiment, as shown in Fig. 2C', the circuit structure 2a of the entire layout can be pre-cut to obtain a plurality of cut circuit structures 2a', and then each of the cut circuits The circuit structure 2a' is stacked on the supporting structure 3a of the full-page surface through the conductive element 45. Then, as shown in Fig. 2D', an encapsulation layer 41 is formed between the diced circuit structure 2a' and the full-page carrier structure 3a, so that the encapsulation layer 41 covers the electronic component 40 and the The conductive elements 45, the conductive bumps 35 and the diced circuit structure 2a'. After that, as shown in Figure 2E', first remove the first carrier 20 through a process such as grinding, and then perform a dicing process along the cutting path S shown in Figure 2D' to obtain as shown in Figure 2F The package stack structure 2'.

Please refer to FIGS. 3A to 3E, which are schematic cross-sectional views of the second embodiment of the manufacturing method of the package stack structure 4, 4'following the process of FIG. 2B. The difference between this embodiment and the first embodiment lies in the manufacturing process of the circuit structure. The other manufacturing processes are substantially the same. Therefore, only the differences will be described below, and the similarities will not be repeated.

As shown in FIG. 3A, a first carrier 20 like glass is provided, and a release layer 20a is formed thereon to make a dielectric layer 200, a metal structure 29, and a stacked contact 212, and then form a circuit structure After 2a, a second supporting member 20' is disposed on the second surface 21b of the circuit structure 2a.

In this embodiment, the second carrier 20' is also full-page glass, which is bonded to the second surface 21b of the circuit structure 2a by a bonding layer 20b (such as glue), and the bonding layer 20b covers The stacking contact 212.

As shown in FIG. 3B, the first carrier 20 and its release layer 20a are removed, and the metal structure 29 and the dielectric layer 200 are exposed.

In this embodiment, the metal structure 29 is exposed on the surface of the dielectric layer 200 as a stack contact 290.

Furthermore, in another embodiment, as shown in FIG. 3B', a metal layer 22 can be formed on the metal structure 29 by electroplating, so that the metal layer 22 is electrically connected to the circuit layer 211 of the circuit structure 2a' Wherein, the metal layer 22 is, for example, an electrical contact pad or another metal layer under the bump to serve as a stack contact.

In addition, pre-cutting operations can be performed according to requirements. As shown in Figure 3B', when the second carrier 20' is of a strip unit type (such as a rectangular strip, which is combined with a plurality of cut circuit structures 2a'), it can be cut directly Process to obtain a plurality of prefabricated components (including the cut circuit structure 2a' and the cut second carrier 20' combined with the circuit structure 2a'). Or, as shown in Figure 3B", when the second carrier 20' is of a wafer type (such as a full-page round shape, which is combined with a plurality of the circuit structures 2a), it can be placed on the second carrier 20' A trench 200' is cut (not extended to the circuit structure 2a).

As shown in Fig. 3C, following the process shown in Fig. 3B, the circuit structure 2a is combined with its metal layer 22 (or stacked contacts 290) with a plurality of conductive elements 45 to form a package structure, and then the package structure The conductive element 45 is bonded to the electrical connection pad 330 of the carrying structure 3a as shown in FIG. 2C. Next, an encapsulation layer 41 is formed between the circuit structure 2a and the carrying structure 3a, so that the encapsulation layer 41 covers the electronic component 40, the conductive components 45 and the conductive bumps 35.

As shown in FIG. 3D, the stack contact 212 is exposed by removing the second carrier 20' and its bonding layer 20b, and a plurality of external components 42 are formed on the second side 30b of the carrier structure 3a for electrical connection The wiring layer 33.

In this embodiment, the external component 42 is, for example, a solder ball or other metal body for connecting to an electronic device such as a circuit board in the subsequent manufacturing process (the figure is omitted).

As shown in FIG. 3E, the singulation process is performed along the cutting path S shown in FIG. 3D to obtain the package stack structure 4', and the stack contacts 212 can be combined with conductive materials such as solder material 43 to bond Another electronic component 44 such as a memory chip.

In this embodiment, when the second carrier 20' is a unit strip type (as shown in Figure 3B or 3B'), it can be heated or illuminated (such as UV light) to make the bonding layer 20b lose Partially sticky to remove the second carrier 20' and its bonding layer 20b.

In other embodiments, as shown in Figure 3C', the process shown in Figure 3B' is continued, and the cut circuit structure 2a' is combined with the supporting structure 3a of the entire layout surface, and the subsequent steps are as After the half-cutting process is performed on the cutting path D shown in FIG. 3C', the second carrier 20' and its bonding layer 20b are removed, and then the single-cutting process is performed along the cutting path S shown in FIG. 3C' to Form the structure as shown in Figure 3D'.

In another embodiment, when the second carrier 20' is a wafer-type glass (as shown in FIG. 3B"), the encapsulation layer 41 will fill the groove 200 of the second carrier 20' Therefore, the encapsulation layer 41 in the trench 200' can be used as the cutting paths D, S to perform the half-cutting process, removing the second carrier 20' and its bonding layer 20b, and singulation process.

Please refer to FIGS. 4A to 4D, which are schematic cross-sectional views of the third embodiment of the manufacturing method of the package stack structure following the process of FIG. 2B. The main difference between this embodiment and the first embodiment lies in the manufacturing process of the package assembly 3'. The other manufacturing processes are substantially the same. Therefore, only the differences will be described below, and the similarities will not be repeated.

As shown in Figures 4A to 4B, a package assembly 3'is provided, which includes a cut-out carrier structure 3a' and an electronic component 40 combined with the carrier structure 3a', and the package assembly 3'passes through a plurality of conductive elements 45 is stacked on the circuit structure 2a of the entire layout, and a plurality of external components 42 are formed on the second side 30b of the supporting structure 3a' to electrically connect the wiring layer 33 of the supporting structure 3a'.

As shown in FIG. 4C, an encapsulation layer 41 is formed on the circuit structure 2a of the entire layout surface so that the encapsulation layer 41 covers the electronic components 40, the conductive components 45, the conductive bumps 35, and the external Part of the side surface of the element 42 and the cut carrying structure 3a'.

As shown in FIG. 4D, the first carrier 20 is removed through a process such as grinding, and a dicing process is performed along the cutting path S shown in FIG. 4C to obtain a package stack structure 4".

Please refer to FIGS. 5A to 5C, which are cross-sectional schematic diagrams of the fourth embodiment of the manufacturing method of the package stack structure following the process of FIG. 2B. The difference between this embodiment and the first embodiment lies in the manufacturing process of the package assembly 3'. The other manufacturing processes are substantially the same. Therefore, only the differences will be described below, and the similarities will not be repeated.

As shown in FIG. 5A, a package assembly 3'is provided, which includes a cut-out carrier structure 3a' and an electronic component 40 combined with the carrier structure 3a', and then the package assembly 3'is stacked through a plurality of conductive elements 45 On the circuit structure 2a' that has been cut.

As shown in FIG. 5B, an encapsulation layer 41 is formed between the singulated circuit structure 2a' and the singulated carrier structure 3a', so that the encapsulation layer 41 covers the electronic component 40 and the The conductive element 45, the conductive bumps 35, the singulated circuit structure 2a', and the singulated carrying structure 3a'.

As shown in Fig. 5C, the first carrier 20 is removed through a process such as grinding, and the singulation process is performed along the cutting path S shown in Fig. 5B to obtain the package stack structure 2 shown in Fig. 2F '.

The manufacturing method of the present invention utilizes the design of coreless circuit structures 2a, 2a' to reduce the thickness L of the package stack structure 2', 4', and uses a carrier (that is, the first carrier) 20 or the second carrier 20') to enhance the structural strength of the circuit structure 2a, 2a', for example, the thickness T of the circuit structure 2a2a' is at least 20 microns, and the package stack structure 2', 4 The minimum thickness L of',4" can be 410 microns, so compared with the prior art, the manufacturing method of the present invention can not only greatly reduce the overall thickness of the package stack structure 2', 4', 4" to meet the lightness and thinness of electronic products Short and small, and before stacking the circuit structure 2a, 2a' to the supporting structure 3a, 3a', the problem of warping of the circuit structure 2a, 2a' can be avoided.

The present invention further provides a packaging stack structure 2, 2', 4, 4', 4", which includes: a carrying structure 3a, 3a', a circuit structure 2a, 2a', and an encapsulation layer 41.

The supporting structure 3a, 3a' is defined with a first side 30a and a second side 30b opposite to each other, wherein the first side 30a of the supporting structure 3a, 3a' is provided with at least one electronic component 40.

One side of the circuit structure 2a, 2a' is provided with a supporting member (that is, the first supporting member 20 or the second supporting member 20'), and the other side is connected to the supporting structure 3a by a plurality of conductive elements 45 , 3a' on the first side 30a.

The encapsulation layer 41 is formed between the circuit structure 2a, 2a' and the first side 30a of the supporting structure 3a, 3a' to cover the conductive elements 45 and the electronic element 40.

In one embodiment, the carrier (that is, the first carrier 20) is a silicon wafer that contacts the dielectric material (that is, the dielectric layer 200) that combines the circuit structures 2a, 2a'.

In one embodiment, the circuit structure 2a, 2a' has a first surface 21a and a second surface 21b opposite to each other, and the first surface 21a is coupled to the carrier (that is, the first carrier 20), and The second surface 21b is configured with a plurality of stacked contacts 212, 212' to combine the conductive elements 45.

In one embodiment, the carrier (that is, the second carrier 20') is made of glass, and the bonding layer 20b contacts the dielectric material (that is, the dielectric body 210) that connects the circuit structure 2a.

In one embodiment, the circuit structure 2a, 2a' has a first surface 21a and a second surface 21b opposite to each other, and the second surface 21b is bonded to the carrier (that is, the second carrier 20'), The first surface 21 a is configured with a plurality of stacked contacts 290 (or the metal layer 22) to combine the conductive elements 45.

In summary, the package stack structure and its manufacturing method and package structure of the present invention are designed with a coreless layered circuit structure to reduce the thickness of the package stack structure, and by arranging the carrier on the circuit structure In order to strengthen the structural strength of the circuit structure, the present invention can not only greatly reduce the overall thickness of the package stack structure, but also avoid the problem of warping of the circuit structure.

The above-mentioned embodiments are used to exemplify the principles and effects of the present invention, but not to limit the present invention. Anyone who is familiar with the art can modify the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the rights of the present invention should be listed in the scope of patent application described later.

2‧‧‧Package stack structure

2a‧‧‧Line structure

20‧‧‧First carrier

200‧‧‧Dielectric layer

21‧‧‧Line Department

21a‧‧‧First surface

212‧‧‧Stacking contacts

29‧‧‧Metal structure

3a‧‧‧Bearing structure

30a‧‧‧First side

30b‧‧‧Second side

32‧‧‧Insulation layer

33‧‧‧Wiring layer

330‧‧‧Electrical connection pad

35‧‧‧Conductive bump

40‧‧‧Electronic components

41‧‧‧Packaging layer

45‧‧‧Conductive element

L,T‧‧‧Thickness

Claims (27)

A package stack structure includes: a supporting structure, defined with opposite first and second sides, wherein the first side of the supporting structure is provided with at least one electronic component, and a plurality of external components are formed on the supporting structure On the second side; and the circuit structure, which has a first surface and a second surface opposite to each other, and the first surface is provided with a supporting member, and the second surface is coupled to the first side of the supporting structure with a plurality of conductive elements on. According to the package stack structure described in claim 1, wherein the carrier is a silicon wafer that contacts the dielectric material that combines the circuit structure. According to the package stack structure described in item 1 of the scope of patent application, the circuit structure is a circuit redistribution layer structure. According to the package stack structure described in claim 1, wherein the second surface of the circuit structure is provided with a plurality of stack contacts to combine the conductive elements. According to the package stack structure described in item 1 of the scope of the patent application, the carrier is glass, and a bonding layer contacts the dielectric material of the circuit structure. The packaging stack structure described in the first item of the patent application includes a packaging layer formed between the circuit structure and the carrying structure to cover the conductive elements and the electronic elements. According to the package stack structure described in claim 1, wherein the conductive element is a solder ball, a metal pillar, or a metal bump covered with an insulating block. A manufacturing method of a package stack structure includes: providing a circuit structure provided with a bearing member and a bearing structure, wherein the bearing structure is defined with opposite first and second sides, and the first side of the bearing structure At least one electronic component is provided; the circuit structure is bonded to the first side of the carrying structure with a plurality of conductive elements, and an encapsulation layer is formed between the circuit structure and the carrying structure, so that the encapsulation layer covers the A conductive element and the electronic element; and removing the carrier, and forming a plurality of external components on the second side of the carrier structure. According to the manufacturing method of the package stack structure described in item 8 of the scope of patent application, the conductive elements are first arranged on the circuit structure, and then the circuit structure is combined with the carrying structure by the conductive elements. According to the manufacturing method of the package stack structure described in item 8 of the scope of patent application, the conductive elements are first arranged on the supporting structure, and then the circuit structure is bonded to the supporting structure with the conductive elements. According to the manufacturing method of the package stack structure described in the scope of patent application, the carrier is a silicon wafer, which contacts the dielectric material that combines the circuit structure. According to the manufacturing method of the package stack structure described in item 11 of the scope of patent application, the removal of the carrier is performed by grinding. According to the manufacturing method of the package stack structure described in item 8 of the scope of patent application, the circuit structure is a circuit redistribution layer structure. Such as the manufacturing method of package stack structure described in item 8 of the scope of patent application, which Wherein, the circuit structure has a first surface and a second surface opposite to each other, and the first surface is coupled to the carrier, and the second surface is configured with a plurality of stacked contacts for coupling the conductive elements. According to the manufacturing method of the package stack structure described in item 8 of the scope of patent application, the carrier is glass, and the dielectric material of the circuit structure is contacted and bonded by a bonding layer. The manufacturing method of the package stack structure as described in item 15 of the scope of patent application, wherein the carrier and the bonding layer are removed by peeling. According to the manufacturing method of the package stack structure described in the scope of patent application, the circuit structure is cut into a single type before the supporting structure is combined, and the carrier is half-cut before removing the supporting member. According to the manufacturing method of the package stack structure described in item 8 of the patent application, the conductive element is a solder ball, a metal pillar or a metal bump covered with an insulating block. The manufacturing method of the package stack structure as described in item 8 of the scope of patent application, wherein the circuit structure is cut into a single type before being combined with the supporting structure, and the supporting structure is a full-page type before being combined with the circuit structure . According to the manufacturing method of the package stack structure described in item 8 of the scope of patent application, wherein the circuit structure is in a full-page configuration before being combined with the carrying structure, and the supporting structure is in a full-page configuration before being combined with the circuit structure. The manufacturing method of the package stack structure described in item 8 of the scope of patent application, wherein the circuit structure is cut into a single type before being combined with the supporting structure, and the supporting structure is cut into a single type before being combined with the wiring structure state. Such as the manufacturing method of package stack structure described in item 8 of the scope of patent application, which In this case, the circuit structure is in a full-page form before the load-bearing structure is combined, and the load-bearing structure is in a cut single form before the circuit structure is combined. The manufacturing method of one of the package stack structures described in item 18, 19, or 22 of the scope of patent application, wherein, after removing the carrier, the cutting is performed. A package structure includes: a circuit structure containing a dielectric material, which has two opposite sides; a carrier, which is arranged on one side of the circuit structure and contacts the dielectric material that is combined with the circuit structure; and a conductive element, It is arranged on the other side of the circuit structure to electrically connect the circuit structure. For the package structure described in item 24 of the scope of patent application, the circuit structure is a circuit redistribution layer structure. In the package structure described in item 24 of the scope of patent application, the carrier is a silicon wafer. According to the package structure described in claim 24, the conductive element is a solder ball, a metal pillar, or a metal bump covered with an insulating block.

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