US11127699B2 - Chip package structure and manufacturing method thereof - Google Patents
Chip package structure and manufacturing method thereof Download PDFInfo
- Publication number
- US11127699B2 US11127699B2 US16/830,235 US202016830235A US11127699B2 US 11127699 B2 US11127699 B2 US 11127699B2 US 202016830235 A US202016830235 A US 202016830235A US 11127699 B2 US11127699 B2 US 11127699B2
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- United States
- Prior art keywords
- conductive
- chip
- redistribution layer
- encapsulant
- layer
- Prior art date
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 239000008393 encapsulating agent Substances 0.000 claims abstract description 48
- 239000000758 substrate Substances 0.000 claims description 31
- 239000000463 material Substances 0.000 claims description 27
- 239000004020 conductor Substances 0.000 claims description 10
- 230000000149 penetrating effect Effects 0.000 claims 1
- 239000010410 layer Substances 0.000 description 113
- 238000000034 method Methods 0.000 description 16
- 230000008569 process Effects 0.000 description 15
- 230000005540 biological transmission Effects 0.000 description 10
- 230000008054 signal transmission Effects 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 238000007747 plating Methods 0.000 description 4
- 238000005137 deposition process Methods 0.000 description 3
- 238000000227 grinding Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000012792 core layer Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000002860 competitive effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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Definitions
- the disclosure relates to a chip package structure and a manufacturing method thereof, and in particular to a chip package structure having a plurality of chips and a manufacturing method thereof.
- the disclosure provides a chip package structure having favorable signal transmission quality or efficiency and a manufacturing method of the chip package structure.
- the chip package structure of the disclosure includes a first chip, an encapsulant, a first redistribution layer, a second redistribution layer, a second chip, and a third chip.
- the first chip has a first active surface, a first back side surface opposite to the first active surface, a plurality of conductive vias, and a plurality of first conductive connectors located on the back side surface.
- the encapsulant covers the first active surface, the first back side surface, and the conductive connectors of the first chip.
- the encapsulant has a first encapsulating surface and a second encapsulating surface opposite to the first encapsulating surface.
- the first redistribution layer is located on the first encapsulating surface of the encapsulant.
- the second redistribution layer is located on the second encapsulating surface of the encapsulant.
- the second chip is disposed on the second redistribution layer.
- the third chip is disposed on the second redistribution layer.
- the manufacturing method of the chip package structure of the disclosure includes the following steps: forming a first redistribution layer on a carrier substrate; disposing a first chip on the first redistribution layer, the first chip having a first active surface, a first back side surface opposite to the active surface, a plurality of conductive vias, and a plurality of first conductive connectors located on the first back side surface, and the first conductive connectors being electrically connected to the first redistribution layer; forming an encapsulant on the first redistribution layer, the encapsulant covering the first active surface, the first back side surface, and the first conductive connectors of the first chip; forming a second redistribution layer on the encapsulant; disposing a second chip on the second redistribution layer; and disposing a third chip on the second redistribution layer.
- the chip package structure and the manufacturing method of the chip package structure of the disclosure can facilitate the signal transmission quality or efficiency.
- FIG. 1A to FIG. 1G are schematic partial cross-sectional views illustrating part of a manufacturing method of a chip package structure according to a first embodiment of the disclosure.
- FIG. 1H is a schematic partial top view of the chip package structure according to the first embodiment of the disclosure.
- FIG. 1I is a schematic partial cross-sectional view illustrating part of the manufacturing method of the chip package structure according to the first embodiment of the disclosure.
- FIG. 2A to FIG. 2F are schematic partial cross-sectional views illustrating part of a manufacturing method of a chip package structure according to a second embodiment of the disclosure.
- a first redistribution layer 160 is formed on a carrier substrate 191 .
- the disclosure has no special limitation on the carrier substrate 191 as long as the carrier substrate 191 can be adapted to carry a layer formed thereon or a component disposed thereon.
- the carrier substrate 191 may have a light to heat conversion (LTHC) adhesive layer or other similar release layer thereon.
- LTHC light to heat conversion
- the first redistribution layer 160 may include insulating layers 161 and conductive layers 162 .
- a topmost insulating layer 161 a i.e., the insulating layer 161 farthest from the carrier substrate 191
- the openings 161 b may expose a topmost conductive layer 162 a (i.e., the conductive layer 162 farthest from the carrier substrate 191 ).
- the first redistribution layer 160 may be formed by a commonly used semiconductor process (such as a deposition process, a photolithography process, and/or an etching process), which is omitted herein.
- a plurality of third conductive connectors 150 may be disposed on the first redistribution layer 160 .
- the third conductive connectors 150 may be embedded in the openings 161 b (shown in FIG. 1A ) of the topmost insulating layer 161 a , and electrically connected to corresponding portions in the topmost conductive layer 162 a.
- the third conductive connector 150 may include a pre-formed conductive member.
- the third conductive connector 150 may include a pre-formed conductive pillar, but the disclosure is not limited thereto.
- the third conductive connectors 150 may be formed by a commonly used semiconductor process (such as a photolithography process, a sputtering process, an electroplating process, and/or an etching process), but the disclosure is not limited thereto.
- the third conductive connector 150 may include a plating core layer and a seed layer surrounding the plating core layer, but the disclosure is not limited thereto.
- a first chip 110 is disposed on the first redistribution layer 160 .
- the first chip 110 includes a substrate 113 .
- the substrate 113 has a component region (not shown) on one side, and a surface on which the component region is located may be referred to as an active surface. That is, the first chip 110 has a first active surface 111 and a first back side surface 112 , and the first back side surface 112 is opposite to the first active surface 111 .
- the first chip 110 may include a plurality of connection pads 116 , a circuit structure 114 , a plurality of first conductive connectors 117 , a plurality of second conductive connectors 118 , and a plurality of conductive vias 115 .
- the connection pads 116 are located on the first active surface 111 .
- the first conductive connectors 117 are located on the first back side surface 112 .
- the second conductive connectors 118 are located on the first active surface 111 .
- the conductive vias 115 penetrate through the substrate 113 .
- the first conductive connectors 117 may be electrically connected to the first redistribution layer 160 .
- components in the component region may be electrically connected to the corresponding connection pads (for example, a portion of the connection pads 116 of the first chip 110 ) through a corresponding back end of line interconnect.
- one of the first conductive connectors 117 and one of the second conductive connectors 118 may be electrically connected through the corresponding connection pad 116 , the corresponding conductive via 115 , and a corresponding portion of the circuit conductive layer 114 b .
- the conductive via 115 may be electrically connected to the corresponding connection pad 116 through a corresponding back end of line interconnect.
- connection pad 116 is, for example, an aluminum pad or a copper pad, but the disclosure is not limited thereto.
- the connection pad 116 may be partially covered by a passivation layer 119 .
- the circuit structure 114 may include circuit insulating layers 114 a , 114 c and a circuit conductive layer 114 b .
- the circuit insulating layer 114 a may be located between the circuit conductive layer 114 b and the substrate 113 .
- the circuit insulating layer 114 c may cover the circuit conductive layer 114 b.
- the via conductive layer 115 b may be of a multilayer structure.
- the via conductive layer 115 b may include a barrier layer, a seed layer, and a plating layer, but the disclosure is not limited thereto.
- the circuit insulating layer 114 a and the via insulating layer 115 a closest to the substrate 113 may be a same layer, and the circuit conductive layer 114 b and the via conductive layer 115 b closest to the substrate 113 may be a same layer.
- the substrate 113 may be a silicon substrate, and the conductive via 115 may be referred to as a through silicon via (TSV), but the disclosure is not limited thereto.
- TSV through silicon via
- a portion of the encapsulating material 149 may be removed to form an encapsulant 140 .
- the encapsulant 140 may cover the first active surface 111 , the first back side surface 112 , side walls 117 s of the first conductive connectors 117 , side walls 118 s of the second conductive connectors 118 , and side walls 150 s of the third conductive connectors 150 of the first chip 110 .
- the encapsulant 140 may expose a portion of the second conductive connectors 118 and a portion of the third conductive connectors 150 .
- the possibility of damage to the components of the component region or the connection pads 116 can be reduced when the aforementioned planarization step is performed.
- a second redistribution layer 170 is formed on the encapsulant 140 .
- the disclosure does not limit a sequence in which the second chip 120 is disposed on the second redistribution layer 170 and the third chip 130 is disposed on the second redistribution layer 170 .
- an underfill may be formed between the second chip 120 and the second redistribution layer 170 and/or between the third chip 130 and the second redistribution layer 170 .
- the carrier substrate 191 may be removed to expose the first redistribution layer 160 .
- the disclosure does not limit a sequence in which the second chip 120 is disposed on the second redistribution layer 170 , the third chip 130 is disposed on the second redistribution layer 170 and the carrier substrate 191 is removed.
- the second chip 120 and the third chip 130 may be disposed on the second redistribution layer 170 first, and then the carrier substrate 191 may be removed.
- the carrier substrate 191 may be removed first, and then the second chip 120 or the third chip 130 may be disposed on the second redistribution layer 170 .
- the fifth conductive terminals 185 may include solder balls, but the disclosure is not limited thereto.
- the chip package structure 100 includes the first chip 110 , the encapsulant 140 , the first redistribution layer 160 , the second redistribution layer 170 , the second chip 120 , and the third chip 130 .
- the first chip 110 has the first active surface 111 , the first back side surface 112 , the conductive vias 115 , and the first conductive connectors 117 .
- the first back side surface 112 is opposite to the first active surface 111 .
- the first conductive connectors 117 are located on the first back side surface 112 .
- the encapsulant 140 covers the first active surface 111 , the first back side surface 112 , and the conductive connectors 117 of the first chip 110 .
- the encapsulant 140 has a first encapsulating surface 141 and a second encapsulating surface 142 .
- the second encapsulating surface 142 is opposite to the first encapsulating surface 141 .
- the first redistribution layer 160 is located on the first encapsulating surface 141 of the encapsulant 140 .
- the second redistribution layer 170 is located on the second encapsulating surface 142 of the encapsulant 140 .
- the second chip 120 is disposed on the second redistribution layer 170 .
- the third chip 130 is disposed on the second redistribution layer 170 .
- the first chip 110 may be an active die, but the disclosure is not limited thereto.
- the first chip 110 may be a bridge die for interconnecting the second chip 120 and the third chip 130 .
- the first chip 110 may further have the second conductive connectors 118 on the first active surface 111 .
- the encapsulant 140 further covers the second conductive connectors 118 .
- the chip package structure 100 may further include the third conductive connectors 150 .
- the third conductive connectors 150 penetrate through the encapsulant 140 .
- the third conductive connectors 150 are electrically connected to a portion of the first redistribution layer 160 and a portion of the second redistribution layer 170 .
- a diameter of the third conductive connectors 150 (for example, a minimum diameter 150 w ) is greater than a diameter of the conductive vias 115 (for example, a minimum diameter 115 w ; shown in FIG. 1I ).
- the minimum diameter 150 w of the third conductive connectors 150 is greater than the minimum diameter 115 w of the conductive vias 115 (shown in FIG. 1I ). That is, a maximum transmission current value of the third conductive connectors 150 may be greater than a maximum transmission current value of the conductive vias 115 . Therefore, the third conductive connectors 150 may be suitable for (but not limited to) transmission of a larger current (compared to the maximum transmission current value of the conductive vias 115 ) for a power supply, a ground terminal or the like, and the conductive vias 115 may be suitable for (but not limited to) transmission of a smaller current (compared to the maximum transmission current value of the third conductive connectors 150 ) for a signal or the like.
- the chip package structure 100 may further include the first conductive terminals 181 and the second conductive terminals 182 .
- the first conductive terminals 181 are located between the second chip 120 and the second redistribution layer 170 , and the first conductive terminals 181 overlap the first chip 110 .
- the second conductive terminals 182 are located between the second chip 120 and the second redistribution layer 170 , and the second conductive terminals 182 do not overlap the first chip 110 .
- the two adjacent first conductive terminals 181 have a first pitch P 1 therebetween, the two adjacent second conductive terminals 182 have a second pitch P 2 therebetween, and the first pitch P 1 is smaller than the second pitch P 2 .
- a projection area of each of the first conductive terminals 181 may be smaller than a projection area of each of the second conductive terminals 182 .
- the projection area of each of the first conductive terminals 181 projected on the second encapsulating surface 142 may be smaller than the projection area of each of the second conductive terminals 182 projected on the second encapsulating surface 142 (or a virtual surface parallel to the first encapsulating surface 141 ).
- the first conductive terminals 181 are electrically connected to the corresponding conductive vias 115
- the second conductive terminals 182 are electrically connected to the corresponding third conductive connectors 150
- the minimum diameter 150 w of the third conductive connectors 150 is greater than the minimum diameter 115 w of the conductive vias 115
- the projection area of each of the second conductive terminals 182 is greater than the projection area of each of the first conductive terminals 181 .
- the chip package structure 100 may further include the third conductive terminals 183 and the fourth conductive terminals 184 .
- the third conductive terminals 183 are located between the third chip 130 and the second redistribution layer 170 , and the third conductive terminals 183 overlap the first chip 110 .
- the fourth conductive terminals 184 are located between the third chip 130 and the second redistribution layer 170 , and the fourth conductive terminals 184 do not overlap the first chip 110 .
- the two adjacent third conductive terminals 183 have a third pitch P 3 therebetween, the two adjacent fourth conductive terminals 184 have a fourth pitch P 4 therebetween, and the third pitch P 3 is smaller than the fourth pitch P 4 .
- the third conductive connectors 150 and the corresponding fourth conductive terminals 184 may be suitable for transmission of a larger current for a power supply, a ground terminal or the like, and the conductive vias 115 and the corresponding third conductive terminals 183 may be suitable for transmission of a smaller current for a signal or the like.
- the first active surface 111 of the first chip 110 , the second active surface 121 of the second chip 120 , and the third active surface 131 of the third chip 130 may face the second redistribution layer 170 . In this way, a signal transmission path between the first chip 110 and the second chip 120 and between the first chip 110 and the third chip 130 can be reduced, and the quality or efficiency of signal transmission can be improved.
- the second chip 120 and the third chip 130 may be homogeneous chips or heterogeneous chips, which is not limited in the disclosure.
- the second chip 120 and the third chip 130 may be dies, packaged chips, stacked chip packages, or application-specific integrated circuits (ASICs) with the same or different functions, but the disclosure is not limited thereto.
- ASICs application-specific integrated circuits
- FIG. 2A to FIG. 2F are schematic partial cross-sectional views illustrating part of a manufacturing method of a chip package structure according to a second embodiment of the disclosure.
- a manufacturing method of a chip package structure 200 is similar to the manufacturing method of the chip package structure 100 of the first embodiment. Similar components are denoted by the same reference numerals, and have similar functions, materials, or formation manners, and the descriptions are omitted.
- FIG. 2A to FIG. 2F are schematic partial cross-sectional views illustrating part of the manufacturing method of the chip package structure subsequent to a step of FIG. 1A .
- a first chip 110 is disposed on a first redistribution layer 160 .
- an encapsulating material 249 may be formed on the first redistribution layer 160 .
- the encapsulating material 249 covers a first active surface 111 , a first back side surface 112 , side walls 117 s of a plurality of first conductive connectors 117 , and side walls 118 s of a plurality of second conductive connectors 118 of the first chip 110 .
- a portion of the encapsulating material 249 may be removed by laser drilling, etching, or other suitable manners to form a plurality of openings 249 b , and the openings 249 b may expose a portion of a topmost conductive layer 162 a.
- a conductive material 259 may be filled into the opening 249 b (shown in FIG. 2C ) by a commonly used semiconductor process (such as a deposition process and/or a plating process).
- the conductive material 259 filled into the opening 249 b may be electrically connected to a portion of the topmost conductive layer 162 a.
- the conductive material 259 may further cover a surface of the encapsulating material 249 opposite to the carrier substrate 191 , but the disclosure is not limited thereto. In an embodiment not shown, the conductive material 259 may expose a surface of the encapsulating material 249 opposite to the carrier substrate 191 .
- a portion of the conductive material 259 may be removed by etching, grinding, polishing, or other suitable manners to expose the surface of the encapsulating material 249 opposite to the carrier substrate 191 .
- etching, grinding, polishing, or other suitable manners may be used to expose the end of the second conductive connector 118 opposite to the carrier substrate 191 .
- a plurality of third conductive connectors 250 and an encapsulant 240 covering side walls 250 s of the third conductive connectors 250 may be formed by the foregoing steps.
- the third conductive connector 250 may be referred to as a through mold via (TMV), but the disclosure is not limited thereto.
- TMV through mold via
- the chip package structure 200 may include the first chip 110 , the encapsulant 240 , the first redistribution layer 160 , the second redistribution layer 170 , the second chip 120 , the third chip 130 , and the third conductive connectors 250 .
- the third conductive connectors 250 penetrate through the encapsulant 240 .
- the third conductive connectors 250 are electrically connected to a portion of the first redistribution layer 160 and a portion of the second redistribution layer 170 .
- a diameter of the third conductive connectors 250 may be greater than a diameter of the conductive vias 115 (for example, a minimum diameter 115 w ; shown in FIG. 1I ).
- the second conductive terminals 182 may be electrically connected to the corresponding third conductive connectors 250
- the fourth conductive terminals 184 are electrically connected to the corresponding third conductive connectors 250 .
- a layout design of the circuit layer or circuit structure (for example, the circuit structure 114 , the first redistribution layer 160 , and/or the second redistribution layer 170 ) of the foregoing embodiments may be adjusted according to requirements in applications. That is, the circuits that are not directly connected in the drawings may be electrically connected on other cross sections or in other regions through other structures (such as conductive vias) or components.
- the chip package structure and the manufacturing method of the chip package structure of the disclosure can facilitate signal transmission quality or efficiency.
Abstract
Description
Claims (18)
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US16/830,235 US11127699B2 (en) | 2019-04-10 | 2020-03-25 | Chip package structure and manufacturing method thereof |
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TWI764032B (en) | 2022-05-11 |
TWI772736B (en) | 2022-08-01 |
CN111816644A (en) | 2020-10-23 |
TWI747127B (en) | 2021-11-21 |
US20200328161A1 (en) | 2020-10-15 |
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