CN103219318B - High-temperature-resistant MIM capacitor for microwave internal matching transistor and manufacturing method thereof - Google Patents
High-temperature-resistant MIM capacitor for microwave internal matching transistor and manufacturing method thereof Download PDFInfo
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Abstract
The invention discloses a high-temperature-resistant MIM capacitor for a microwave internal matching transistor and a manufacturing method of the high-temperature-resistant MIM capacitor and relates to the technical field of integrated circuits and manufacturing methods of the integrated circuits. The high-temperature-resistant MIM capacitor comprises a substrate, a metal lower electrode, an insulating medium layer and a metal upper electrode, wherein the metal lower electrode is fixed on the upper surface of the substrate, the insulating medium layer wraps outside the metal lower electrode, a metal lower electrode extracting hole which penetrates through the insulating medium layer is formed in the insulating medium layer, a lower electrode extracting electrode which is fixedly connected with the metal lower electrode is arranged in the metal lower electrode extracting hole, and the metal upper electrode is fixed on the upper surface of the insulating medium layer. The manufacturing method of the high-temperature-resistant MIM capacitor for the microwave internal matching transistor can avoid that the insulating medium layer is influenced by stress. The high-temperature-resistant MIM capacitor for the microwave internal matching transistor has the advantages of being good in microwave characteristics and high-temperature operating characteristics, and easy to process.
Description
Technical field
The present invention relates to the manufacture method technical field of matched crystal pipe manufacturer and integrated circuit and integrated circuit in microwave, particularly relate to a kind of electric capacity and manufacture method thereof of metal-insulator-metal type.
Background technology
Microwave high-power transistor due to operating frequency high, die area is large, the input, output-resistor of tube core is lower, the performance impact of parasitic parameter to transistor is serious, the microwave system connection that characteristic impedance is 50 ohm if directly apply to, because impedance is not seriously mated, transistor can be caused cannot to realize high-power output, the performance of transistor cannot be given full play to.For this reason, in adopting, the input, output-resistor of matching network on tube core promotes (conversion) and reduces the impact of parasitic parameter, is realize a kind of effective way that microwave power transistor is high-power, high-gain exports.The interior matching transistor of hot operation (200 DEG C-300 DEG C), the interior matching capacitance requiring it to adopt also can at high temperature reliable and stable work.
Larger lossy microwave is caused after avoiding adding interior matching network, to require frequency performance higher in matching transistor often adopt MOM(metal-oxide layer-metal) electric capacity, for improving the quality of oxide layer, generally carry out high-temperature thermal oxidation on silicon chip, then in oxide layer, form a metal electrode of electric capacity, this electrode is owing to also will support whole electric capacity, therefore generally to form the thick proof gold layer of 100 microns, remove the silicon of oxide layer another side subsequently until silicon dioxide layer, then form another metal electrode of MOM capacitor in this face.Can find out, the method is not only large by gold amount, and technique requires also relatively stricter to the corrosion of oxidation and silicon chip, otherwise can affect the rate of finished products of MOM capacitor.
Along with the continuous progress of semiconductor technology, in some, matching capacitance have employed MIM(metal-insulating barrier-metal) structure, MOM capacitor reality is also a branch of MIM capacitor, the insulating barrier of MIM capacitor generally adopts dielectric deposition processes to be formed, due to the existence of existing metal level, the temperature of deposit medium generally can not be very high, thus the compactness of dielectric layer is affected, and also can bring disadvantageous consequence to the performance of MIM capacitor.Simultaneously, the cutting of traditional MIM capacitor is on dielectric layer, dielectric layer can produce larger defect stress through the effect of diamant or emery wheel saw blade, through pyroprocesses such as follow-up sinterings, this stress can discharge, cause the defects such as insulating medium layer crackle, formed the long-term stable operation of MIM capacitor and threaten, long-term stability, the reliably working of internal matching transistor are also unfavorable.Along with the development of the microwave power device of the hot operations such as SiC, the requirement of matching capacitance in high temperature resistant work is also improved constantly.
Summary of the invention
Technical problem to be solved by this invention is to provide the effective MIM capacitor of matched crystal and manufacture method thereof in a kind of resistant to elevated temperatures microwave, described manufacture method can avoid insulating medium layer to be subject to the impact of stress, described MIM capacitor has excellent microwave property and resistance to elevated temperatures, and is easy to processing.
For solving the problems of the technologies described above, the technical solution used in the present invention is: the effective MIM capacitor of matched crystal in a kind of resistant to elevated temperatures microwave, it is characterized in that comprising substrate, lower metal electrode, insulating medium layer and electrode of metal, described lower metal electrode is fixed on the upper surface of described substrate, the outside of described lower metal electrode is enclosed with insulating medium layer, described insulating medium layer is through the high temperature anneal and which is provided with the lower metal electrode fairlead running through insulating medium layer, the bottom electrode extraction electrode be fixedly connected with described lower metal electrode is provided with in described lower metal electrode fairlead, described electrode of metal is fixed on the upper surface of described insulating medium layer.
Preferred: the thickness of described insulating medium layer is not less than 3000
, the thickness of described electrode of metal and lower metal electrode extraction electrode is 1 μm-10 μm.
Preferred: described MIM capacitor also comprises the metal layer being fixed on described substrate lower surface.
Preferred: the making material of described substrate is sapphire or carborundum.
A manufacture method for the effective MIM capacitor of matched crystal in resistant to elevated temperatures microwave, is characterized in that comprising the following steps:
(1) first time photoetching: use the figure making lower metal electrode by lithography at the upper surface of substrate;
(2) evaporation of metal: by silicon to 60 DEG C-80 DEG C, substrate evaporates 1000
-3000
nickel;
(3) peel off unnecessary metal: together got rid of with photoresist by metal on a photoresist, only leave the metal at lower metal electrode place;
(4) insulating medium layer of deposit MIM capacitor: adopt PECVD having substrate surface deposit one deck insulating medium layer of lower metal electrode;
(5) densification anneal process: above-mentioned wafer is heated to 800 DEG C-850 DEG C, carries out annealing in process to it;
(6) second time photoetching: the fairlead forming lower metal electrode, makes with photoresist as protection mask using non-fairlead part;
(7) etching insulative dielectric layer forms the fairlead of lower metal electrode;
(8) second time removes photoresist: remove clean by the photoresist eroding away the wafer surface of lower metal electrode fairlead;
(9) metal sputtering: in upper surface splash-proofing sputtering metal titanium-Jin or the Titanium tungsten-Jin formation Seed Layer of the wafer through above-mentioned process;
(10) third time photoetching: the figure forming electrode of metal and bottom electrode extraction electrode on Seed Layer surface;
(11) electrogilding: plating is carried out to electrode of metal and bottom electrode extraction electrode and thickeies, thickness 1 μm-10 μm, remove photoresist;
(12) remove and corrode the Seed Layer beyond clean electrode of metal and bottom electrode extraction electrode, forming electrode of metal and bottom electrode extraction electrode;
(13) four masks: the insulating medium layer in dicing lane is exposed in photoetching, for subsequent corrosion is prepared;
(14) insulating medium layer in dicing lane is corroded: by clean for the insulating medium layer corrosion in dicing lane;
Remove photoresist (15) the 4th times: removed by the photoresist of the MIM capacitor wafer surface after corrosion clean;
(16) scribing: the MIM capacitor be on a wafer is divided into MIM capacitor discrete one by one.
Preferred: before carrying out first time photoetching, to need backing material to clean up.
Preferred: after carrying out the 4th time and removing photoresist, to need to carry out back face metalization operation at the bottom surface of substrate.
The beneficial effect adopting technique scheme to produce is: the present invention is in layout design, add and once the insulating medium layer in the dicing lane of MIM capacitor cut place is corroded clean photoetching process, cutting electric capacity is avoided to carry out on insulating medium layer, but carry out at carborundum or sapphire surface, thus avoid the impact that capacitive insulation dielectric layer is subject to stress.
In manufacturing process, add insulating medium layer densification technique, avoid the deficiency that dielectric layer too loosens, simultaneously owing to have employed the support as electric capacity of carborundum or sapphire, instead of as MOM capacitor, use the support of proof gold as electric capacity of 100 micron thickness, avoid and proof gold to be consumed excessively and coating gold exists stress and causes the drawback that whole disk is curling after electroplating, decrease in microwave and mate MOM capacitor to pure gold consumption, the proof gold layer of about 100 microns can omit, the substitute is the metallic nickel adopted on carborundum or sapphire, about 3000
, saved the consumption of precious metal significantly, it also avoid the regular maintenance to electroplate liquid, avoided the deficiency of frequent preparation electroplate liquid.
Additionally by the introducing of high temperature densification technique, improve ability and the stability of electric capacity hot operation, also improve the long-time stability of interior matching capacitance under general work condition, to promote in microwave the overall performance electrical performance and reliability of mating high power transistor and stability favourable.The present invention is conducive to the following process of capacitance sheet, both ensure that in MIM microwave, matching capacitance has the excellent microwave property of MOM capacitor, has made again this electric capacity have the feature of the easy like that processing of mos capacitance.So its microwave property and stability and reliability are higher than traditional MIM capacitor, to shelving substantially by hand at present, sinter, in the microwave of bonding, the lifting of the stability of mesh power transistor, reliability and overall rate of finished products all can have facilitation, improves rate of finished products.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation.
Fig. 1 is the structural representation after first time photoetching;
Fig. 2 peels off unnecessary metal and structural representation after removing photoresist;
Fig. 3 is the structural representation after the insulating medium layer of deposit MIM capacitor;
Fig. 4 is the structural representation after densification anneal process;
Fig. 5 is the structural representation after second time photoetching;
Fig. 6 is the structural representation after second time photoetching through etching insulating layer medium and after removing photoresist;
Fig. 7 is the structural representation after metal sputtering forms Seed Layer;
Fig. 8 is the structural representation after third time photoetching;
Fig. 9 is the structural representation after electrogilding;
Figure 10 be remove and erodable section Seed Layer after structural representation;
Figure 11 is the structural representation after four mask;
Figure 12 erodes the insulating dielectric layer at dicing lane place and the structural representation after removing four mask glue;
Figure 13 is the structural representation after metallizing to the back side of wafer;
Figure 14 is the structural representation of the first MIM capacitor formed after scribing;
Figure 15 is the structural representation of the second MIM capacitor formed after scribing;
Wherein: the photoresist 12 after the photoresist 9 after photoresist 8, for the second time photoetching development 1, after substrate 2, lower metal electrode 3, electrode of metal 4, bottom electrode extraction electrode 5, electrode of metal 6, metal layer 7, for the first time photoetching development, the fairlead 10 of lower metal electrode, Seed Layer 11, for the third time photoetching development, the photoresist after four mask development.
Embodiment
As shown in figure 14, the effective MIM capacitor of matched crystal in a kind of resistant to elevated temperatures microwave, comprises substrate 1, lower metal electrode 2, insulating medium layer 3 and electrode of metal 5.Described lower metal electrode 2 is fixed on the upper surface of described substrate 1, the outside of described lower metal electrode 2 is enclosed with insulating medium layer 3, described insulating medium layer 3 is through the high temperature anneal and which is provided with the lower metal electrode fairlead 9 running through insulating medium layer, in described lower metal electrode fairlead 9, be provided with the bottom electrode extraction electrode 4 be fixedly connected with described lower metal electrode 2, described electrode of metal 5 is fixed on the upper surface of described insulating medium layer 3.
As shown in figure 15, the effective MIM capacitor of matched crystal in a kind of resistant to elevated temperatures microwave, is with the electric capacity difference shown in Figure 14: be provided with metal layer at the back side of substrate.
A manufacture method for the effective MIM capacitor of matched crystal in resistant to elevated temperatures microwave, comprises the following steps:
1, first backing material that the present invention adopts to be cleaned up, backing material requires do not produce obvious alloy or chemical reaction with adopted lower metal electrode material at about 850 DEG C and self also will keep stable, be unlikely to have harmful substance to discharge, substrate is SiC or the higher material of sapphire equistability, and object ensures that photoresist and metal subsequently and this backing material keep good adhesion.
2, first time photoetching: object is the figure making MIM lower metal electrode by lithography, owing to will carry out evaporation of metal subsequently, so the litho pattern requiring this photoetching to be formed preferably inverted trapezoidal or the T-shape shown in Fig. 1.
3, evaporation of metal: for ensureing that metal and substrate surface adhere to well, can adopt by silicon to 60-80 DEG C during evaporation of metal, if also have sticking problem, before evaporated metal nickel, first can evaporate 10-15
titanium, and then evaporate 1000-3000
nickel.
4, peel off unnecessary metal: together got rid of with photoresist by metal on a photoresist, only leave the metal at MIM lower metal electrode place, as shown in Figure 2.
The insulating dielectric layer of 5, deposit MIM capacitor: adopt PECVD and plasma enhanced chemical vapor deposition method having substrate surface deposit one deck insulating medium layer of lower metal electrode, as shown in Figure 3, its thickness is relevant with the size requirements of capacitance, but for ensureing the rate of finished products of MIM capacitor, generally this layer of medium is not less than 3000
simultaneously for avoiding the defects such as particle on the impact of capacitor quality, preferably adopt two-layer dielectric deposit, also two or more different insulating medium layer deposit can be adopted as the compound inslation dielectric layer of silicon dioxide and silicon nitride and silicon dioxide, and its object is also the integrality for improving insulating medium layer.
6, densification anneal process: because temperature during PECVD formation dielectric is lower, some holes or protium can be there is in insulating medium layer, as shown in Figure 3, it is unfavorable to the steady operation of MIM capacitor, so the fine and close annealing process of the high temperature that invention increases insulating medium layer, owing to present invention employs carborundum or Sapphire Substrate, obvious alloy or chemical reaction can not be there is with already present lower metal electrode in it 850 DEG C time, ensure that the stability of MIM capacitor bottom electrode metal, dielectric layer after densification as shown in Figure 4, the hole of insulating medium layer disappears, structure is finer and close.
7, second time photoetching: object is the fairlead forming MIM lower metal electrode, using non-extension with photoresist as protection mask, as shown in Figure 5.
8, etching insulative dielectric layer: the fairlead forming lower metal electrode.
9, second time removes photoresist: remove clean by the photoresist eroding away the wafer surface of the fairlead of lower metal electrode, as shown in Figure 6.
10, metal sputtering: through the wafer surface large area splash-proofing sputtering metal titanium-Jin of above-mentioned process or Titanium tungsten-Jin; The object of titanium or titanium tungsten layer forms good adhesiveness with the nickel dam of insulating medium layer and lower metal electrode, and the existence of metal is the Seed Layer formed for realizing MIM metal electrode plating thickening, as shown in Figure 7.
11, third time photoetching: form MIM electrode of metal and bottom electrode extraction electrode figure on Seed Layer surface, as shown in Figure 8.
12, electrogilding: to MIM electrode of metal and bottom electrode extraction electrode carry out plating thicken, thickness general control at 1-10 μm, as shown in Figure 9.
13, to remove photoresist and Seed Layer beyond corroding metal top electrode and bottom electrode extraction electrode: the electrode of metal and the bottom electrode extraction electrode that form MIM capacitor, as shown in Figure 10, actual with bottom electrode extraction electrode place below electrode of metal also have Seed Layer, because itself and the electrogilding thickeied are integrated, therefore not marking Seed Layer again in this figure and schematic diagram subsequently, the interior coupling lead-in wire of internally matched device can need according to design the bonding carrying out metal lead wire on this two places metal in the future.
14, four mask: object is the insulating medium layer exposed in dicing lane, for subsequent corrosion is prepared, as shown in figure 11.
15, the insulating medium layer in dicing lane is corroded: by clean for the insulating medium layer corrosion in dicing lane.Object avoids the insulating medium layer in dicing lane to be subject to stress rupture when mechanical scribing, and under high temperature subsequently, stress is expanded, and forms crackle, and stretches to MIM capacitor, to the stability of electric capacity and reliability unfavorable.
16, photoresist is removed the 4th time: removed by the photoresist of the MIM capacitor wafer surface after corrosion clean, as shown in figure 12.
17, back face metalization: object makes electric capacity and base realize good connection, and according to glue technique for sticking, then back side metallization technology can omit.
18, scribing: the MIM capacitor be formed on a wafer is divided into MIM capacitor discrete one by one, as shown in Figure 14 or Figure 15, use shelved by standby follow-up interior mesh power transistor.
Traditional MIM capacitor is generally carry out on silicon or gallium arsenide substrate, because metal and silicon or GaAs material easily alloy reaction occur, so the formation temperature of capacitive insulation dielectric layer generally will, more than 350 DEG C, cause insulating medium layer too loose, unfavorable to the stability of MIM capacitor.The present invention adopts SiC or sapphire as substrate, due to SiC and sapphire stability, the temperature of itself and metal generation significant reaction is generally greater than 900 DEG C, so the stability of MIM capacitor metal electrode of the present invention can be ensured, after deposition insulating layer medium, the high temperature of 800-850 DEG C also can be adopted to carry out densification anneal process to insulating medium layer, avoid the existence of insulating medium layer inside aperture phenomenon, namely insulating medium layer is too loose, avoid metal and insulating medium layer to a certain extent and adhere to phenomenon loosely, thus improve the Stability and dependability of MIM capacitor of the present invention, also the lifting of the microwave property of this electric capacity is conducive to.Due to the raising of insulating medium layer compactness, it also avoid because follow-up sintering, wire bonding apply ultrasonic power equal pressure to the destruction of porous medium layer to capacitive surface, cause occurring the bad phenomenon such as capacitance short-circuit.Improve total rate of finished products of mesh power device tubulature in microwave.
For avoiding scribing to the destruction of insulating medium layer, after capacitance sheet technique completes, invention increases once to the photoetching process of the dielectric layer of dicing lane, object was corroded by the insulating medium layer in dicing lane totally before scribing, thus avoid the damage that scribing cutter stays on dielectric layer, also just avoid this damage and occur Stress Release in the pyroprocesses such as follow-up sintering, cause dielectric layer to occur the phenomenon of crackle, improve stability and the rate of finished products of interior matching capacitance.
Invention further reduces in microwave that matching capacitance is to pure gold consumption, the proof gold layer of about 100 microns can omit, and the substitute is the metallic nickel adopted on carborundum or sapphire, about 3000
, saved the consumption of precious metal significantly, it also avoid the regular maintenance to electroplate liquid, avoided the deficiency of frequent preparation electroplate liquid.
The compactness of capacitive insulation medium of the present invention is owing to have passed through higher Temperature Treatment, and it is better than the compactness directly forming the insulating medium layer of MIM capacitor after the general PECVD of employing forms insulating medium layer.So its microwave property and stability and reliability are higher than traditional MIM capacitor, to shelving substantially by hand at present, sinter, in the microwave of bonding, the lifting of the stability of mesh power transistor, reliability and overall rate of finished products all can have facilitation.
Claims (3)
1. the manufacture method of the effective MIM capacitor of matched crystal in resistant to elevated temperatures microwave, is characterized in that comprising the following steps:
(1) first time photoetching: use the figure making lower metal electrode by lithography at the upper surface of substrate;
(2) evaporation of metal: by silicon to 60 DEG C-80 DEG C, substrate evaporates the nickel of 1000-3000;
(3) peel off unnecessary metal: together got rid of with photoresist by metal on a photoresist, only leave the metal at lower metal electrode place;
(4) insulating medium layer of deposit MIM capacitor: adopt PECVD having substrate surface deposit one deck insulating medium layer of lower metal electrode;
(5) densification anneal process: wafer is heated to 800 DEG C-850 DEG C, carries out annealing in process to it;
(6) second time photoetching: the fairlead forming lower metal electrode, makes with photoresist as protection mask using non-fairlead part;
(7) etching insulative dielectric layer forms the fairlead (9) of lower metal electrode;
(8) second time removes photoresist: remove clean by the photoresist eroding away the wafer surface of lower metal electrode fairlead;
(9) metal sputtering: at upper surface splash-proofing sputtering metal titanium-Jin or Titanium tungsten-Jin formation Seed Layer (10) of the wafer through above-mentioned process;
(10) third time photoetching: the figure forming electrode of metal and bottom electrode extraction electrode on Seed Layer surface;
(11) electrogilding: plating is carried out to electrode of metal and bottom electrode extraction electrode and thickeies, thickness 1 μm-10 μm, remove photoresist;
(12) remove and corrode the Seed Layer beyond clean electrode of metal and bottom electrode extraction electrode, forming electrode of metal and bottom electrode extraction electrode;
(13) four masks: the insulating medium layer in dicing lane is exposed in photoetching, for subsequent corrosion is prepared;
(14) insulating medium layer in dicing lane is corroded: by clean for the insulating medium layer corrosion in dicing lane;
Remove photoresist (15) the 4th times: removed by the photoresist of the MIM capacitor wafer surface after corrosion clean;
(16) scribing: the MIM capacitor be on a wafer is divided into MIM capacitor discrete one by one.
2. the manufacture method of the effective MIM capacitor of matched crystal in a kind of resistant to elevated temperatures microwave according to claim 1, is characterized in that before carrying out first time photoetching, need backing material to clean up.
3. the manufacture method of the effective MIM capacitor of matched crystal in a kind of resistant to elevated temperatures microwave according to claim 1, is characterized in that, after carrying out the 4th time and removing photoresist, needing to carry out back face metalization operation at the bottom surface of substrate.
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CN103545172A (en) * | 2013-10-11 | 2014-01-29 | 中国电子科技集团公司第十三研究所 | Method of preventing medium cracks at cuts of microwave internally-matched capacitors |
CN103904137A (en) * | 2014-03-21 | 2014-07-02 | 中国电子科技集团公司第十三研究所 | Mos capacitor and manufacturing method thereof |
CN104037062B (en) * | 2014-06-11 | 2016-10-05 | 中国电子科技集团公司第十三研究所 | The manufacture method of mos capacitance |
CN105070707B (en) * | 2015-07-16 | 2018-01-02 | 江苏中电振华晶体技术有限公司 | A kind of MIM capacitor and its manufacture method |
CN105280727A (en) * | 2015-11-06 | 2016-01-27 | 中国电子科技集团公司第十三研究所 | Microwave internal matching power transistor matching capacitor and manufacturing method thereof |
TWI707408B (en) * | 2019-04-10 | 2020-10-11 | 力成科技股份有限公司 | Integrated antenna package structure and manufacturing method thereof |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1218293A (en) * | 1997-11-26 | 1999-06-02 | 日本电气株式会社 | Capacitor and method of manufacturing the same |
JP3173451B2 (en) * | 1998-02-25 | 2001-06-04 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
TW494559B (en) * | 2001-06-08 | 2002-07-11 | Taiwan Semiconductor Mfg | Method for producing metal-insulator-metal (MIM) capacitor |
CN1637973A (en) * | 2003-12-30 | 2005-07-13 | E.I.内穆尔杜邦公司 | Thin film capacitors on ceramic |
TW200746387A (en) * | 2005-08-11 | 2007-12-16 | Samsung Electronics Co Ltd | Metal-insulator-metal (MIM) capacitors formed beneath first level metallization and methods of forming same |
CN102113113A (en) * | 2008-08-04 | 2011-06-29 | 株式会社村田制作所 | Manufacturing method of dielectric thin-film capacitor and dielectric thin-film capacitor |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3128925B2 (en) * | 1992-03-02 | 2001-01-29 | 松下電器産業株式会社 | Method of manufacturing capacitive element for semiconductor integrated circuit |
EP0837504A3 (en) * | 1996-08-20 | 1999-01-07 | Ramtron International Corporation | Partially or completely encapsulated ferroelectric device |
JP4226804B2 (en) * | 2001-06-25 | 2009-02-18 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
KR100943484B1 (en) * | 2002-12-31 | 2010-02-22 | 동부일렉트로닉스 주식회사 | Method for fabricating mim capacitor |
US20120113561A1 (en) * | 2010-11-04 | 2012-05-10 | National Chiao Tung University | Capacitor device and method for forming the same |
-
2013
- 2013-04-12 CN CN201310126712.3A patent/CN103219318B/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1218293A (en) * | 1997-11-26 | 1999-06-02 | 日本电气株式会社 | Capacitor and method of manufacturing the same |
JP3173451B2 (en) * | 1998-02-25 | 2001-06-04 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
TW494559B (en) * | 2001-06-08 | 2002-07-11 | Taiwan Semiconductor Mfg | Method for producing metal-insulator-metal (MIM) capacitor |
CN1637973A (en) * | 2003-12-30 | 2005-07-13 | E.I.内穆尔杜邦公司 | Thin film capacitors on ceramic |
TW200746387A (en) * | 2005-08-11 | 2007-12-16 | Samsung Electronics Co Ltd | Metal-insulator-metal (MIM) capacitors formed beneath first level metallization and methods of forming same |
CN102113113A (en) * | 2008-08-04 | 2011-06-29 | 株式会社村田制作所 | Manufacturing method of dielectric thin-film capacitor and dielectric thin-film capacitor |
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