CN102113113A - Manufacturing method of dielectric thin-film capacitor and dielectric thin-film capacitor - Google Patents
Manufacturing method of dielectric thin-film capacitor and dielectric thin-film capacitor Download PDFInfo
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- CN102113113A CN102113113A CN2009801311664A CN200980131166A CN102113113A CN 102113113 A CN102113113 A CN 102113113A CN 2009801311664 A CN2009801311664 A CN 2009801311664A CN 200980131166 A CN200980131166 A CN 200980131166A CN 102113113 A CN102113113 A CN 102113113A
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- 239000003990 capacitor Substances 0.000 title claims abstract description 91
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 31
- 239000010409 thin film Substances 0.000 title abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 58
- 238000000034 method Methods 0.000 claims abstract description 47
- 238000010438 heat treatment Methods 0.000 claims abstract description 29
- 238000009826 distribution Methods 0.000 claims description 81
- 239000012528 membrane Substances 0.000 claims description 56
- 230000004888 barrier function Effects 0.000 claims description 37
- 230000015572 biosynthetic process Effects 0.000 claims description 10
- 239000010410 layer Substances 0.000 description 182
- 239000010408 film Substances 0.000 description 62
- 239000012790 adhesive layer Substances 0.000 description 19
- 238000009413 insulation Methods 0.000 description 19
- 239000012212 insulator Substances 0.000 description 18
- 229920002120 photoresistant polymer Polymers 0.000 description 14
- 229910052751 metal Inorganic materials 0.000 description 12
- 239000002184 metal Substances 0.000 description 12
- 229910052710 silicon Inorganic materials 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 230000033228 biological regulation Effects 0.000 description 8
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 7
- 150000001875 compounds Chemical class 0.000 description 7
- 239000000463 material Substances 0.000 description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 239000011347 resin Substances 0.000 description 6
- 229920005989 resin Polymers 0.000 description 6
- 230000006866 deterioration Effects 0.000 description 5
- 238000003475 lamination Methods 0.000 description 5
- 238000004544 sputter deposition Methods 0.000 description 5
- 229910052786 argon Inorganic materials 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000005496 eutectics Effects 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 238000000992 sputter etching Methods 0.000 description 3
- 229910002367 SrTiO Inorganic materials 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 229910052788 barium Inorganic materials 0.000 description 2
- 229910052797 bismuth Inorganic materials 0.000 description 2
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 2
- 238000000224 chemical solution deposition Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 238000004090 dissolution Methods 0.000 description 2
- 238000001755 magnetron sputter deposition Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910052726 zirconium Inorganic materials 0.000 description 2
- 229910018487 Ni—Cr Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- -1 argon ion Chemical class 0.000 description 1
- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 description 1
- 229910002113 barium titanate Inorganic materials 0.000 description 1
- 238000005266 casting Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 238000010023 transfer printing Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/01—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate
- H01L27/016—Thin-film circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/224—Housing; Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/228—Terminals
- H01G4/236—Terminals leading through the housing, i.e. lead-through
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/33—Thin- or thick-film capacitors
Abstract
Disclosed is a manufacturing method of a dielectric thin-film capacitor which forms an upper external electrode (15) on one main surface of a conductive substrate (1) and forms a lower external electrode (17) on the other main surface of the conductive substrate (1). The method includes a capacitor forming process which forms a capacitor (4), which is formed from first and second electrode layers (5, 7) on both the top and bottom surfaces of a dielectric layer (6), on one main surface of the conductive substrate (1); and a wire forming process which forms substrate wires (11) which electrically connect the first electrode layer (5) to the conductive substrate (1); and includes a heat treatment process for heat treating the capacitor (4) between the capacitor forming process and the wire forming process. Thus, a dielectric thin-film capacitor which can suppress an increase in the equivalent series resistance (ESR) without a loss in reliability is implemented.
Description
Technical field
The present invention relates to the manufacture method and the thin dielectric membrane capacitance of thin dielectric membrane capacitance, relate to the manufacture method of the thin dielectric membrane capacitance that is formed with outer electrode in the both sides of the interarea of conductive board and the thin dielectric membrane capacitance that uses this manufacture method to produce in more detail.
Background technology
From in the past, in this thin dielectric membrane capacitance, the oxide that barium titanate etc. have a perovskite structure is used for the dielectric portion of capacitor more.
For example, in patent documentation 1, following thin-film capacitor (thin dielectric membrane capacitance) has been proposed: as shown in figure 12, face and conductive film covering 102 ohmic contact with low-resistance silicon substrate 101, in another face, according to the anti-eutectic film 104 of centre across the predetermined pattern that prevents the 1st metal electrode 103 and above-mentioned silicon substrate 101 generation eutectics, and the part of the 1st metal electrode 103 and above-mentioned silicon substrate 101 ways of connecting are covered and form the 1st metal electrode 103 that the insulant with metatitanic acid system has lattice constant about equally, lining forms the dielectric film 105 of metatitanic acid system on the 1st metal electrode 103, and lining forms the 2nd metal electrode 106 on this dielectric film 105.
The 1st metal electrode 103 and the 2nd metal electrode 106 are by Cr layer 103a and 106a, Pt layer 103b and 106b and Au layer 103c and this three-layer structure formation of 106c, and dielectric film 105 is suitable with the dielectric portion of capacitor.
In this patent documentation 1, to be its patterns compare that the earth forms and the structure that contacts with silicon substrate 101 with anti-eutectic film 104 to the 1st metal electrode 103, when under 500～600 ℃ insulating barrier 105 being carried out sputter, eutectics take place and ohmic contact with silicon substrate 101 in the 1st metal electrode 103.
Patent documentation 1: Japanese kokai publication sho 56-83917 communique
Yet, in this thin dielectric membrane capacitance, usually after waiting and deposited film, improve the crystallinity of thin dielectric film by heat treatment with sputtering method, CVD method, realize the raising of dielectric property thus.
Yet, be formed with the thin-film capacitor of conductive film covering 102 as the lower surface shown in patent documentation 1 at silicon substrate 101, form under the situation of electrode in the both sides of silicon substrate 101, eutectic part and silicon can be oxidized when heat-treating, therefore might the 1st metal electrode 103 become greatly with contact resistance between the silicon substrate 101 and the equivalent series resistance of capacitor (below, be called " ESR ".) increase.
On the other hand, considered to make the thickness thickening of the 1st metal electrode 103 in order to reduce contact resistance, but the surperficial roughening of the 1st metal electrode 103 in this case, and its result might cause the deterioration of capacitor specific characteristics.
Summary of the invention
The present invention In view of the foregoing finishes, even purpose is to provide and has carried out heat treatment and also do not lose manufacture method and the thin dielectric membrane capacitance of thin dielectric membrane capacitance that reliability just can suppress the increase of ESR.
In order to achieve the above object, the manufacture method of thin dielectric membrane capacitance involved in the present invention is that an interarea side at conductive board is formed with at least one the 1st outer electrode, be formed with the manufacture method of the thin dielectric membrane capacitance of the 2nd outer electrode in another interarea side of above-mentioned conductive board, the manufacture method of above-mentioned thin dielectric membrane capacitance is characterised in that: have: capacitor department forms operation, will have at least more than one the capacitor department of electric capacity generating unit that upper and lower surface at dielectric layer is formed with electrode layer and be formed on the above-mentioned interarea of above-mentioned conductive board; Form operation with distribution, the electrode layer that will become a utmost point in the above-mentioned electrode layer and above-mentioned conductive board be electrically connected to fetch forms the substrate distribution, comprises the heat treatment step that above-mentioned capacitor department is heat-treated between above-mentioned capacitor forms operation and above-mentioned distribution formation operation.
In addition, the manufacture method of thin dielectric membrane capacitance of the present invention is characterised in that: form at above-mentioned heat treatment step and above-mentioned distribution and have the insulating barrier that coats above-mentioned capacitor department with insulating barrier between the operation and form operation, at least one portion of aforesaid substrate distribution is formed on the above-mentioned insulating barrier.
In addition, the manufacture method of thin dielectric membrane capacitance of the present invention is characterised in that: have the film resistor that forms the film resistor that is electrically connected with above-mentioned capacitor department and form operation between above-mentioned heat treatment step and above-mentioned distribution formation operation.
And the manufacture method of thin dielectric membrane capacitance of the present invention is characterised in that: form in the operation at above-mentioned film resistor, flat condition ground forms above-mentioned film resistor.
In addition, thin dielectric membrane capacitance involved in the present invention is that an interarea side at conductive board is formed with at least one the 1st outer electrode, and be formed with the thin dielectric membrane capacitance of the 2nd outer electrode in another interarea side of above-mentioned conductive board, above-mentioned thin dielectric membrane capacitance is characterised in that: will possess at least more than one the capacitor department of electric capacity generating unit that upper and lower surface at dielectric layer has electrode layer and be formed on the above-mentioned interarea of above-mentioned conductive board, and the electrode layer that will become a utmost point in the above-mentioned electrode layer is electrically connected with above-mentioned the 2nd outer electrode via substrate distribution and above-mentioned conductive board, and, the electrode layer that becomes another utmost point is electrically connected with above-mentioned the 1st outer electrode, above-mentioned capacitor department has been carried out heat treatment, and the aforesaid substrate distribution forms after above-mentioned heat treatment at least.
In addition, thin dielectric membrane capacitance of the present invention is characterised in that: above-mentioned capacitor department is insulated layer and coats, and at least a portion of aforesaid substrate distribution is formed on the above-mentioned insulating barrier.
And thin dielectric membrane capacitance of the present invention is characterised in that: film resistor forms with the electrode layer that will become above-mentioned another utmost point and is electrically connected.
In addition, thin dielectric membrane capacitance of the present invention is characterised in that: above-mentioned film resistor is formed on the capacitor department.
In addition, thin dielectric membrane capacitance of the present invention is characterised in that: film resistor flat condition ground forms.
According to the manufacture method and the film capacitor of above-mentioned thin dielectric membrane capacitance, capacitor department is being carried out after the heat treatment forming the substrate distribution, so the substrate distribution can not be exposed in the heat treatment environment and oxidized.Therefore, even carried out the reliability that heat treatment also can not be lost capacitor department, can suppress the increase of ESR.
In addition, the electrode layer that will become a utmost point directly is not electrically connected with conductive board, connect and make them pass through the substrate wired electric, therefore can make the substrate distribution become thick fully, perhaps the substrate distribution is used low-resistance conductive materials such as Au, Cu, can reduce fully thus from the resistance between electrode layer to the 2 outer electrodes that will become an above-mentioned utmost point.That is, can access the thin dielectric membrane capacitance of the big and high power capacity of the degree of freedom of adjustment of selected, length of material, shape of distribution, high reliability, low ESR.
In addition, before forming the substrate distribution, coat capacitor department, therefore can prevent the deterioration of the capacitor specific characteristics that the etching when distribution forms causes with insulating barrier.
In addition, capacitor constructions is added film resistor, therefore can access high power capacity, the high reliability that has possessed the resistance function, the thin dielectric membrane capacitance that hangs down ESR.
In addition, film resistor is formed on the capacitor department, even therefore possessing the maximization that also can avoid element under the situation of film resistor as much as possible.
In addition, film resistor is formed flat condition, the resistance value that therefore can suppress film resistor produces inhomogeneous.
Description of drawings
Fig. 1 is the cutaway view of an execution mode (the 1st execution mode) of the thin dielectric membrane capacitance that produces with manufacture method of the present invention of expression.
Fig. 2 is the cutaway view (1/3) of manufacturing process of an execution mode of the manufacture method of expression thin dielectric membrane capacitance involved in the present invention.
Fig. 3 is the cutaway view (2/3) of manufacturing process of an execution mode of the manufacture method of expression thin dielectric membrane capacitance involved in the present invention.
Fig. 4 is the cutaway view (3/3) of manufacturing process of an execution mode of the manufacture method of expression thin dielectric membrane capacitance involved in the present invention.
Fig. 5 is the cutaway view of expression the 2nd execution mode of the present invention.
Fig. 6 is the cutaway view of expression the 3rd execution mode of the present invention.
Fig. 7 is the cutaway view of expression the 4th execution mode of the present invention.
Fig. 8 is the cutaway view of wanting portion (1/2) of the manufacturing process of expression the 4th execution mode.
Fig. 9 is the cutaway view of wanting portion (2/2) of the manufacturing process of expression the 4th execution mode.
Figure 10 is the cutaway view of expression the 5th execution mode of the present invention.
Figure 11 is the cutaway view of expression the 6th execution mode of the present invention.
Figure 12 is the cutaway view of the conventional example put down in writing of patent documentation 1.
Embodiment
Below, describe embodiments of the present invention in detail based on Figure of description.
Fig. 1 is the cutaway view of an execution mode (the 1st execution mode) of the thin dielectric membrane capacitance that produces with manufacture method of the present invention of expression.
That is, in this thin dielectric membrane capacitance, an interarea at the conductive board 1 that is formed by semiconductors such as Si is formed with by SiO
2Deng the barrier layer 2 that constitutes, and be formed with adhesive layer 3 on the surface of this barrier layer 2, and, be formed with capacitor department 4 on the surface of this adhesive layer 3.Above-mentioned barrier layer 2 has and prevents Elements Diffusion that conductive board 1 the contained function to capacitor department 4.
In addition, concerning the 1st and the 2nd electrode layer 5,7, as described later, capacitor department 4 is that preferably heat treatment forms under the environment of oxygen element containing, the therefore preferred material that uses Pt, Au, Ru etc. that heat treatment is had oxidative resistance.In addition, adhesive layer 3 can use and the material of dielectric layer 6 same compositions system or the material of same composition.
In addition, organic insulator 10 is formed by polyimide resin, epoxy resin, absorbs the mechanical stress from electrode distribution described later, substrate distribution.
The 1st electrode layer 5 is connected with substrate distribution 11, and the 2nd electrode layer 7 is connected with electrode distribution 12.
Particularly, substrate distribution 11 connects insulating barrier 8 (inorganic insulation layer 9 and organic insulator 1) from the upper surface of the 1st electrode layer 5, be set to the side of insulating barrier 8 from the organic insulator 10 continuously, be electrically connected with the 1st connection electrode 14 of ohmic contact on conductive board 1.
In addition, electrode distribution 12 forms from the upper surface of the 2nd electrode layer 7 and connects insulating barrier 8 (inorganic insulation layer 9 and organic insulator 1) and be configured on the organic insulator 10.
And, be electrically connected with upper external electrode 15 by electrode distribution 12 at upper surface formation upper external electrode (the 1st outer electrode) 15, the 2 electrode layers 7 of above-mentioned electrode distribution 12.
In addition, the part except upper external electrode 15 of a side on conductive board 1, protected resin 18 coats.
And, on another interarea of conductive board 1, form the 2nd connection electrode 16, on the 2nd connection electrode 16, form bottom outer electrode (the 2nd outer electrode) 17.
In addition, the 1st and the 2nd connection electrode 14,16 need reduce ESR with conductive board 1 ohmic contact, is therefore preferably formed by Au.
In addition, upper external electrode 15 and preferably multi-ply construction of bottom outer electrode 17 can be used for example Au/Cu, Au/Ni, Sn/Cu.
Like this, concerning this thin dielectric membrane capacitance, bottom outer electrode 17 is electrically connected with the 1st electrode layer 5 via the 2nd connection electrode 16, conductive board the 1, the 1st connection electrode 14, substrate distribution 11, and upper external electrode 15 is electrically connected with the 2nd electrode layer 7 via electrode distribution 12.And when applying voltage between to upper external electrode 15 and bottom outer electrode 17, capacitor department 4 performances are as the function of capacitor.
Below, be described in detail the manufacture method of thin dielectric membrane capacitance.
At first, shown in Fig. 2 (a), prepare thickness for example and be the conductive board 1 that constitutes by p type conductivity Si substrate etc. of 525 μ m.
Then, shown in Fig. 2 (b), make barrier layer 2 and adhesive layer 3 film forming in order.
That is, by for example thermal oxidation method make thickness be 700nm by SiO
2Deng barrier layer 2 film forming that constitute.
Then, (Chemical Solution Deposition is called " CSD " below to utilize chemical solution deposition.) method etc., for example forming on barrier layer 2, thickness is the adhesive layer 3 of 100nm.As adhesive layer 3, can use BST, SrTiO
3, BaTiO
3, Pb (Zr, Ti) O
3Deng perovskite compound, SrBi
4Ti
4O
15Deng bismuth layer-like compound etc., but for example forming under the situation of adhesive layer 3, can make as follows by BST.
That is, at first, prepare Ba, Sr, Ti and be mol ratio and be for example Ba: Sr: Ti=7: cooperate the film forming material solution that forms at 3: 10.Then, this film forming material solution is coated on the barrier layer 2, makes it dry on 300～400 ℃ heating plate, the high speed intensification heat treatment of carrying out under 650 ℃ temperature 30 minutes makes it crystallization, forms adhesive layer 3 thus.
Then, shown in Fig. 2 (c), make the 1st electrode layer 5, dielectric layer 6 and the 2nd electrode layer 7 film forming in order.
Promptly, wait by for example RF magnetron sputtering method and to form the 1st electrode layer 5 that constitutes by Pt that thickness is 200nm, then same with adhesive layer 3, is the dielectric layer 6 of 100nm by formation such as CSD methods by the thickness that BST etc. constitutes, same with the 1st electrode layer 5 afterwards, be the 2nd electrode layer 6 that constitutes by Pt of 200nm by formation thickness such as RF magnetron sputtering methods.
Then, shown in Fig. 2 (d), use known photoetching technique and argon ion etching method to wait above-mentioned adhesive layer the 3, the 1st electrode layer 5, dielectric layer 6 and the 2nd electrode layer 7 are etched into predetermined pattern, form capacitor department 4.That is, carried out across photomask ultraviolet lighting being mapped to photoresist after the prebake applying photoresist, exposed, develop, the back dries by the fire the optical mask pattern transfer printing is become the resist pattern.Then, by the argon ion etching method argon ion is struck etching face and come etching is carried out in the regulation zone of the 2nd electrode layer 7, dielectric layer the 6, the 1st electrode layer 5 and adhesive layer 3, produce capacitor department 4 thus.
Then, capacitor department 4 is heat-treated, improve the dielectric property of dielectric layer 6.This heat treatment is carried out for the crystallinity that improves dielectric layer 6, is for example carrying out 30 minutes heat treatment under 850 ℃ the temperature.In addition, if oxygen defect is many in the dielectric layer 6, the voltage loads in the time of then might non-refractory, thus reliability reduces, and therefore preferably heat-treats in containing the environment of aerobic.
Then, shown in Fig. 3 (e), form the insulating barrier 8 that constitutes by inorganic insulation layer 9 and organic insulator 10 in the mode of covering capacitor portion 4 integral body.That is, by for example sputtering method make thickness be 500nm by SiN
xDeng inorganic insulation layer 9 film forming that constitute.Then, mode with the upper surface that covers above-mentioned inorganic insulation layer 9 applies photosensitive polyimide, under 125 ℃ temperature, heated 5 minutes afterwards, and expose, development treatment, heated about 1 hour down at 350 ℃ afterwards, for example forming, thickness is the organic insulator 10 of the predetermined pattern of 5000nm.
Then, shown in Fig. 3 (f), the organic insulator 10 that will be made of photosensitive polyimide forms hole 19,20 as mask by reactive ion-etching processing inorganic insulation layer 9, makes a part of exposing surface of the 1st and the 2nd electrode layer 5,7.
Then, behind the resist pattern that has formed regulation,, make a part of exposing surface of conductive board 1 with there being the resiliency hydrofluoric acid dissolution to remove the part of barrier layer 2.
Afterwards, by vacuum vapour deposition to the surperficial exposed portions serve evaporation of conductive board 1 for example thickness be the Au of 300nm, remove photoresist by peeling off (lift-off) method, shown in Fig. 3 (g), form the 1st connection electrode 14.
Then, shown in Fig. 4 (h), be layered on the upper surface of organic insulator 10 and side and then the 1st connection electrode 14 from the inner face in hole 20 and form substrate distribution 11,19 inner face forms electrode distribution 12 to the upper surface of organic insulator 10 from the hole.And form upper external electrode 15 on the top of this electrode distribution 12 afterwards.
Particularly, these substrate distributions 11, electrode distribution 12 and upper external electrode 15 are made in the following manner.
That is, at first, by sputtering method make thickness be the Ti layer of 100nm at surface filming, making thickness on this Ti layer is the Cu layer film forming of 500nm.Then, according to the mode that on the Cu layer, has peristome, apply the resist pattern that photoresist forms regulation on this Cu layer, then carry out metallide, forming Ni layer and the thickness that thickness is 2000nm in order at above-mentioned peristome is the Au layer of 1000nm.Then, remove the upper external electrode 15 that above-mentioned photoresist forms two layers of structure that are made of Au layer and Ni layer.
Then, the mode of separating with the position that will become substrate distribution 11 according to the position that will become electrode distribution 12 applies the resist pattern that photoresist forms regulation on the Cu layer once more, then comes etching Cu layer and Ti layer by wet etching.And afterwards, remove photoresist, form the electrode distribution 12 and the substrate distribution 11 of two layers of structure that constitute by Cu layer and Ti layer.
Then, shown in Fig. 4 (i), with the part on the protection resin bed 18 coating conducting substrates 1 except upper external electrode 15.
Promptly; above photoresists such as photosensitive polyimide were coated in, heating 5 minutes under 125 ℃ temperature afterwards exposed, development treatment; heated about 1 hour down at 350 ℃ afterwards, for example forming, thickness is the protection resin bed 18 of the predetermined pattern of 5000nm.
Then, shown in Fig. 4 (j), on another interarea of conductive board 1, form the 2nd connection electrode 16, on the 2nd connection electrode 16, form bottom outer electrode 17.
That is, at first, the thickness that is whittled into regulation is ground at the back side of conductive board 1, and it is handled, form the 2nd connection electrode 16 that constitutes by Au that thickness is 300nm by vacuum vapour deposition with the hydrofluoric acid that resiliency is arranged.Then, carry out metallide, making thickness is the Ni layer of 2000nm and Au layer that thickness is 1000nm film forming in order, forms the bottom outer electrode 17 of two layers of structure thus.
At last, under 350 ℃ temperature, heat-treat, make the interface stabilityization of bottom outer electrode 17 and conductive board 1, obtain the thin dielectric membrane capacitance thus in order to obtain more reliable ohmic contact.
Like this, in this 1st execution mode, capacitor department 4 is being carried out form substrate distribution 11 after the heat treatment, so substrate distribution 11 can not be exposed in the heat treatment environment and oxidized yet.Even therefore carried out the reliability that heat treatment also can not be lost capacitor department 4, can suppress the increase of ESR.
In addition, the 2nd electrode layer 7 is electrically connected with conductive board 1, and they are electrically connected via substrate distribution 11, therefore can make substrate distribution 11 become thick fully, perhaps substrate distribution 11 is used low-resistance conductive materials such as Au, Cu, can reduce fully from the resistance above-mentioned the 2nd electrode layer 7 to the 2nd outer electrodes 17.That is, can access the thin dielectric membrane capacitance of the big high capacitance of the degree of freedom of adjustment of selected, length of material, shape of distribution, high reliability, low ESR.
In addition, before forming substrate distribution 11, coat capacitor department 4, therefore can prevent the deterioration of the capacitor specific characteristics that the etching when distribution forms causes with insulating barrier 8.
Fig. 5 is the cutaway view of the thin dielectric membrane capacitance of expression the 2nd execution mode of the present invention, concerning the 2nd execution mode, an interarea side at conductive board 1 is formed with 2 capacitor department 21a, 21b, and in each capacitor department 21a, 21b, electrode layer and dielectric layer be lamination alternately, has a plurality of electric capacity generating units.
That is, on the barrier layer 2 that is formed on the conductive board 1, clip inorganic insulation layer 22 ground and form 2 adhesive layer 23a, 23b.And, lamination the 1st electrode layer 24a and 24b, the 1st dielectric layer 25a and 25b, the 2nd electrode layer 26a and 26b, the 2nd dielectric layer 27a and 27b, the 3rd electrode layer 28a and 28b, the 3rd dielectric layer 29a and 29b and the 4th electrode layer 30a and 30b in order on each adhesive layer 23a, 23b, thus capacitor department 21a, 21b formed.Then, on the 4th electrode layer 30a of the superiors of capacitor department 21a, 21b, the surface of 30b, be formed with the 4th dielectric layer 31a, 31b.In addition, inorganic insulation layer 22 is coated by organic insulator 32.
In addition, substrate distribution 33a, 33b and electrode distribution 35a, 35b forms and the 1st execution mode has roughly same shape, and substrate distribution 33a, 33b is electrically connected to and the 1st connection electrode 34a, the 34b of conductive board 1 ohmic contact.
And, the 1st electrode layer 24a, 24b are electrically connected with bottom outer electrode 17 via substrate distribution 33a and 33b, the 1st connection electrode 34a and 34b, conductive board 1 and the 2nd connection electrode 16, and the 4th electrode layer 30a, 30b are electrically connected with upper external electrode 36a, 36b via electrode distribution 35a, 35b.In addition, concerning this thin dielectric membrane capacitance, coat at the capacitor department 21a of conductive board 1, the whole protected resin bed except upper external electrode 36a, 36b 37 of 21b side.
And, in this 2nd execution mode, also be before forming substrate distribution 33a, 33b, carry out the heat treatment of capacitor department 21a, 21b, can not lose the reliability of capacitor department thus, and suppress the increase of ESR.
And in this 2nd execution mode, capacitor department 21a, 21b have a plurality of electric capacity generating units, the film capacitor of the proof voltage that therefore can be improved.In addition, the 4th dielectric layer 31a, 31b are formed on capacitor department 21a, the 21b, the deterioration of capacitor can suppress leakage current in the time of therefore can preventing inorganic insulation layer 22 film forming.
Fig. 6 is the cutaway view of the thin dielectric membrane capacitance of expression the 3rd execution mode of the present invention, in this 3rd execution mode, on the barrier layer 2 that is formed on the conductive board 1, form adhesive layer the 23, the 1st electrode layer 24 and the 1st dielectric layer 25 in order, on the 1st dielectric layer 25, replace long-pending electrode layer in stratum and dielectric layer and form capacitor department.
Promptly, on above-mentioned the 1st dielectric layer 25,, form capacitor department with these the 1st～the 4th dielectric layers 25,27a, 27b, 29a, 29b and the 1st electrode layer 24,26a, 26b, 28a, 28b, 30a, 30b across inorganic insulation layer 22 lamination the 2nd electrode layer 26a and 26b, the 2nd dielectric layer 27a and 27b, the 3rd electrode layer 28a and 28b, the 3rd dielectric layer 29a and 29b and the 4th electrode layer 30a and 30b in order.
And, in this 3rd execution mode, also be before forming substrate distribution 33a, 33b, carry out the heat treatment of capacitor department, can not lose the reliability of capacitor department thus, and suppress the increase of ESR.
And, also same in this 3rd execution mode with the 2nd execution mode, possess capacitor department with a plurality of electric capacity generating units, therefore can form the film capacitor that has improved proof voltage.In addition, the 4th dielectric layer 31a, 31b are formed on the capacitor department, the deterioration of capacitor can suppress leakage current in the time of therefore can preventing inorganic insulation layer 22 film forming.
And, in the above-mentioned the 2nd and the 3rd execution mode, except the formation pattern of the lamination number of suitably adjusting dielectric layer, electrode layer and dielectric layer, electrode layer, electrode distribution, substrate distribution, also can similarly make with the 1st execution mode.
Fig. 7 is the cutaway view of the thin dielectric membrane capacitance of expression the 4th execution mode of the present invention, in this 4th execution mode, flat condition ground forms film resistor 42 on organic insulator 10, and the 2nd electrode layer 7 is electrically connected with film resistor 42 via electrode distribution 12.And electrode distribution 12 is held a concurrent post the upper external electrode, and film resistor 42 is electrically connected with another upper external electrode 41.
That is, the 4th execution mode and the 1st execution mode are same, are formed with by SiO on an interarea of conductive board 1
2Deng the barrier layer 2 that constitutes, and be formed with adhesive layer 3 on the surface of this barrier layer 2, and be formed with the capacitor department 4 that constitutes by the 1st electrode layer 5, dielectric layer 6 and the 2nd electrode layer 7 on the surface of this adhesive layer 3.
In addition, capacitor department 4 and the 1st execution mode are same, and the insulating barrier 8 that is made of inorganic insulation layer 9 and organic insulator 10 coats.
In addition, substrate distribution 11 and electrode distribution 12 also form the shape roughly same with the 1st execution mode, and the 1st electrode layer 5 is connected with substrate distribution 11, and the 2nd electrode layer 7 is connected with electrode distribution 12.Wherein, in the 4th execution mode, electrode distribution 12 is held a concurrent post the upper external electrode as mentioned above like that.
And, on the surface of organic insulator 10, being formed with another upper external electrode 41, this upper external electrode 41 is electrically connected via film resistor 42 with electrode distribution 12.
And conductive board 1 is except the part of electrode distribution 12 and upper external electrode 41, and whole protected resin bed 43 coats.
Below, describe the manufacture method of above-mentioned the 4th execution mode in detail based on Fig. 8 and Fig. 9.
At first, same with the 1st execution mode, on conductive board 1, form barrier layer 2, adhesive layer the 3, the 1st electrode layer 5, dielectric layer 6 and the 2nd electrode layer 7 in order, use known photoetching technique and argon ion etching method to wait and be etched into predetermined pattern, form capacitor department 4.And, in containing the environment of oxygen element, capacitor department 4 is heat-treated for the dielectric property that improves dielectric layer 6.Then, form the insulating barrier 8 that constitutes by inorganic insulation layer 9, organic insulator 10, inorganic insulation layer 9 is processed by reactive ion-etching according to the mode that coats capacitor department 4.Then, shown in Fig. 8 (a), form hole 19,20, make a part of exposing surface of the 1st and the 2nd electrode layer 5,7.
Then, shown in Fig. 8 (b), making thickness by sputtering method is the thin layer film forming that is made of TaN, Ni-Cr alloy of 40～60nm.Then, after the coating photoresist forms the resist pattern of regulation, come etching to remove the regulation zone by reactive ion etching, form film resistor 42, photoresist is removed in dissolving afterwards.
Then, apply once more after photoresist forms the resist pattern of regulation,, make a part of exposing surface of conductive board 1 with the part that the hydrofluoric acid dissolution that resiliency is arranged is removed barrier layer 2.
Afterwards,, remove photoresist, shown in Fig. 8 (c), form the 1st connection electrode 14 by peeling off method making after for example thickness is the Au film forming of 300nm in the surperficial exposed portions serve of conductive board 1 by vacuum vapour deposition.
Then, making thickness by sputtering method is the Ti layer of 100nm and the Au layer film forming that thickness is 500nm, then, apply photoresist and form the resist pattern, after by wet etching Au layer and Ti layer being processed, remove photoresist, thus, shown in Fig. 9 (d), form substrate distribution 11, electrode distribution 12 and upper external electrode 41.Afterwards, in air, under 370 ℃, carry out 30 minutes heat treatment, make film resistor 42 oxidations carry out stabilization processes.
Afterwards, by with the same method of the 1st execution mode, in proper order, shown in Fig. 9 (e), be overmolding to the integral body of covering except upper external electrode 41 and electrode distribution 12 with protection resin bed 43.
Then, use the method same, in proper order, shown in Fig. 9 (f), on another interarea of conductive board 1, form the 2nd connection electrode 16, on the 2nd connection electrode 16, form bottom outer electrode 17 with the 1st execution mode.
Like this, in this 4th execution mode, except the action effect of the 1st execution mode, can realize the high power capacity of resistance function compound by adding film resistor 42, the film capacitor of high reliability, low ESR.
In addition, film resistor is formed on the capacitor department 4, therefore can avoids causing the maximization of element as much as possible.
In addition, film resistor 42 is formed flat condition, therefore can suppress resistance value and produce inhomogeneous.
Figure 10 is the cutaway view of the thin dielectric membrane capacitance of expression the 5th execution mode.
That is, in the 5th execution mode, form film resistor 46 on barrier layer 2, electrode distribution 47 is electrically connected with above-mentioned film resistor 46 on the face of barrier layer 2 with upper external electrode 45.
Shown in the 5th execution mode, even under the situation that has formed film resistor 46 on the barrier layer 2, except the action effect of the 1st execution mode, can also realize the high power capacity of resistance function compound by adding film resistor 46, the film capacitor of high reliability, low ESR.
In addition, same with the 4th execution mode, film resistor 46 is formed flat condition, therefore can suppress resistance value and produce inhomogeneous.
Figure 11 is the cutaway view of the thin dielectric membrane capacitance of expression the 6th execution mode.
In this 6th execution mode, capacitor department has the structure roughly same with the 3rd execution mode.
That is, on the barrier layer 2 that is formed on the conductive board 1, form adhesive layer the 48, the 1st electrode layer 49 and the 1st dielectric layer 50 in order, on the 1st dielectric layer 50, replace long-pending electrode layer in stratum and dielectric layer and form capacitor department.
Promptly, on above-mentioned the 1st dielectric layer 50, clip inorganic insulation layer 51 ground lamination the 2nd electrode layer 52a and 52b, the 2nd dielectric layer 53a and 53b, the 3rd electrode layer 54a and 54b, the 3rd dielectric layer 55a and 55b and the 4th electrode layer 56a and 56b, the 4th dielectric layer 57a and 57b and the 5th electrode layer 58a and 58b in order, form capacitor department with these the 1st～the 4th dielectric layers 50,53a, 53b, 55a, 55b, 57a, 57b and the 1st～the 5th electrode layer 49,52a, 52b, 54a, 54b, 56a, 56b, 58a, 58b.Then, on the 5th electrode layer 58a and 58b, form the 5th dielectric layer 59a, 59b, and the top of inorganic insulation layer 51 coated by organic insulator 60.
And, substrate distribution 61 and electrode distribution 62,63 adopt and the roughly same shape of the 4th execution mode, and the 1st electrode layer 49 is connected with the 1st connection electrode 14 via substrate distribution 11, and the 5th electrode layer 58a, 58b is electrically connected respectively with the electrode distribution 63,62 of holding a concurrent post the upper external electrode.
And, on organic insulator 60, form film resistor 64, to this film resistor 64 electrode electrically connected distributions 63 and upper external electrode 65, the 5th electrode layer 58 is electrically connected with upper external electrode 65 via electrode distribution 63 and film resistor 64 thus.
Like this, in this 6th execution mode, except the action effect of the 1st execution mode, can also realize the high power capacity of resistance function compound by adding film resistor 64, the film capacitor of high reliability, low ESR.
In addition, film resistor 64 is formed on the capacitor department, therefore can avoids causing the maximization of element as much as possible.
In addition, film resistor 64 is formed flat condition, therefore can suppress resistance value and produce inhomogeneous.
In addition, the invention is not restricted to above-mentioned execution mode.In the present invention, aforesaid various variation can be arranged, still described in the respective embodiments described above film build method, membrance casting condition, thickness etc. are exemplary, are not limited to these methods, condition, thickness.In addition, not ccontaining doubt made under a plurality of situations uniformly, also can by cutting wait be divided into single.
Even have the thin dielectric membrane capacitance of outer electrode in the both sides of conductive board, can not lose reliability as capacitor yet, can suppress the increase of ESR.
The Reference numeral explanation
1: the electric conductivity substrate; 4,21a, 21b: capacitor section; 5,7: electrode layer; 6: dielectric layer; 8: insulating barrier; 11,33,61: the substrate distribution; 12,47,62,63: electrode wiring; 15,41,45: top outer electrode (the 1st outer electrode); 17: bottom outer electrode (the 2nd outer electrode); 24,26,28,30: electrode layer; 25,27,29: dielectric layer; 42,46,64: film resistor; 49,52,54,56,58: electrode layer; 50,53,55,57,59: dielectric layer.
Claims (9)
1. the manufacture method of a thin dielectric membrane capacitance, described thin dielectric membrane capacitance is formed with at least one the 1st outer electrode in an interarea side of conductive board, another interarea side at above-mentioned conductive board is formed with the 2nd outer electrode, and the manufacture method of above-mentioned thin dielectric membrane capacitance is characterised in that:
Have:
Capacitor department forms operation, will have at least more than one the capacitor department of electric capacity generating unit that upper and lower surface at dielectric layer is formed with electrode layer and be formed on the above-mentioned interarea of above-mentioned conductive board; With
Distribution forms operation, forms the substrate distribution that the electrode layer that will become a utmost point in the above-mentioned electrode layer is electrically connected with above-mentioned conductive board,
Between above-mentioned capacitor formation operation and above-mentioned distribution formation operation, comprise the heat treatment step that above-mentioned capacitor department is heat-treated.
2. the manufacture method of thin dielectric membrane capacitance according to claim 1 is characterized in that:
Form at above-mentioned heat treatment step and above-mentioned distribution and to have the insulating barrier that coats above-mentioned capacitor department with insulating barrier between the operation and form operation, at least a portion of aforesaid substrate distribution is formed on the above-mentioned insulating barrier.
3. according to the manufacture method of claim 1 or the described thin dielectric membrane capacitance of claim 2, it is characterized in that:
Between above-mentioned heat treatment step and above-mentioned distribution formation operation, have the film resistor that forms the film resistor that is electrically connected with above-mentioned capacitor department and form operation.
4. the manufacture method of thin dielectric membrane capacitance according to claim 3 is characterized in that:
Form in the operation at above-mentioned film resistor, flat condition ground forms above-mentioned film resistor.
5. thin dielectric membrane capacitance is formed with at least one the 1st outer electrode in an interarea side of conductive board, and is formed with the 2nd outer electrode in another interarea side of above-mentioned conductive board, and above-mentioned thin dielectric membrane capacitance is characterised in that:
To possess at least more than one the capacitor department of electric capacity generating unit that upper and lower surface at dielectric layer has electrode layer and be formed on the above-mentioned interarea of above-mentioned conductive board, and
The electrode layer that will become a utmost point in the above-mentioned electrode layer is electrically connected with above-mentioned the 2nd outer electrode via substrate distribution and above-mentioned conductive board, and the electrode layer that will become another utmost point is electrically connected with above-mentioned the 1st outer electrode,
Above-mentioned capacitor department has been carried out heat treatment, and the aforesaid substrate distribution forms after above-mentioned heat treatment at least.
6. thin dielectric membrane capacitance according to claim 5 is characterized in that:
Above-mentioned capacitor department is insulated layer and coats, and at least a portion of aforesaid substrate distribution is formed on the above-mentioned insulating barrier.
7. according to claim 5 or the described thin dielectric membrane capacitance of claim 6, it is characterized in that:
Film resistor forms with the electrode layer that will become above-mentioned another utmost point and is electrically connected.
8. thin dielectric membrane capacitance according to claim 7 is characterized in that:
Above-mentioned film resistor is formed on the capacitor department.
9. according to claim 7 or the described thin dielectric membrane capacitance of claim 8, it is characterized in that:
Above-mentioned film resistor flat condition ground forms.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2008-200958 | 2008-08-04 | ||
| JP2008200958 | 2008-08-04 | ||
| PCT/JP2009/002090 WO2010016171A1 (en) | 2008-08-04 | 2009-05-13 | Manufacturing method of dielectric thin-film capacitor and dielectric thin-film capacitor |
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| CN102113113A true CN102113113A (en) | 2011-06-29 |
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| CN2009801311664A Pending CN102113113A (en) | 2008-08-04 | 2009-05-13 | Manufacturing method of dielectric thin-film capacitor and dielectric thin-film capacitor |
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| Country | Link |
|---|---|
| JP (1) | JP5348565B2 (en) |
| CN (1) | CN102113113A (en) |
| WO (1) | WO2010016171A1 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103219318A (en) * | 2013-04-12 | 2013-07-24 | 中国电子科技集团公司第十三研究所 | High-temperature-resistant MIM capacitor for microwave internal matching transistor and manufacturing method thereof |
| CN107689299A (en) * | 2016-08-05 | 2018-02-13 | 三星电机株式会社 | Thin film ceramic capacitors |
| CN109923630A (en) * | 2016-11-02 | 2019-06-21 | 株式会社村田制作所 | Capacitor |
| US10720280B2 (en) | 2016-08-05 | 2020-07-21 | Samsung Electro-Mechanics Co., Ltd. | Thin-film ceramic capacitor having capacitance forming portions separated by separation slit |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5924461B1 (en) * | 2014-08-06 | 2016-05-25 | 株式会社村田製作所 | Composite electronic components |
| WO2017057422A1 (en) * | 2015-10-02 | 2017-04-06 | 株式会社村田製作所 | Thin film lc component and mounting structure of same |
| JP7039982B2 (en) * | 2017-12-13 | 2022-03-23 | 富士電機株式会社 | Resistor element and its manufacturing method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1022464A (en) * | 1996-07-03 | 1998-01-23 | Matsushita Electron Corp | Semiconductor device and manufacture thereof |
| JPH1041485A (en) * | 1996-07-26 | 1998-02-13 | Hitachi Ltd | Semiconductor device and production of the same |
| JPH10321803A (en) * | 1997-05-23 | 1998-12-04 | Mitsubishi Materials Corp | Thin film capacitor |
-
2009
- 2009-05-13 JP JP2010523721A patent/JP5348565B2/en not_active Expired - Fee Related
- 2009-05-13 CN CN2009801311664A patent/CN102113113A/en active Pending
- 2009-05-13 WO PCT/JP2009/002090 patent/WO2010016171A1/en active Application Filing
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1022464A (en) * | 1996-07-03 | 1998-01-23 | Matsushita Electron Corp | Semiconductor device and manufacture thereof |
| JPH1041485A (en) * | 1996-07-26 | 1998-02-13 | Hitachi Ltd | Semiconductor device and production of the same |
| JPH10321803A (en) * | 1997-05-23 | 1998-12-04 | Mitsubishi Materials Corp | Thin film capacitor |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103219318A (en) * | 2013-04-12 | 2013-07-24 | 中国电子科技集团公司第十三研究所 | High-temperature-resistant MIM capacitor for microwave internal matching transistor and manufacturing method thereof |
| CN103219318B (en) * | 2013-04-12 | 2015-07-08 | 中国电子科技集团公司第十三研究所 | High-temperature-resistant MIM capacitor for microwave internal matching transistor and manufacturing method thereof |
| CN107689299A (en) * | 2016-08-05 | 2018-02-13 | 三星电机株式会社 | Thin film ceramic capacitors |
| US10468187B2 (en) | 2016-08-05 | 2019-11-05 | Samsung Electro-Mechanics Co., Ltd. | Thin-film ceramic capacitor having capacitance forming portions separated by separation slit |
| US10720280B2 (en) | 2016-08-05 | 2020-07-21 | Samsung Electro-Mechanics Co., Ltd. | Thin-film ceramic capacitor having capacitance forming portions separated by separation slit |
| CN109923630A (en) * | 2016-11-02 | 2019-06-21 | 株式会社村田制作所 | Capacitor |
| CN109923630B (en) * | 2016-11-02 | 2023-04-28 | 株式会社村田制作所 | Capacitor with a capacitor body |
Also Published As
| Publication number | Publication date |
|---|---|
| JPWO2010016171A1 (en) | 2012-01-12 |
| JP5348565B2 (en) | 2013-11-20 |
| WO2010016171A1 (en) | 2010-02-11 |
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Application publication date: 20110629 |