WO2010016171A1 - Manufacturing method of dielectric thin-film capacitor and dielectric thin-film capacitor - Google Patents

Manufacturing method of dielectric thin-film capacitor and dielectric thin-film capacitor Download PDF

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Publication number
WO2010016171A1
WO2010016171A1 PCT/JP2009/002090 JP2009002090W WO2010016171A1 WO 2010016171 A1 WO2010016171 A1 WO 2010016171A1 JP 2009002090 W JP2009002090 W JP 2009002090W WO 2010016171 A1 WO2010016171 A1 WO 2010016171A1
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Prior art keywords
electrode
thin film
layer
capacitor
dielectric
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PCT/JP2009/002090
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French (fr)
Japanese (ja)
Inventor
野村雅信
竹島裕
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株式会社 村田製作所
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Application filed by 株式会社 村田製作所 filed Critical 株式会社 村田製作所
Priority to JP2010523721A priority Critical patent/JP5348565B2/en
Priority to CN2009801311664A priority patent/CN102113113A/en
Publication of WO2010016171A1 publication Critical patent/WO2010016171A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/01—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate
    • H01L27/016—Thin-film circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/224—Housing; Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/228—Terminals
    • H01G4/236—Terminals leading through the housing, i.e. lead-through
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/33—Thin- or thick-film capacitors 

Definitions

  • the present invention relates to a dielectric thin film capacitor manufacturing method and a dielectric thin film capacitor. More specifically, the present invention relates to a dielectric thin film capacitor manufacturing method in which external electrodes are formed on both sides of a main surface of a conductive substrate, and the manufacturing method. The present invention relates to a dielectric thin film capacitor manufactured using the same.
  • an oxide having a perovskite structure such as barium titanate is often used in the dielectric portion of the capacitor.
  • a conductive film 102 is in ohmic contact with one surface of a low-resistance silicon substrate 101, and the other surface is almost equal to a titanate-based insulator.
  • the first metal electrode 103 having a lattice constant is interposed through a eutectic prevention film 104 having a predetermined pattern for preventing the first metal electrode 103 and the silicon substrate 101 from being eutectic.
  • 103 is deposited so as to be connected to the silicon substrate 101, a titanate-based insulating film 105 is deposited on the first metal electrode 103, and a second layer is formed on the insulating film 105.
  • a thin film capacitor (dielectric thin film capacitor) having a metal electrode 106 deposited thereon has been proposed.
  • Each of the first metal electrode 103 and the second metal electrode 106 has a three-layer structure of Cr layers 103a and 106a, Pt layers 103b and 106b, and Au layers 103c and 106c, and the insulating film 105 is a dielectric portion of the capacitor. It corresponds to.
  • the first metal electrode 103 has a structure in which the pattern is formed larger than the eutectic prevention film 104 and is in contact with the silicon substrate 101, and the insulating layer 105 is sputtered at 500 to 600 ° C.
  • the first metal electrode 103 and the silicon substrate 101 are eutectic and are in ohmic contact.
  • the crystallinity of the dielectric thin film is improved by heat treatment, thereby improving the dielectric characteristics.
  • Electrodes are formed on both sides of the silicon substrate 101, such as a thin film capacitor in which a conductive film 102 is formed on the lower surface of the silicon substrate 101 as shown in Patent Document 1, the eutectic portion and silicon are formed when heat treatment is performed. Because of the oxidation, the contact resistance between the first metal electrode 103 and the silicon substrate 101 increases, and the equivalent series resistance (hereinafter referred to as “ESR”) of the capacitor may increase.
  • ESR equivalent series resistance
  • the present invention has been made in view of such circumstances, and provides a dielectric thin film capacitor manufacturing method and a dielectric thin film capacitor capable of suppressing an increase in ESR without impairing reliability even when heat treatment is performed. For the purpose.
  • a method of manufacturing a dielectric thin film capacitor according to the present invention includes forming at least one first external electrode on one main surface side of a conductive substrate, and forming the other main electrode of the conductive substrate.
  • a capacitor portion forming step formed on the one main surface of the conductive substrate, and an electrode layer to be one of the electrode layers and the conductive substrate are electrically connected to form a substrate wiring A wiring formation step, and a heat treatment step of heat treating the capacitor portion between the capacitor formation step and the wiring formation step.
  • the dielectric thin film capacitor manufacturing method of the present invention further includes an insulating layer forming step of covering the capacitor portion with an insulating layer between the heat treatment step and the wiring forming step, and at least a part of the substrate wiring. Is formed on the insulating layer.
  • the dielectric thin film capacitor manufacturing method of the present invention includes a thin film resistance forming step for forming a thin film resistor electrically connected to the capacitor portion between the heat treatment step and the wiring forming step. It is characterized by that.
  • the dielectric thin film capacitor manufacturing method of the present invention is characterized in that the thin film resistor forming step forms the thin film resistor in a flat shape.
  • At least one first external electrode is formed on one main surface side of the conductive substrate, and the second main surface side of the conductive substrate is a second one.
  • a dielectric thin film capacitor in which an external electrode is formed, wherein the capacitor portion including at least one capacitance generating portion having electrode layers on both upper and lower surfaces of the dielectric layer is the one main surface of the conductive substrate.
  • An electrode layer that is formed on the electrode layer and is to be one of the electrode layers is electrically connected to the second external electrode via a substrate wiring and the conductive substrate, and the other electrode layer
  • An electrode layer to be a pole is electrically connected to the first external electrode, the capacitor portion is heat-treated, and at least the substrate wiring is formed after the heat treatment.
  • the dielectric thin film capacitor of the present invention is characterized in that the capacitor portion is covered with an insulating layer, and at least a part of the substrate wiring is formed on the insulating layer.
  • the dielectric thin film capacitor of the present invention is characterized in that the thin film resistor is formed so as to be electrically connected to the electrode layer to be the other electrode.
  • the dielectric thin film capacitor of the present invention is characterized in that the thin film resistor is formed on a capacitor portion.
  • the dielectric thin film capacitor of the present invention is characterized in that the thin film resistor is formed in a flat shape.
  • the substrate wiring is formed after the capacitor portion is heat-treated, the substrate wiring is not exposed to the heat treatment atmosphere and oxidized. Accordingly, even if heat treatment is performed, the reliability of the capacitor portion is not impaired, and an increase in ESR can be suppressed.
  • the substrate wiring can be made sufficiently thick.
  • a low resistance conductive material such as Au or Cu, and it is possible to sufficiently reduce the resistance between the electrode layer to be the one electrode and the second external electrode. is there. That is, it is possible to obtain a high-capacity, high-reliability, low-ESR dielectric thin film capacitor with a high degree of freedom in selecting the material and shape of the wiring and adjusting the length.
  • the capacitor portion is covered with an insulating layer before the substrate wiring is formed, it is possible to prevent deterioration of the capacitor characteristics due to etching during wiring formation.
  • the thin film resistor is formed on the capacitor portion, it is possible to avoid the increase in size of the element as much as possible even when the thin film resistor is provided.
  • the thin film resistor is formed in a flat shape, it is possible to suppress variation in the resistance value of the thin film resistor.
  • FIG. 1 is a sectional view showing an embodiment (first embodiment) of a dielectric thin film capacitor manufactured by the manufacturing method of the present invention.
  • a diffusion prevention layer 2 made of SiO 2 or the like is formed on one main surface of a conductive substrate 1 made of a semiconductor such as Si, and on the surface of the diffusion prevention layer 2.
  • An adhesion layer 3 is formed, and a capacitor portion 4 is formed on the surface of the adhesion layer 3.
  • the diffusion prevention layer 2 has a function of preventing elements contained in the conductive substrate 1 from diffusing into the capacitor portion 4.
  • the capacitor unit 4 includes a first electrode layer 5 formed on the adhesion layer 3, a dielectric layer 6 formed on the first electrode layer 5, and a first electrode formed on the dielectric layer 6. 2 electrode layers 7.
  • the dielectric layer 6 includes, for example, (Ba, Sr) TiO 3 (hereinafter referred to as “BST”), BaTiO 3 , SrTiO 3, etc., Pb (Zr, Ti) O 3 , SrBi 4 Ti 4 O 15, etc.
  • BST Ba, Sr TiO 3
  • BaTiO 3 BaTiO 3
  • SrTiO 3 etc.
  • SrBi 4 Ti 4 O 15 etc.
  • the bismuth layered compound can be used.
  • the capacitor part 4 is preferably heat-treated in an oxygen-containing atmosphere
  • the first and second electrode layers 5 and 7 are resistant to heat treatment such as Pt, Au, and Ru.
  • a material having properties is preferably used.
  • the adhesion layer 3 a material having the same composition as that of the dielectric layer 6 or a material having the same composition can be used.
  • the capacitor unit 4 is entirely covered with an insulating layer 8.
  • the insulating layer 8 includes an inorganic insulating layer 9 and an organic insulating layer 10.
  • the inorganic insulating layer 9 has a function of preventing moisture from the outside from entering the capacitor unit 4 and is made of, for example, SiN x or SiO 2 .
  • SiN x as the inorganic insulating layer 9, the molar ratio of Si and N 3: Other 4 stoichiometry having a composition Si 3 N 4, and deviates from the stoichiometric composition as required Compounds can be used.
  • the organic insulating layer 10 is formed of a polyimide resin or an epoxy resin, and absorbs mechanical stress from electrode wiring and substrate wiring described later.
  • the first electrode layer 5 is connected to the substrate wiring 11, and the second electrode layer 7 is connected to the electrode wiring 12.
  • the substrate wiring 11 penetrates the insulating layer 8 (the inorganic insulating layer 9 and the organic insulating layer 1) from the upper surface of the first electrode layer 5, and extends from the organic insulating layer 10 to the side surface of the insulating layer 8. And electrically connected to the first connection electrode 14 that is in ohmic contact with the conductive substrate 1.
  • the electrode wiring 12 is formed so as to penetrate the insulating layer 8 (inorganic insulating layer 9 and organic insulating layer 1) from the upper surface of the second electrode layer 7 and to be disposed on the organic insulating layer 10. .
  • An upper external electrode (first external electrode) 15 is formed on the upper surface of the electrode wiring 12, and the second electrode layer 7 is electrically connected to the upper external electrode 15 through the electrode wiring 12. .
  • the upper surface side of the conductive substrate 1 is covered with a protective resin 18 except for the upper external electrode 15.
  • a second connection electrode 16 is formed on the other main surface of the conductive substrate 1, and a lower external electrode (second external electrode) 17 is formed on the second connection electrode 16. .
  • first and second connection electrodes 14 and 16 are preferably formed of Au because it is necessary to lower the ESR by making ohmic contact with the conductive substrate 1.
  • the upper external electrode 15 and the lower external electrode 17 preferably have a multilayer structure, and for example, Au / Cu, Au / Ni, Sn / Cu can be used.
  • the lower external electrode 17 is electrically connected to the first electrode layer 5 via the second connection electrode 16, the conductive substrate 1, the first connection electrode 14, and the substrate wiring 11.
  • the upper external electrode 15 is electrically connected to the second electrode layer 7 through the electrode wiring 12.
  • a conductive substrate 1 made of, for example, a p-type conductive Si substrate having a thickness of 525 ⁇ m is prepared.
  • the diffusion prevention layer 2 and the adhesion layer 3 are sequentially formed.
  • the diffusion prevention layer 2 made of SiO 2 or the like having a thickness of 700 nm is formed by a thermal oxidation method.
  • an adhesion layer 3 of, eg, a 100 nm-thickness is formed on the diffusion prevention layer 2 by a chemical solution deposition (hereinafter referred to as “CSD”) method or the like.
  • CSD chemical solution deposition
  • BST SrTiO 3 , BaTiO 3 , perovskite compounds such as Pb (Zr, Ti) O 3 , bismuth layered compounds such as SrBi 4 Ti 4 O 15, etc.
  • BST chemical solution deposition
  • this film forming raw material solution is applied onto the diffusion preventing layer 2, dried on a hot plate at 300 to 400 ° C., and subjected to crystallization at high temperature heating treatment at a temperature of 650 ° C. for 30 minutes.
  • the adhesion layer 3 is formed.
  • a first electrode layer 5, a dielectric layer 6, and a second electrode layer 7 are sequentially formed.
  • the first electrode layer 5 made of Pt having a film thickness of 200 nm is formed by RF magnetron sputtering or the like, and then the dielectric layer having a film thickness of 100 nm made of BST or the like by the CSD method or the like, similar to the adhesion layer 3. 6 is formed, and then, similarly to the first electrode layer 5, a second electrode layer 6 made of Pt having a thickness of 200 nm is formed by an RF magnetron sputtering method or the like.
  • the adhesion layer 3, the first electrode layer 5, the dielectric layer 6, and the second electrode layer 7 are formed by using a well-known photolithography technique, an argon ion milling method, or the like. Is etched into a predetermined pattern to form the capacitor portion 4. That is, after a photoresist is applied and prebaked, the photoresist is irradiated with ultraviolet light through a photomask, and exposure, development, and postbaking are performed to transfer the photomask pattern to the resist pattern.
  • argon ions are collided with the etching surface by an argon ion milling method to etch predetermined regions of the second electrode layer 7, the dielectric layer 6, the first electrode layer 5, and the adhesion layer 3, and thereby the capacitor portion 4 is produced.
  • the capacitor portion 4 is heat-treated to improve the dielectric characteristics of the dielectric layer 6.
  • This heat treatment is performed to improve the crystallinity of the dielectric layer 6, and is performed at a temperature of, for example, 850 ° C. for 30 minutes.
  • the heat treatment is preferably performed in an oxygen-containing atmosphere.
  • an insulating layer 8 including an inorganic insulating layer 9 and an organic insulating layer 10 is formed so as to cover the entire capacitor unit 4. That is, for example, the inorganic insulating layer 9 made of SiN x or the like having a thickness of 500 nm is formed by sputtering. Next, a photosensitive polyimide is applied so as to cover the upper surface of the inorganic insulating layer 9, and then heated at a temperature of 125 ° C. for 5 minutes, exposed and developed, and then heated at 350 ° C. for about 1 hour. For example, the organic insulating layer 10 having a predetermined pattern with a film thickness of 5000 nm is formed.
  • the organic insulating layer 10 made of photosensitive polyimide is used as a mask, the inorganic insulating layer 9 is processed by reactive ion etching to form holes 19 and 20, and the first Then, a part of the second electrode layers 5 and 7 is exposed on the surface.
  • a part of the diffusion preventing layer 2 is dissolved and removed with buffered hydrofluoric acid to expose a part of the conductive substrate 1 on the surface.
  • Au having a film thickness of, for example, 300 nm is deposited on the surface exposed portion of the conductive substrate 1 by a vacuum deposition method, and the photoresist is removed by a lift-off method, and as shown in FIG. Form.
  • the substrate wiring 11 is formed from the inner surface of the hole 20 to the upper surface and side surfaces of the organic insulating layer 10 and further to the first connection electrode 14, and from the inner surface of the hole 19.
  • An electrode wiring 12 is formed over the upper surface of the organic insulating layer 10. Thereafter, an upper external electrode 15 is formed on the electrode wiring 12.
  • the substrate wiring 11, the electrode wiring 12, and the upper external electrode 15 are specifically produced as follows.
  • a Ti layer having a thickness of 100 nm is formed on the surface by sputtering, and a Cu layer having a thickness of 500 nm is formed on the Ti layer.
  • a photoresist is applied on the Cu layer so as to have an opening on the Cu layer to form a predetermined resist pattern, and then electrolytic plating is performed to form a Ni layer having a thickness of 2000 nm in the opening.
  • an Au layer having a thickness of 1000 nm is sequentially formed.
  • the photoresist is removed to form an upper external electrode 15 having a two-layer structure composed of an Au layer and a Ni layer.
  • a predetermined resist pattern is formed by applying a photoresist on the Cu layer so that the portion to be the electrode wiring 12 and the portion to be the substrate wiring 11 are separated from each other, and then wet etching is performed. Etch Cu layer and Ti layer. Thereafter, the photoresist is removed, and an electrode wiring 12 and a substrate wiring 11 having a two-layer structure composed of a Cu layer and a Ti layer are formed.
  • the portion excluding the upper external electrode 15 on the conductive substrate 1 is covered with a protective resin layer 18.
  • a photosensitive resin such as photosensitive polyimide is applied to the upper surface, and then heated at 125 ° C. for 5 minutes, exposed and developed, and then heated at 350 ° C. for about 1 hour.
  • a protective resin layer 18 having a predetermined pattern of 5000 nm is formed.
  • the second connection electrode 16 is formed on the other main surface of the conductive substrate 1, and the lower external electrode 17 is formed on the second connection electrode 16.
  • the back surface of the conductive substrate 1 is ground to a predetermined thickness, treated with buffered hydrofluoric acid, and a second connection electrode 16 made of Au having a thickness of 300 nm is formed by vacuum deposition.
  • electrolytic plating is performed to sequentially form a 2000 nm thick Ni layer and a 1000 nm thick Au layer, thereby forming a lower external electrode 17 having a two-layer structure.
  • heat treatment is performed at a temperature of 350 ° C. to stabilize the interface between the lower external electrode 17 and the conductive substrate 1, thereby obtaining a dielectric thin film capacitor.
  • the substrate wiring 11 is formed after the capacitor portion 4 is heat-treated, the substrate wiring 11 is not exposed to the heat treatment atmosphere and oxidized. Therefore, even if heat treatment is performed, the increase in ESR can be suppressed without impairing the reliability of the capacitor unit 4.
  • the substrate wiring 11 can be made sufficiently thick, A low resistance conductive material such as Au or Cu can be used for the wiring 11, and the resistance between the second electrode layer 7 and the second external electrode 17 can be sufficiently reduced. It is. That is, it is possible to obtain a high-capacity, high-reliability, low-ESR dielectric thin film capacitor with a high degree of freedom in selecting the material and shape of the wiring and adjusting the length.
  • the capacitor portion 4 is covered with the insulating layer 8 before the substrate wiring 11 is formed, deterioration of the capacitor characteristics due to etching during wiring formation can be prevented.
  • FIG. 5 is a cross-sectional view of a dielectric thin film capacitor showing a second embodiment of the present invention.
  • the second embodiment has two capacitors on one main surface side of the conductive substrate 1.
  • the portions 21a and 21b are formed, and the capacitor portions 21a and 21b are alternately laminated with electrode layers and dielectric layers, and have a plurality of capacitance generating portions.
  • two adhesion layers 23 a and 23 b are formed on the diffusion prevention layer 2 formed on the conductive substrate 1 with the inorganic insulating layer 22 interposed therebetween.
  • the first electrode layers 24a, 24b, the first dielectric layers 25a, 25b, the second electrode layers 26a, 26b, the second dielectric layers 27a, 27b, Third electrode layers 28a and 28b, third dielectric layers 29a and 29b, and fourth electrode layers 30a and 30b are sequentially stacked to form capacitor portions 21a and 21b.
  • the fourth dielectric layers 31a and 31b are formed on the surfaces of the uppermost fourth electrode layers 30a and 30b of the capacitor portions 21a and 21b.
  • the inorganic insulating layer 22 is covered with an organic insulating layer 32.
  • the substrate wirings 33a and 33b and the electrode wirings 35a and 35b are formed so as to have substantially the same shape as in the first embodiment, and the substrate wirings 33a and 33b are in ohmic contact with the conductive substrate 1.
  • One connection electrode 34a, 34b is electrically connected.
  • the first electrode layers 24 a and 24 b are electrically connected to the lower external electrode 17 through the substrate wirings 33 a and 33 b, the first connection electrodes 34 a and 34 b, the conductive substrate 1, and the second connection electrode 16.
  • the fourth electrode layers 30a and 30b are electrically connected to the upper external electrodes 36a and 36b via the electrode wirings 35a and 35b.
  • the entire capacitor substrate 21a, 21b side of the conductive substrate 1 is covered with a protective resin layer 37 except for the upper external electrodes 36a, 36b.
  • the heat treatment of the capacitor portions 21a and 21b is performed before the substrate wirings 33a and 33b are formed, thereby increasing the ESR without impairing the reliability of the capacitor portions. Suppressed.
  • the capacitor portions 21a and 21b have a plurality of capacitance generating portions, a thin film capacitor with improved withstand voltage can be obtained. Further, since the fourth dielectric layers 31a and 31b are formed on the capacitor portions 21a and 21b, it is possible to prevent deterioration of the capacitor during the formation of the inorganic insulating layer 22, and to suppress the leakage current. It becomes possible.
  • FIG. 6 is a cross-sectional view of a dielectric thin film capacitor showing a third embodiment of the present invention.
  • the dielectric thin film capacitor is formed on the diffusion prevention layer 2 formed on the conductive substrate 1.
  • An adhesion layer 23, a first electrode layer 24, and a first dielectric layer 25 are sequentially formed, and electrode layers and dielectric layers are alternately stacked on the first dielectric layer 25 to form a capacitor portion. Forming.
  • the second electrode layers 26a and 26b, the second dielectric layers 27a and 27b, the third electrode layers 28a and 28b, and the third electrode layer are interposed via the inorganic insulating layer 22.
  • the dielectric layers 29a, 29b and the fourth electrode layers 30a, 30b are sequentially stacked.
  • the first to fourth dielectric layers 25, 27a, 27b, 29a, 29b and the first electrode layers 24, 26a, 26b, 28a, 28b, 30a, 30b form a capacitor portion.
  • heat treatment of the capacitor portion is performed before the formation of the substrate wirings 33a and 33b, thereby suppressing an increase in ESR without impairing the reliability of the capacitor portion. Yes.
  • the third embodiment also includes a capacitor section having a plurality of capacitance generating sections, as in the second embodiment, a thin film capacitor with improved withstand voltage can be formed.
  • the fourth dielectric layers 31a and 31b are formed on the capacitor portion, it is possible to prevent the capacitor from being deteriorated when the inorganic insulating layer 22 is formed, and to suppress the leakage current.
  • the first and second embodiments except that the number of laminated dielectric layers and electrode layers and the formation pattern of the dielectric layers, electrode layers, electrode wirings, and substrate wirings are adjusted as appropriate. It can be manufactured in the same manner as in the embodiment.
  • FIG. 7 is a cross-sectional view of a dielectric thin film capacitor showing a fourth embodiment of the present invention.
  • a thin film resistor 42 is formed flat on the organic insulating layer 10.
  • the second electrode layer 7 is electrically connected to the thin film resistor 42 via the electrode wiring 12.
  • the electrode wiring 12 also serves as an upper external electrode, and the thin film resistor 42 is electrically connected to another upper external electrode 41.
  • a diffusion prevention layer 2 made of SiO 2 or the like is formed on one main surface of the conductive substrate 1, and the diffusion prevention layer is formed.
  • An adhesion layer 3 is formed on the surface 2, and a capacitor portion 4 including a first electrode layer 5, a dielectric layer 6, and a second electrode layer 7 is formed on the surface of the adhesion layer 3. .
  • the capacitor portion 4 is covered with an insulating layer 8 composed of an inorganic insulating layer 9 and an organic insulating layer 10 as in the first embodiment.
  • the substrate wiring 11 and the electrode wiring 12 are also formed in substantially the same shape as in the first embodiment, and the first electrode layer 5 is connected to the substrate wiring 11 and the second electrode layer 7 is an electrode. It is connected to the wiring 12.
  • the electrode wiring 12 also serves as the upper external electrode as described above.
  • an upper external electrode 41 is formed on the surface of the organic insulating layer 10, and the upper external electrode 41 and the electrode wiring 12 are electrically connected via a thin film resistor 42.
  • the conductive substrate 1 is entirely covered with a protective resin layer 43 except for the electrode wiring 12 and the upper external electrode 41.
  • the diffusion prevention layer 2, the adhesion layer 3, the first electrode layer 5, the dielectric layer 6, and the second electrode layer 6 are sequentially formed on the conductive substrate 1,
  • the capacitor portion 4 is formed by etching into a predetermined pattern using a known photolithography technique and an argon ion milling method. And in order to improve the dielectric characteristic of the dielectric material layer 6, the capacitor
  • an insulating layer 8 composed of an inorganic insulating layer 9 and an organic insulating layer 10 is formed so as to cover the capacitor portion 4, and the inorganic insulating layer 9 is processed by a reactive ion etching method.
  • the holes 19 and 20 are formed and a part of 1st and 2nd electrode layers 5 and 7 are surface-exposed.
  • a thin film layer made of TaN or Ni—Cr alloy having a film thickness of 40 to 60 nm is formed by sputtering.
  • a predetermined region is etched away by reactive ion etching to form a thin film resistor 42, and then the photoresist is dissolved and removed.
  • a part of the diffusion preventing layer 2 is dissolved and removed with buffered hydrofluoric acid, and a part of the conductive substrate 1 is exposed on the surface.
  • a 100 nm thick Ti layer and a 500 nm thick Au layer are formed by sputtering, then a photoresist is applied to form a resist pattern, and the Au layer and Ti layer are processed by wet etching. The photoresist is removed, thereby forming the substrate wiring 11, the electrode wiring 12, and the upper external electrode 41 as shown in FIG. 9D. Thereafter, heat treatment is performed in air at 370 ° C. for 30 minutes to oxidize the thin film resistor 42 and perform stabilization treatment.
  • the protective resin layer 43 is covered so as to cover the whole except for the upper external electrode 41 and the electrode wiring 12 by the same method and procedure as in the first embodiment.
  • the second connection electrode 16 is formed on the other main surface of the conductive substrate 1 by the same method and procedure as in the first embodiment, and the second A lower external electrode 17 is formed on the connection electrode 16.
  • a thin film resistor 42 is added, so that a thin film having a high capacity, high reliability, and low ESR combined with a resistance function.
  • a capacitor can be realized.
  • the thin film resistor is formed on the capacitor portion 4, it is possible to avoid the increase in the size of the element as much as possible.
  • the thin film resistor 42 is formed in a flat shape, it is possible to suppress variation in the resistance value.
  • FIG. 10 is a cross-sectional view of a dielectric thin film capacitor showing a fifth embodiment.
  • the thin film resistor 46 is formed on the diffusion preventing layer 2, and the electrode wiring 47 and the upper external electrode 45 are electrically connected to the thin film resistor 46 on the surface of the diffusion preventing layer 2. It is connected.
  • the thin film resistor 46 is formed on the diffusion prevention layer 2 as in the fifth embodiment, the thin film resistor 46 is added in addition to the function and effect of the first embodiment. It is possible to realize a high-capacity, high-reliability, low-ESR thin-film capacitor that combines functions.
  • the thin film resistor 46 is formed in a flat shape, it is possible to suppress variation in resistance value.
  • FIG. 11 is a cross-sectional view of a dielectric thin film capacitor showing a sixth embodiment.
  • the capacitor section has a structure substantially similar to that of the third embodiment.
  • the adhesion layer 48, the first electrode layer 49, and the first dielectric layer 50 are sequentially formed on the diffusion prevention layer 2 formed on the conductive substrate 1, and the first dielectric layer 50 is formed on the first dielectric layer 50. Electrode layers and dielectric layers are alternately stacked to form a capacitor portion.
  • the dielectric layers 55a and 55b, the fourth electrode layers 56a and 56b, the fourth dielectric layers 57a and 57b, and the fifth electrode layers 58a and 58b are sequentially stacked, and the first to fourth dielectric layers are sequentially stacked.
  • the body layers 50, 53a, 53b, 55a, 55b, 57a, 57b and the first to fifth electrode layers 49, 52a, 52b, 54a, 54b, 56a, 56b, 58a, 58b form a capacitor portion.
  • fifth dielectric layers 59 a and 59 b are formed on the fifth electrode layers 58 a and 58 b, and the upper surface of the inorganic insulating layer 51 is covered with the organic insulating layer 60.
  • the substrate wiring 61 and the electrode wirings 62 and 63 have substantially the same shape as that of the fourth embodiment, and the first electrode layer 49 is connected to the first connection electrode 14 via the substrate wiring 11.
  • the fifth electrode layers 58a and 58b are electrically connected to electrode wirings 63 and 62 that also serve as upper external electrodes, respectively.
  • a thin film resistor 64 is formed on the organic insulating layer 60, and the electrode wiring 63 and the upper external electrode 65 are electrically connected to the thin film resistance 64, whereby the fifth electrode layer 58 is connected to the electrode wiring 63 and the thin film.
  • the upper external electrode 65 is electrically connected through the resistor 64.
  • the thin film resistor 64 in addition to the function and effect of the first embodiment, by adding the thin film resistor 64, the high-capacity, high reliability, and low ESR combined with the resistance function are achieved.
  • a thin film capacitor can be realized.
  • the thin film resistor 64 is formed on the capacitor portion, it is possible to avoid the increase in size of the element as much as possible.
  • the thin film resistor 64 is formed in a flat shape, it is possible to suppress the variation in the resistance value.
  • the present invention is not limited to the above embodiment. Although the present invention can be modified in various ways as described above, the film formation method, film formation conditions, film thickness, etc. described in the above embodiments are exemplifications. It is not limited. Needless to say, when a plurality of parts are manufactured together, they may be divided individually by dicing or the like.

Abstract

Disclosed is a manufacturing method of a dielectric thin-film capacitor which forms an upper external electrode (15) on one main surface of a conductive substrate (1) and forms a lower external electrode (17) on the other main surface of the conductive substrate (1). The method includes a capacitor forming process which forms a capacitor (4), which is formed from first and second electrode layers (5,7) on both the top and bottom surfaces of a dielectric layer (6), on one main surface of the conductive substrate (1); and a wire forming process which forms substrate wires (11) which electrically connect the first electrode layer (5) to the conductive substrate (1); and includes a heat treatment process for heat treating the capacitor (4) between the capacitor forming process and the wire forming process. Thus, a dielectric thin-film capacitor which can suppress an increase in the equivalent series resistance (ESR) without a loss in reliability is implemented.

Description

誘電体薄膜キャパシタの製造方法、及び誘電体薄膜キャパシタDielectric thin film capacitor manufacturing method and dielectric thin film capacitor
　本発明は、誘電体薄膜キャパシタの製造方法、及び誘電体薄膜キャパシタに関し、より詳しくは導電性基板の主面の両側に外部電極が形成された誘電体薄膜キャパシタの製造方法、及びこの製造方法を使用して作製された誘電体薄膜キャパシタに関する。 The present invention relates to a dielectric thin film capacitor manufacturing method and a dielectric thin film capacitor. More specifically, the present invention relates to a dielectric thin film capacitor manufacturing method in which external electrodes are formed on both sides of a main surface of a conductive substrate, and the manufacturing method. The present invention relates to a dielectric thin film capacitor manufactured using the same.
　従来より、この種の誘電体薄膜キャパシタは、チタン酸バリウム等のペロブスカイト構造を有する酸化物がキャパシタの誘電体部分に多く用いられている。 Conventionally, in this type of dielectric thin film capacitor, an oxide having a perovskite structure such as barium titanate is often used in the dielectric portion of the capacitor.
　例えば、特許文献１には、図１２に示すように、低抵抗のシリコン基板１０１の一方の面には導電性被膜１０２をオーミックコンタクトし、他方の面にはチタン酸系の絶縁物とほぼ等しい格子定数をもつ第１の金属電極１０３を該第１の金属電極１０３と前記シリコン基板１０１とが共晶するのを防ぐ所定パターンの共晶防止膜１０４を介在してかつ該第１の金属電極１０３の一部が前記シリコン基板１０１に接続するように被着形成し、該第１の金属電極１０３上にチタン酸系の絶縁膜１０５を被着形成し、さらに該絶縁膜１０５上に第２の金属電極１０６を被着形成した薄膜コンデンサ（誘電体薄膜キャパシタ）が提案されている。 For example, in Patent Document 1, as shown in FIG. 12, a conductive film 102 is in ohmic contact with one surface of a low-resistance silicon substrate 101, and the other surface is almost equal to a titanate-based insulator. The first metal electrode 103 having a lattice constant is interposed through a eutectic prevention film 104 having a predetermined pattern for preventing the first metal electrode 103 and the silicon substrate 101 from being eutectic. 103 is deposited so as to be connected to the silicon substrate 101, a titanate-based insulating film 105 is deposited on the first metal electrode 103, and a second layer is formed on the insulating film 105. A thin film capacitor (dielectric thin film capacitor) having a metal electrode 106 deposited thereon has been proposed.
　第１の金属電極１０３及び第２の金属電極１０６は、いずれもＣｒ層１０３ａ、１０６ａ、Ｐｔ層１０３ｂ、１０６ｂ及びＡｕ層１０３ｃ、１０６ｃの三層構造からなり、絶縁膜１０５がキャパシタの誘電体部分に相当する。 Each of the first metal electrode 103 and the second metal electrode 106 has a three-layer structure of Cr layers 103a and 106a, Pt layers 103b and 106b, and Au layers 103c and 106c, and the insulating film 105 is a dielectric portion of the capacitor. It corresponds to.
　この特許文献１では、第１の金属電極１０３は、そのパターンを共晶防止膜１０４より大きく形成して、シリコン基板１０１と接触する構造となっており、絶縁層１０５を５００～６００℃でスパッタリングする際に、第１の金属電極１０３とシリコン基板１０１とが共晶してオーミックコンタクトしている。 In this Patent Document 1, the first metal electrode 103 has a structure in which the pattern is formed larger than the eutectic prevention film 104 and is in contact with the silicon substrate 101, and the insulating layer 105 is sputtered at 500 to 600 ° C. In this case, the first metal electrode 103 and the silicon substrate 101 are eutectic and are in ohmic contact.
特開昭５６－８３９１７号公報JP 56-83917 A
　ところで、この種の誘電体薄膜キャパシタでは、通常、スパッタ法やＣＶＤ法等により薄膜を堆積させた後、熱処理により誘電体薄膜の結晶性を向上させ、これにより誘電特性の向上を図っている。 By the way, in this type of dielectric thin film capacitor, usually, after depositing a thin film by a sputtering method, a CVD method or the like, the crystallinity of the dielectric thin film is improved by heat treatment, thereby improving the dielectric characteristics.
　しかしながら、特許文献１に示すようなシリコン基板１０１の下面に導電性被膜１０２を形成した薄膜コンデンサのように、シリコン基板１０１の両側に電極を形成する場合、熱処理を行うと共晶部分及びシリコンが酸化されるため、第１の金属電極１０３とシリコン基板１０１との間の接触抵抗が大きくなり、キャパシタの等価直列抵抗（以下、「ＥＳＲ」という。）が増大するおそれがある。 However, when electrodes are formed on both sides of the silicon substrate 101, such as a thin film capacitor in which a conductive film 102 is formed on the lower surface of the silicon substrate 101 as shown in Patent Document 1, the eutectic portion and silicon are formed when heat treatment is performed. Because of the oxidation, the contact resistance between the first metal electrode 103 and the silicon substrate 101 increases, and the equivalent series resistance (hereinafter referred to as “ESR”) of the capacitor may increase.
　一方、接触抵抗を小さくするためには第１の金属電極１０３の膜厚を厚くすることが考えられるが、この場合は第１の金属電極１０３の表面が粗くなり、その結果、キャパシタ特性の劣化を招くおそれがある。 On the other hand, in order to reduce the contact resistance, it is conceivable to increase the film thickness of the first metal electrode 103. In this case, however, the surface of the first metal electrode 103 becomes rough, resulting in deterioration of capacitor characteristics. May be incurred.
　本発明はこのような事情に鑑みなされたものであって、熱処理を行っても信頼性を損なうことなく、ＥＳＲの増加を抑制できる誘電体薄膜キャパシタの製造方法、及び誘電体薄膜キャパシタを提供することを目的とする。 The present invention has been made in view of such circumstances, and provides a dielectric thin film capacitor manufacturing method and a dielectric thin film capacitor capable of suppressing an increase in ESR without impairing reliability even when heat treatment is performed. For the purpose.
　上記目的を達成するために本発明に係る誘電体薄膜キャパシタの製造方法は、導電性基板の一方の主面側に少なくとも一つの第１の外部電極を形成し、前記導電性基板の他方の主面側に第２の外部電極を形成した誘電体薄膜キャパシタの製造方法であって、誘電体層の上下両面に電極層が形成された少なくとも一つ以上の容量発生部を有するキャパシタ部を前記導電性基板の前記一方の主面上に形成するキャパシタ部形成工程と、前記電極層のうちの一方の極となるべき電極層と前記導電性基板とを電気的に接続して基板配線を形成する配線形成工程とを有し、前記キャパシタ形成工程と前記配線形成工程との間に前記キャパシタ部を熱処理する熱処理工程を含んでいることを特徴としている。 In order to achieve the above object, a method of manufacturing a dielectric thin film capacitor according to the present invention includes forming at least one first external electrode on one main surface side of a conductive substrate, and forming the other main electrode of the conductive substrate. A method of manufacturing a dielectric thin film capacitor in which a second external electrode is formed on a surface side, wherein the capacitor portion having at least one capacitance generating portion having electrode layers formed on both upper and lower surfaces of the dielectric layer is electrically conductive. A capacitor portion forming step formed on the one main surface of the conductive substrate, and an electrode layer to be one of the electrode layers and the conductive substrate are electrically connected to form a substrate wiring A wiring formation step, and a heat treatment step of heat treating the capacitor portion between the capacitor formation step and the wiring formation step.
　また、本発明の誘電体薄膜キャパシタの製造方法は、前記熱処理工程と前記配線形成工程との間に前記キャパシタ部を絶縁層で被覆する絶縁層形成工程を有し、前記基板配線の少なくとも一部を前記絶縁層上に形成することを特徴としている。 The dielectric thin film capacitor manufacturing method of the present invention further includes an insulating layer forming step of covering the capacitor portion with an insulating layer between the heat treatment step and the wiring forming step, and at least a part of the substrate wiring. Is formed on the insulating layer.
　また、本発明の誘電体薄膜キャパシタの製造方法は、前記キャパシタ部と電気的に接続された薄膜抵抗を形成する薄膜抵抗形成工程を前記熱処理工程と前記配線形成工程との間に有していることを特徴としている。 Further, the dielectric thin film capacitor manufacturing method of the present invention includes a thin film resistance forming step for forming a thin film resistor electrically connected to the capacitor portion between the heat treatment step and the wiring forming step. It is characterized by that.
　さらに、本発明の誘電体薄膜キャパシタの製造方法は、前記薄膜抵抗形成工程が、前記薄膜抵抗を平坦状に形成することを特徴としている。 Furthermore, the dielectric thin film capacitor manufacturing method of the present invention is characterized in that the thin film resistor forming step forms the thin film resistor in a flat shape.
　また、本発明に係る誘電体薄膜キャパシタは、導電性基板の一方の主面側に少なくとも一つの第１の外部電極が形成されると共に、前記導電性基板の他方の主面側に第２の外部電極が形成された誘電体薄膜キャパシタであって、誘電体層の上下両面に電極層を有する少なくとも一つ以上の容量発生部を備えたキャパシタ部が、前記導電性基板の前記一方の主面上に形成されると共に、前記電極層のうちの一方の極となるべき電極層が、基板配線及び前記導電性基板を介して前記第２の外部電極と電気的に接続され、かつ、他方の極となるべき電極層が、前記第１の外部電極と電気的に接続され、前記キャパシタ部が熱処理されてなると共に、少なくとも前記基板配線は、前記熱処理後に形成されることを特徴としている。 In the dielectric thin film capacitor according to the present invention, at least one first external electrode is formed on one main surface side of the conductive substrate, and the second main surface side of the conductive substrate is a second one. A dielectric thin film capacitor in which an external electrode is formed, wherein the capacitor portion including at least one capacitance generating portion having electrode layers on both upper and lower surfaces of the dielectric layer is the one main surface of the conductive substrate. An electrode layer that is formed on the electrode layer and is to be one of the electrode layers is electrically connected to the second external electrode via a substrate wiring and the conductive substrate, and the other electrode layer An electrode layer to be a pole is electrically connected to the first external electrode, the capacitor portion is heat-treated, and at least the substrate wiring is formed after the heat treatment.
　また、本発明の誘電体薄膜キャパシタは、前記キャパシタ部は絶縁層で被覆されると共に、前記基板配線の少なくも一部が前記絶縁層上に形成されていることを特徴としている。 The dielectric thin film capacitor of the present invention is characterized in that the capacitor portion is covered with an insulating layer, and at least a part of the substrate wiring is formed on the insulating layer.
　さらに、本発明の誘電体薄膜キャパシタは、薄膜抵抗が、前記他方の極となるべき電極層と電気的に接続されるように形成されていることを特徴としている。 Furthermore, the dielectric thin film capacitor of the present invention is characterized in that the thin film resistor is formed so as to be electrically connected to the electrode layer to be the other electrode.
　また、本発明の誘電体薄膜キャパシタは、前記薄膜抵抗は、キャパシタ部上に形成されていることを特徴としている。 The dielectric thin film capacitor of the present invention is characterized in that the thin film resistor is formed on a capacitor portion.
　また、本発明の誘電体薄膜キャパシタは、薄膜抵抗が、平坦状に形成されていることを特徴としている。 The dielectric thin film capacitor of the present invention is characterized in that the thin film resistor is formed in a flat shape.
　上記誘電体薄膜キャパシタの製造方法、及び薄膜キャパシタによれば、キャパシタ部を熱処理した後に基板配線を形成するため、基板配線が熱処理雰囲気に晒されて酸化されることもない。したがって熱処理を行ってもキャパシタ部の信頼性を損なうことがなく、ＥＳＲの増加を抑制することができる。 According to the method for manufacturing a dielectric thin film capacitor and the thin film capacitor, since the substrate wiring is formed after the capacitor portion is heat-treated, the substrate wiring is not exposed to the heat treatment atmosphere and oxidized. Accordingly, even if heat treatment is performed, the reliability of the capacitor portion is not impaired, and an increase in ESR can be suppressed.
　また、一方の極となるべき電極層と導電性基板とを直接に電気的接続させるのではなく、基板配線を介して電気的接続させているので、基板配線を十分に厚くしたり、基板配線にＡｕやＣｕ等の低抵抗の導電性材料を使用することが可能であり、前記一方の極となるべき電極層から第２の外部電極までの間の抵抗を十分に低減することが可能である。すなわち、配線の材質や形状の選定、長さの調整の自由度の大きい高容量、高信頼性・低ＥＳＲの誘電体薄膜キャパシタを得ることができる。 In addition, since the electrode layer to be one pole and the conductive substrate are not directly electrically connected but via the substrate wiring, the substrate wiring can be made sufficiently thick, In addition, it is possible to use a low resistance conductive material such as Au or Cu, and it is possible to sufficiently reduce the resistance between the electrode layer to be the one electrode and the second external electrode. is there. That is, it is possible to obtain a high-capacity, high-reliability, low-ESR dielectric thin film capacitor with a high degree of freedom in selecting the material and shape of the wiring and adjusting the length.
　また、基板配線を形成する前にキャパシタ部を絶縁層で被覆するので、配線形成時のエッチングによるキャパシタ特性の劣化を防ぐことができる。 In addition, since the capacitor portion is covered with an insulating layer before the substrate wiring is formed, it is possible to prevent deterioration of the capacitor characteristics due to etching during wiring formation.
　また、キャパシタ構造に薄膜抵抗を付加するので、抵抗機能を備えた高容量、高信頼性、低ＥＳＲの誘電体薄膜キャパシタを得ることができる。 Also, since a thin film resistor is added to the capacitor structure, a high capacity, high reliability, low ESR dielectric thin film capacitor having a resistance function can be obtained.
　また、薄膜抵抗をキャパシタ部上に形成するので、薄膜抵抗を備えている場合であっても素子の大型化を極力回避することができる。 In addition, since the thin film resistor is formed on the capacitor portion, it is possible to avoid the increase in size of the element as much as possible even when the thin film resistor is provided.
　また、薄膜抵抗を平坦状に形成するので、薄膜抵抗の抵抗値にバラツキが生じるのを抑制することができる。 Further, since the thin film resistor is formed in a flat shape, it is possible to suppress variation in the resistance value of the thin film resistor.
本発明の製造方法で製造された誘電体薄膜キャパシタの一実施の形態（第１の実施の形態）を示す断面図である。It is sectional drawing which shows one Embodiment (1st Embodiment) of the dielectric thin film capacitor manufactured with the manufacturing method of this invention. 本発明に係る誘電体薄膜キャパシタの製造方法の一実施の形態を示す製造工程の断面図（１／３）である。It is sectional drawing (1/3) of the manufacturing process which shows one Embodiment of the manufacturing method of the dielectric thin film capacitor which concerns on this invention. 本発明に係る誘電体薄膜キャパシタの製造方法の一実施の形態を示す製造工程の断面図（２／３）である。It is sectional drawing (2/3) of the manufacturing process which shows one Embodiment of the manufacturing method of the dielectric thin film capacitor which concerns on this invention. 本発明に係る誘電体薄膜キャパシタの製造方法の一実施の形態を示す製造工程の断面図（３／３）である。It is sectional drawing (3/3) of the manufacturing process which shows one Embodiment of the manufacturing method of the dielectric thin film capacitor which concerns on this invention. 本発明の第２の実施の形態を示す断面図である。It is sectional drawing which shows the 2nd Embodiment of this invention. 本発明の第３の実施の形態を示す断面図である。It is sectional drawing which shows the 3rd Embodiment of this invention. 本発明の第４の実施の形態を示す断面図である。It is sectional drawing which shows the 4th Embodiment of this invention. 第４の実施の形態の製造工程の要部を示す断面図（１／２）である。It is sectional drawing (1/2) which shows the principal part of the manufacturing process of 4th Embodiment. 第４の実施の形態の製造工程の要部を示す断面図（２／２）である。It is sectional drawing (2/2) which shows the principal part of the manufacturing process of 4th Embodiment. 本発明の第５の実施の形態を示す断面図である。It is sectional drawing which shows the 5th Embodiment of this invention. 本発明の第６の実施の形態を示す断面図である。It is sectional drawing which shows the 6th Embodiment of this invention. 特許文献１に記載された従来例の断面図である。It is sectional drawing of the prior art example described in patent document 1. FIG.
　次に、本発明の実施の形態を添付図面に基づき詳説する。 Next, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
　図１は本発明の製造方法により製造された誘電体薄膜キャパシタの一実施の形態（第１の実施の形態）を示す断面図である。 FIG. 1 is a sectional view showing an embodiment (first embodiment) of a dielectric thin film capacitor manufactured by the manufacturing method of the present invention.
　すなわち、この誘電体薄膜キャパシタは、Ｓｉ等の半導体で形成された導電性基板１の一方の主面にＳｉＯ２等からなる拡散防止層２が形成されると共に、該拡散防止層２の表面には密着層３が形成され、さらに、該密着層３の表面にはキャパシタ部４が形成されている。前記拡散防止層２は、導電性基板１に含有される元素がキャパシタ部４に拡散するのを防止する機能を有する。 That is, in this dielectric thin film capacitor, a diffusion prevention layer 2 made of SiO 2 or the like is formed on one main surface of a conductive substrate 1 made of a semiconductor such as Si, and on the surface of the diffusion prevention layer 2. An adhesion layer 3 is formed, and a capacitor portion 4 is formed on the surface of the adhesion layer 3. The diffusion prevention layer 2 has a function of preventing elements contained in the conductive substrate 1 from diffusing into the capacitor portion 4.
　キャパシタ部４は、密着層３上に形成された第１の電極層５と、該第１の電極層５上に形成された誘電体層６と、該誘電体層６上に形成された第２の電極層７とから構成されている。 The capacitor unit 4 includes a first electrode layer 5 formed on the adhesion layer 3, a dielectric layer 6 formed on the first electrode layer 5, and a first electrode formed on the dielectric layer 6. 2 electrode layers 7.
　誘電体層６は、例えば（Ｂａ，Ｓｒ）ＴｉＯ３（以下、「ＢＳＴ」という。）、ＢａＴｉＯ３，ＳｒＴｉＯ３などの他、Ｐｂ（Ｚｒ，Ｔｉ）Ｏ３系、ＳｒＢｉ４Ｔｉ４Ｏ15等のビスマス層状化合物を用いることができる。 The dielectric layer 6 includes, for example, (Ba, Sr) TiO 3 (hereinafter referred to as “BST”), BaTiO 3 , SrTiO 3, etc., Pb (Zr, Ti) O 3 , SrBi 4 Ti 4 O 15, etc. The bismuth layered compound can be used.
　また、第１及び第２の電極層５、７は、後述するように、キャパシタ部４が好ましくは酸素含有雰囲気で熱処理されてなることから、Ｐｔ、Ａｕ、Ｒｕ等の熱処理に対して耐酸化性を有する材料が好んで使用される。尚、密着層３は、誘電体層６と同一組成系の材料、又は同一組成の材料を使用することができる。 Further, as will be described later, since the capacitor part 4 is preferably heat-treated in an oxygen-containing atmosphere, the first and second electrode layers 5 and 7 are resistant to heat treatment such as Pt, Au, and Ru. A material having properties is preferably used. For the adhesion layer 3, a material having the same composition as that of the dielectric layer 6 or a material having the same composition can be used.
　キャパシタ部４は、全体が絶縁層８で被覆されている。この絶縁層８は、無機絶縁層９と有機絶縁層１０とからなる。無機絶縁層９は外部からの水分がキャパシタ部４に浸入するのを防止する機能を有し、例えばＳｉＮｘやＳｉＯ２で形成される。尚、無機絶縁層９としてＳｉＮｘを使用する場合は、ＳｉとＮのモル比が３：４の化学量論組成であるＳｉ３Ｎ４の他、必要に応じ化学量論組成から偏移した化合物を使用することができる。 The capacitor unit 4 is entirely covered with an insulating layer 8. The insulating layer 8 includes an inorganic insulating layer 9 and an organic insulating layer 10. The inorganic insulating layer 9 has a function of preventing moisture from the outside from entering the capacitor unit 4 and is made of, for example, SiN x or SiO 2 . In the case of using SiN x as the inorganic insulating layer 9, the molar ratio of Si and N 3: Other 4 stoichiometry having a composition Si 3 N 4, and deviates from the stoichiometric composition as required Compounds can be used.
　また、有機絶縁層１０は、ポリイミド樹脂やエポキシ樹脂で形成され、後述する電極配線や基板配線からの機械的応力を吸収する。 The organic insulating layer 10 is formed of a polyimide resin or an epoxy resin, and absorbs mechanical stress from electrode wiring and substrate wiring described later.
　第１の電極層５は基板配線１１に接続されると共に、第２の電極層７は電極配線１２に接続されている。 The first electrode layer 5 is connected to the substrate wiring 11, and the second electrode layer 7 is connected to the electrode wiring 12.
　基板配線１１は、具体的には、第１の電極層５の上面から絶縁層８（無機絶縁層９及び有機絶縁層１）を貫通し、有機絶縁層１０上から絶縁層８の側面に架けて連設され、導電性基板１上にオーミック接触された第１の接続電極１４に電気的に接続されている。 Specifically, the substrate wiring 11 penetrates the insulating layer 8 (the inorganic insulating layer 9 and the organic insulating layer 1) from the upper surface of the first electrode layer 5, and extends from the organic insulating layer 10 to the side surface of the insulating layer 8. And electrically connected to the first connection electrode 14 that is in ohmic contact with the conductive substrate 1.
　また、電極配線１２は、第２の電極層７の上面から絶縁層８（無機絶縁層９及び有機絶縁層１）を貫通し、かつ有機絶縁層１０上に配されるように形成されている。 The electrode wiring 12 is formed so as to penetrate the insulating layer 8 (inorganic insulating layer 9 and organic insulating layer 1) from the upper surface of the second electrode layer 7 and to be disposed on the organic insulating layer 10. .
　そして、前記電極配線１２の上面には上部外部電極（第１の外部電極）１５が形成され、第２の電極層７は電極配線１２を介して上部外部電極１５と電気的に接続されている。 An upper external electrode (first external electrode) 15 is formed on the upper surface of the electrode wiring 12, and the second electrode layer 7 is electrically connected to the upper external electrode 15 through the electrode wiring 12. .
　また、導電性基板１の上面側は、上部外部電極１５を除く部分は、保護樹脂１８で被覆されている。 Further, the upper surface side of the conductive substrate 1 is covered with a protective resin 18 except for the upper external electrode 15.
　さらに、導電性基板１の他方の主面上には第２の接続電極１６が形成され、該第２の接続電極１６上には下部外部電極（第２の外部電極）１７が形成されている。 Further, a second connection electrode 16 is formed on the other main surface of the conductive substrate 1, and a lower external electrode (second external electrode) 17 is formed on the second connection electrode 16. .
　尚、第１及び第２の接続電極１４、１６は、導電性基板１とオーミック接触させてＥＳＲを下げる必要があることから、Ａｕで形成するのが好ましい。 Note that the first and second connection electrodes 14 and 16 are preferably formed of Au because it is necessary to lower the ESR by making ohmic contact with the conductive substrate 1.
　また、上部外部電極１５及び下部外部電極１７は複層構造が好ましく、例えばＡｕ／Ｃｕ、Ａｕ／Ｎｉ、Ｓｎ／Ｃｕを使用することができる。 Further, the upper external electrode 15 and the lower external electrode 17 preferably have a multilayer structure, and for example, Au / Cu, Au / Ni, Sn / Cu can be used.
　このように本誘電体薄膜キャパシタは、下部外部電極１７が、第２の接続電極１６、導電性基板１、第１の接続電極１４、基板配線１１を介して第１の電極層５と電気的に接続され、上部外部電極１５は、電極配線１２を介して第２の電極層７と電気的に接続されている。そして、上部外部電極１５と下部外部電極１７との間に電圧が印加されると、キャパシタ部４はキャパシタとしての機能を発揮する。 Thus, in this dielectric thin film capacitor, the lower external electrode 17 is electrically connected to the first electrode layer 5 via the second connection electrode 16, the conductive substrate 1, the first connection electrode 14, and the substrate wiring 11. The upper external electrode 15 is electrically connected to the second electrode layer 7 through the electrode wiring 12. When a voltage is applied between the upper external electrode 15 and the lower external electrode 17, the capacitor unit 4 functions as a capacitor.
　次に、誘電体薄膜キャパシタの製造方法を詳述する。 Next, a method for manufacturing a dielectric thin film capacitor will be described in detail.
　まず、図２（ａ）に示すように、例えば、厚さが５２５μｍのｐ型導電性Ｓｉ基板等からなる導電性基板１を用意する。 First, as shown in FIG. 2A, a conductive substrate 1 made of, for example, a p-type conductive Si substrate having a thickness of 525 μm is prepared.
　次いで、図２（ｂ）に示すように、拡散防止層２及び密着層３を順次成膜する。 Next, as shown in FIG. 2B, the diffusion prevention layer 2 and the adhesion layer 3 are sequentially formed.
　すなわち、例えば、熱酸化法により膜厚７００ｎｍのＳｉＯ２等からなる拡散防止層２を成膜する。 That is, for example, the diffusion prevention layer 2 made of SiO 2 or the like having a thickness of 700 nm is formed by a thermal oxidation method.
　次いで、化学溶液堆積（Chemical Solution Deposition；以下「ＣＳＤ」という。）法等により拡散防止層２上に、例えば膜厚１００ｎｍの密着層３を形成する。密着層３としては、ＢＳＴ、ＳｒＴｉＯ３、ＢａＴｉＯ３や、Ｐｂ（Ｚｒ，Ｔｉ）Ｏ３等のペロブスカイト化合物、ＳｒＢｉ４Ｔｉ４Ｏ15等のビスマス層状化合物等を使用することができるが、例えば、ＢＳＴで密着層３を形成する場合は、以下のようにして作製することができる。 Next, an adhesion layer 3 of, eg, a 100 nm-thickness is formed on the diffusion prevention layer 2 by a chemical solution deposition (hereinafter referred to as “CSD”) method or the like. As the adhesion layer 3, BST, SrTiO 3 , BaTiO 3 , perovskite compounds such as Pb (Zr, Ti) O 3 , bismuth layered compounds such as SrBi 4 Ti 4 O 15, etc. can be used. When the adhesion layer 3 is formed by BST, it can be produced as follows.
　すなわち、まず、Ｂａ、Ｓｒ、Ｔｉが、モル比で例えばＢａ：Ｓｒ：Ｔｉ＝７：３：１０に配合された成膜原料溶液を用意する。次いで、この成膜原料溶液を拡散防止層２上に塗布し、３００～４００℃のホットプレ－ト上で乾燥させ、６５０℃の温度で３０分間、高速昇温熱処理を行って結晶化させ、これにより密着層３を形成する。 That is, first, a film forming raw material solution in which Ba, Sr, and Ti are mixed at a molar ratio of, for example, Ba: Sr: Ti = 7: 3: 10 is prepared. Next, this film forming raw material solution is applied onto the diffusion preventing layer 2, dried on a hot plate at 300 to 400 ° C., and subjected to crystallization at high temperature heating treatment at a temperature of 650 ° C. for 30 minutes. Thus, the adhesion layer 3 is formed.
　次に、図２（ｃ）に示すように、第１の電極層５、誘電体層６、及び第２の電極層７を順次成膜する。 Next, as shown in FIG. 2C, a first electrode layer 5, a dielectric layer 6, and a second electrode layer 7 are sequentially formed.
　すなわち、例えば、ＲＦマグネトロンスパッタ法等により膜厚２００ｎｍのＰｔからなる第１の電極層５を形成し、次いで、密着層３と同様、ＣＳＤ法等によりＢＳＴ等からなる膜厚１００ｎｍの誘電体層６を形成し、その後、第１の電極層５と同様、ＲＦマグネトロンスパッタ法等により膜厚２００ｎｍのＰｔからなる第２の電極層６を形成する。 That is, for example, the first electrode layer 5 made of Pt having a film thickness of 200 nm is formed by RF magnetron sputtering or the like, and then the dielectric layer having a film thickness of 100 nm made of BST or the like by the CSD method or the like, similar to the adhesion layer 3. 6 is formed, and then, similarly to the first electrode layer 5, a second electrode layer 6 made of Pt having a thickness of 200 nm is formed by an RF magnetron sputtering method or the like.
　次に、図２（ｄ）に示すように、上記密着層３、第１の電極層５、誘電体層６、及び第２の電極層７を、周知のフォトリソグラフィー技術及びアルゴンイオンミリング法等を使用して所定パターンにエッチングし、キャパシタ部４を形成する。すなわち、フォトレジストを塗布してプリベークした後、フォトマスクを介して紫外光をフォトレジストに照射し、露光、現像、ポストベークを行なってフォトマスクパターンをレジストパターンに転写する。次いで、アルゴンイオンミリング法によりアルゴンイオンをエッチング面に衝突させて第２の電極層７、誘電体層６、第１の電極層５、及び密着層３の所定領域をエッチングし、これによりキャパシタ部４を作製する。 Next, as shown in FIG. 2D, the adhesion layer 3, the first electrode layer 5, the dielectric layer 6, and the second electrode layer 7 are formed by using a well-known photolithography technique, an argon ion milling method, or the like. Is etched into a predetermined pattern to form the capacitor portion 4. That is, after a photoresist is applied and prebaked, the photoresist is irradiated with ultraviolet light through a photomask, and exposure, development, and postbaking are performed to transfer the photomask pattern to the resist pattern. Next, argon ions are collided with the etching surface by an argon ion milling method to etch predetermined regions of the second electrode layer 7, the dielectric layer 6, the first electrode layer 5, and the adhesion layer 3, and thereby the capacitor portion 4 is produced.
　次いで、キャパシタ部４を熱処理し、誘電体層６の誘電特性を向上させる。この熱処理は、誘電体層６の結晶性を向上させるために行うものであり、例えば８５０℃の温度で３０分間熱処理を行う。また、誘電体層６に酸素欠陥が多いと、高温時の電圧負荷に耐えられず、信頼性が低下するおそれがあることから、酸素含有雰囲気中で熱処理を行うのが好ましい。 Next, the capacitor portion 4 is heat-treated to improve the dielectric characteristics of the dielectric layer 6. This heat treatment is performed to improve the crystallinity of the dielectric layer 6, and is performed at a temperature of, for example, 850 ° C. for 30 minutes. In addition, if the dielectric layer 6 has a large number of oxygen defects, the dielectric layer 6 cannot withstand a voltage load at a high temperature and the reliability may be lowered. Therefore, the heat treatment is preferably performed in an oxygen-containing atmosphere.
　次に、図３（ｅ）に示すように、キャパシタ部４の全体を覆うように、無機絶縁層９及び有機絶縁層１０からなる絶縁層８を形成する。すなわち、例えば、スパッタ法により厚さ５００ｎｍのＳｉＮｘ等からなる無機絶縁層９を成膜する。次いで、感光性ポリイミドを前記無機絶縁層９の上面を覆うように塗布し、その後、１２５℃の温度で５分間加熱し、露光、現像処理を行った後、３５０℃で１時間程度加熱し、例えば膜厚が５０００ｎｍの所定パターンの有機絶縁層１０を形成する。 Next, as illustrated in FIG. 3E, an insulating layer 8 including an inorganic insulating layer 9 and an organic insulating layer 10 is formed so as to cover the entire capacitor unit 4. That is, for example, the inorganic insulating layer 9 made of SiN x or the like having a thickness of 500 nm is formed by sputtering. Next, a photosensitive polyimide is applied so as to cover the upper surface of the inorganic insulating layer 9, and then heated at a temperature of 125 ° C. for 5 minutes, exposed and developed, and then heated at 350 ° C. for about 1 hour. For example, the organic insulating layer 10 having a predetermined pattern with a film thickness of 5000 nm is formed.
　次に、図３（ｆ）に示すように、感光性ポリイミドからなる有機絶縁層１０をマスクとし、反応性イオンエッチング法により無機絶縁層９を加工して孔１９、２０を形成し、第１及び第２の電極層５、７の一部を表面露出させる。 Next, as shown in FIG. 3 (f), the organic insulating layer 10 made of photosensitive polyimide is used as a mask, the inorganic insulating layer 9 is processed by reactive ion etching to form holes 19 and 20, and the first Then, a part of the second electrode layers 5 and 7 is exposed on the surface.
　次に、所定のレジストパターンを形成した後、バッファードフッ酸で拡散防止層２の一部を溶解除去し、導電性基板１の一部を表面露出させる。 Next, after forming a predetermined resist pattern, a part of the diffusion preventing layer 2 is dissolved and removed with buffered hydrofluoric acid to expose a part of the conductive substrate 1 on the surface.
　その後、真空蒸着法により導電性基板１の表面露出部分に例えば膜厚３００ｎｍのＡｕを蒸着させ、リフトオフ法によりフォトレジストを除去し、図３（ｇ）に示すように、第１の接続電極１４を形成する。 Thereafter, Au having a film thickness of, for example, 300 nm is deposited on the surface exposed portion of the conductive substrate 1 by a vacuum deposition method, and the photoresist is removed by a lift-off method, and as shown in FIG. Form.
　次に、図４（ｈ）に示すように、孔２０の内面から有機絶縁層１０の上面及び側面さらには第１の接続電極１４上に架けて基板配線１１を形成し、孔１９の内面から有機絶縁層１０の上面に架けて電極配線１２を形成する。そしてこの後電極配線１２の上部に、上部外部電極１５を形成する。 Next, as shown in FIG. 4 (h), the substrate wiring 11 is formed from the inner surface of the hole 20 to the upper surface and side surfaces of the organic insulating layer 10 and further to the first connection electrode 14, and from the inner surface of the hole 19. An electrode wiring 12 is formed over the upper surface of the organic insulating layer 10. Thereafter, an upper external electrode 15 is formed on the electrode wiring 12.
　これら基板配線１１、電極配線１２、及び上部外部電極１５は、具体的には以下のようにして作製される。 The substrate wiring 11, the electrode wiring 12, and the upper external electrode 15 are specifically produced as follows.
　すなわち、まず、スパッタ法により膜厚１００ｎｍからなるＴｉ層を表面に成膜し、該Ｔｉ層上に膜厚５００ｎｍからなるＣｕ層を成膜する。次に、Ｃｕ層上に開口部を有するように、該Ｃｕ層上にフォトレジストを塗布して所定のレジストパターンを形成し、次いで、電解めっきを行って前記開口部に膜厚２０００ｎｍのＮｉ層及び膜厚１０００ｎｍのＡｕ層を順次形成する。そして、前記フォトレジストを除去してＡｕ層及びＮｉ層からなる二層構造の上部外部電極１５を形成する。 That is, first, a Ti layer having a thickness of 100 nm is formed on the surface by sputtering, and a Cu layer having a thickness of 500 nm is formed on the Ti layer. Next, a photoresist is applied on the Cu layer so as to have an opening on the Cu layer to form a predetermined resist pattern, and then electrolytic plating is performed to form a Ni layer having a thickness of 2000 nm in the opening. Then, an Au layer having a thickness of 1000 nm is sequentially formed. Then, the photoresist is removed to form an upper external electrode 15 having a two-layer structure composed of an Au layer and a Ni layer.
　次に、再び、電極配線１２となるべき部位と基板配線１１となるべき部位とが離間するように、Ｃｕ層上にフォトレジストを塗布して所定のレジストパターンを形成し、次いで、ウェットエッチングによりＣｕ層及びＴｉ層をエッチングする。そしてその後、フォトレジストを除去し、Ｃｕ層及びＴｉ層からなる二層構造の電極配線１２及び基板配線１１を形成する。 Next, a predetermined resist pattern is formed by applying a photoresist on the Cu layer so that the portion to be the electrode wiring 12 and the portion to be the substrate wiring 11 are separated from each other, and then wet etching is performed. Etch Cu layer and Ti layer. Thereafter, the photoresist is removed, and an electrode wiring 12 and a substrate wiring 11 having a two-layer structure composed of a Cu layer and a Ti layer are formed.
　次いで、図４（ｉ）に示すように、導電性基板１上の上部外部電極１５を除く部分を保護樹脂層１８で被覆する。 Next, as shown in FIG. 4 (i), the portion excluding the upper external electrode 15 on the conductive substrate 1 is covered with a protective resin layer 18.
　すなわち、感光性ポリイミド等の感光性樹脂を上面に塗布し、その後、１２５℃の温度で５分間加熱し、露光、現像処理を行った後、３５０℃で１時間程度加熱し、例えば膜厚が５０００ｎｍの所定パターンの保護樹脂層１８を形成する。 That is, a photosensitive resin such as photosensitive polyimide is applied to the upper surface, and then heated at 125 ° C. for 5 minutes, exposed and developed, and then heated at 350 ° C. for about 1 hour. A protective resin layer 18 having a predetermined pattern of 5000 nm is formed.
　次に、図４（ｊ）に示すように、導電性基板１の他方の主面上に第２の接続電極１６を形成し、第２の接続電極１６上に下部外部電極１７を形成する。 Next, as shown in FIG. 4 (j), the second connection electrode 16 is formed on the other main surface of the conductive substrate 1, and the lower external electrode 17 is formed on the second connection electrode 16.
　すなわち、まず、導電性基板１の裏面を所定厚みとなるように研削し、バッファードフッ酸で処理し、真空蒸着法により膜厚３００ｎｍのＡｕからなる第２の接続電極１６を形成する。次に、電解めっきを行なって膜厚２０００ｎｍのＮｉ層及び膜厚１０００ｎｍのＡｕ層を順次成膜し、これにより二層構造の下部外部電極１７を形成する。 That is, first, the back surface of the conductive substrate 1 is ground to a predetermined thickness, treated with buffered hydrofluoric acid, and a second connection electrode 16 made of Au having a thickness of 300 nm is formed by vacuum deposition. Next, electrolytic plating is performed to sequentially form a 2000 nm thick Ni layer and a 1000 nm thick Au layer, thereby forming a lower external electrode 17 having a two-layer structure.
　最後に、より確実なオーミック接触を得るために３５０℃の温度で熱処理を行い、下部外部電極１７と導電性基板１との界面を安定化させ、これにより誘電体薄膜キャパシタが得られる。 Finally, in order to obtain a more reliable ohmic contact, heat treatment is performed at a temperature of 350 ° C. to stabilize the interface between the lower external electrode 17 and the conductive substrate 1, thereby obtaining a dielectric thin film capacitor.
　このように本第１の実施の形態では、キャパシタ部４を熱処理した後に基板配線１１を形成するため、基板配線１１が熱処理雰囲気に晒されて酸化されることもない。したがって熱処理を行ってもキャパシタ部４の信頼性を損なうこともなく、ＥＳＲの増加を抑制することができる。 As described above, in the first embodiment, since the substrate wiring 11 is formed after the capacitor portion 4 is heat-treated, the substrate wiring 11 is not exposed to the heat treatment atmosphere and oxidized. Therefore, even if heat treatment is performed, the increase in ESR can be suppressed without impairing the reliability of the capacitor unit 4.
　また、第２の電極層７と導電性基板１とを直接に電気的接続させるのではなく、基板配線１１を介して電気的接続させているので、基板配線１１を十分に厚くしたり、基板配線１１にＡｕやＣｕ等の低抵抗の導電性材料を使用することが可能であり、前記第２の電極層７から第２の外部電極１７までの間の抵抗を十分に低減することが可能である。すなわち、配線の材質や形状の選定、長さの調整の自由度の大きい高容量、高信頼性・低ＥＳＲの誘電体薄膜キャパシタを得ることができる。 Further, since the second electrode layer 7 and the conductive substrate 1 are not directly electrically connected but via the substrate wiring 11, the substrate wiring 11 can be made sufficiently thick, A low resistance conductive material such as Au or Cu can be used for the wiring 11, and the resistance between the second electrode layer 7 and the second external electrode 17 can be sufficiently reduced. It is. That is, it is possible to obtain a high-capacity, high-reliability, low-ESR dielectric thin film capacitor with a high degree of freedom in selecting the material and shape of the wiring and adjusting the length.
　また、基板配線１１を形成する前にキャパシタ部４を絶縁層８で被覆しているので、配線形成時のエッチングによるキャパシタ特性の劣化を防ぐことができる。 In addition, since the capacitor portion 4 is covered with the insulating layer 8 before the substrate wiring 11 is formed, deterioration of the capacitor characteristics due to etching during wiring formation can be prevented.
　図５は、本発明の第２の実施の形態を示す誘電体薄膜キャパシタの断面図であって、該第２の実施の形態は、導電性基板１の一方の主面側に２個のキャパシタ部２１ａ、２１ｂが形成され、かつ各キャパシタ部２１ａ、２１ｂは電極層と誘電体操とが交互に積層され、複数の容量発生部を有している。 FIG. 5 is a cross-sectional view of a dielectric thin film capacitor showing a second embodiment of the present invention. The second embodiment has two capacitors on one main surface side of the conductive substrate 1. The portions 21a and 21b are formed, and the capacitor portions 21a and 21b are alternately laminated with electrode layers and dielectric layers, and have a plurality of capacitance generating portions.
　すなわち、導電性基板１上に形成された拡散防止層２上には、無機絶縁層２２を挟んで２個の密着層２３ａ、２３ｂが形成されている。そして、それぞれの密着層２３ａ、２３ｂ上には第１の電極層２４ａ、２４ｂ、第１の誘電体層２５ａ、２５ｂ、第２の電極層２６ａ、２６ｂ、第２の誘電体層２７ａ、２７ｂ、第３の電極層２８ａ、２８ｂ、第３の誘電体層２９ａ、２９ｂ、及び第４の電極層３０ａ、３０ｂが順次積層されてキャパシタ部２１ａ、２１ｂを形成している。そして、キャパシタ部２１ａ、２１ｂの最上層の第４の電極層３０ａ、３０ｂの表面に、第４の誘電体層３１ａ、３１ｂが形成されている。また、無機絶縁層２２は有機絶縁層３２で被覆されている。 That is, two adhesion layers 23 a and 23 b are formed on the diffusion prevention layer 2 formed on the conductive substrate 1 with the inorganic insulating layer 22 interposed therebetween. The first electrode layers 24a, 24b, the first dielectric layers 25a, 25b, the second electrode layers 26a, 26b, the second dielectric layers 27a, 27b, Third electrode layers 28a and 28b, third dielectric layers 29a and 29b, and fourth electrode layers 30a and 30b are sequentially stacked to form capacitor portions 21a and 21b. The fourth dielectric layers 31a and 31b are formed on the surfaces of the uppermost fourth electrode layers 30a and 30b of the capacitor portions 21a and 21b. The inorganic insulating layer 22 is covered with an organic insulating layer 32.
　また、基板配線３３ａ、３３ｂ及び電極配線３５ａ、３５ｂは、第１の実施の形態と略同様の形状を有するように形成され、基板配線３３ａ、３３ｂは、導電性基板１にオーミック接触された第１の接続電極３４ａ、３４ｂに電気的に接続されている。 The substrate wirings 33a and 33b and the electrode wirings 35a and 35b are formed so as to have substantially the same shape as in the first embodiment, and the substrate wirings 33a and 33b are in ohmic contact with the conductive substrate 1. One connection electrode 34a, 34b is electrically connected.
　そして、第１の電極層２４ａ、２４ｂは、基板配線３３ａ、３３ｂ、第１の接続電極３４ａ、３４ｂ、導電性基板１、及び第２の接続電極１６を介して下部外部電極１７に電気的に接続されると共に、第４の電極層３０ａ、３０ｂは、電極配線３５ａ、３５ｂを介して上部外部電極３６ａ、３６ｂに電気的に接続されている。また、本誘電体薄膜キャパシタは、導電性基板１のキャパシタ部２１ａ、２１ｂ側は、上部外部電極３６ａ、３６ｂを除く全体が保護樹脂層３７で被覆されている。 The first electrode layers 24 a and 24 b are electrically connected to the lower external electrode 17 through the substrate wirings 33 a and 33 b, the first connection electrodes 34 a and 34 b, the conductive substrate 1, and the second connection electrode 16. In addition to being connected, the fourth electrode layers 30a and 30b are electrically connected to the upper external electrodes 36a and 36b via the electrode wirings 35a and 35b. Further, in the present dielectric thin film capacitor, the entire capacitor substrate 21a, 21b side of the conductive substrate 1 is covered with a protective resin layer 37 except for the upper external electrodes 36a, 36b.
　そして、本第２の実施の形態においても、基板配線３３ａ、３３ｂを形成する前に、キャパシタ部２１ａ、２１ｂの熱処理が行なわれ、これによりキャパシタ部の信頼性を損なうことなく、ＥＳＲの増加を抑制している。 Also in the second embodiment, the heat treatment of the capacitor portions 21a and 21b is performed before the substrate wirings 33a and 33b are formed, thereby increasing the ESR without impairing the reliability of the capacitor portions. Suppressed.
　しかも、本第２の実施の形態では、キャパシタ部２１ａ、２１ｂが複数の容量発生部を有しているので、耐電圧を向上させた薄膜キャパシタを得ることができる。また、第４の誘電体層３１ａ、３１ｂをキャパシタ部２１ａ、２１ｂ上に形成しているので、無機絶縁層２２の成膜時のキャパシタの劣化を防ぐことができ、リーク電流を抑制することが可能となる。 Moreover, in the second embodiment, since the capacitor portions 21a and 21b have a plurality of capacitance generating portions, a thin film capacitor with improved withstand voltage can be obtained. Further, since the fourth dielectric layers 31a and 31b are formed on the capacitor portions 21a and 21b, it is possible to prevent deterioration of the capacitor during the formation of the inorganic insulating layer 22, and to suppress the leakage current. It becomes possible.
　図６は、本発明の第３の実施の形態を示す誘電体薄膜キャパシタの断面図であって、本第３の実施の形態では、導電性基板１上に形成された拡散防止層２上に密着層２３、第１の電極層２４、及び第１の誘電体層２５が順次形成され、この第１の誘電体層２５上に電極層と誘電体層とが交互に積層されてキャパシタ部を形成している。 FIG. 6 is a cross-sectional view of a dielectric thin film capacitor showing a third embodiment of the present invention. In the third embodiment, the dielectric thin film capacitor is formed on the diffusion prevention layer 2 formed on the conductive substrate 1. An adhesion layer 23, a first electrode layer 24, and a first dielectric layer 25 are sequentially formed, and electrode layers and dielectric layers are alternately stacked on the first dielectric layer 25 to form a capacitor portion. Forming.
　すなわち、前記第１の誘電体層２５上に無機絶縁層２２を介して第２の電極層２６ａ、２６ｂ、第２の誘電体層２７ａ、２７ｂ、第３の電極層２８ａ、２８ｂ、第３の誘電体層２９ａ、２９ｂ、及び第４の電極層３０ａ、３０ｂが順次積層され、これら第１～第４の誘電体層２５、２７ａ、２７ｂ、２９ａ、２９ｂ及び第１の電極層２４、２６ａ、２６ｂ、２８ａ、２８ｂ、３０ａ、３０ｂでキャパシタ部を形成している。 That is, on the first dielectric layer 25, the second electrode layers 26a and 26b, the second dielectric layers 27a and 27b, the third electrode layers 28a and 28b, and the third electrode layer are interposed via the inorganic insulating layer 22. The dielectric layers 29a, 29b and the fourth electrode layers 30a, 30b are sequentially stacked. The first to fourth dielectric layers 25, 27a, 27b, 29a, 29b and the first electrode layers 24, 26a, 26b, 28a, 28b, 30a, 30b form a capacitor portion.
　そして、本第３の実施の形態においても、基板配線３３ａ、３３ｂを形成する前に、キャパシタ部の熱処理が行なわれ、これによりキャパシタ部の信頼性を損なうことなく、ＥＳＲの増加を抑制している。 Also in the third embodiment, heat treatment of the capacitor portion is performed before the formation of the substrate wirings 33a and 33b, thereby suppressing an increase in ESR without impairing the reliability of the capacitor portion. Yes.
　しかも、本第３の実施の形態においても、第２の実施の形態と同様、複数の容量発生部を有するキャパシタ部を備えているので、耐電圧を向上させた薄膜キャパシタを形成することができる。また、第４の誘電体層３１ａ、３１ｂをキャパシタ部上に形成しているので、無機絶縁層２２成膜時のキャパシタ劣化を防ぐことができ、リーク電流を抑制することが可能となる。 Moreover, since the third embodiment also includes a capacitor section having a plurality of capacitance generating sections, as in the second embodiment, a thin film capacitor with improved withstand voltage can be formed. . Further, since the fourth dielectric layers 31a and 31b are formed on the capacitor portion, it is possible to prevent the capacitor from being deteriorated when the inorganic insulating layer 22 is formed, and to suppress the leakage current.
　そして、これら第２及び第３の実施の形態においても、誘電体層や電極層の積層数、及び誘電体層、電極層、電極配線、基板配線の形成パターンを適宜調整する以外は、第１の実施の形態と同様に製造することができる。 In the second and third embodiments, the first and second embodiments except that the number of laminated dielectric layers and electrode layers and the formation pattern of the dielectric layers, electrode layers, electrode wirings, and substrate wirings are adjusted as appropriate. It can be manufactured in the same manner as in the embodiment.
　図７は本発明の第４の実施の形態を示す誘電体薄膜キャパシタの断面図であって、本第４の実施の形態では、有機絶縁層１０上に平坦状に薄膜抵抗４２が形成されると共に、第２の電極層７は電極配線１２を介して薄膜抵抗４２と電気的に接続されている。さらに、電極配線１２は上部外部電極を兼ねると共に、薄膜抵抗４２は、別の上部外部電極４１と電気的に接続されている。 FIG. 7 is a cross-sectional view of a dielectric thin film capacitor showing a fourth embodiment of the present invention. In the fourth embodiment, a thin film resistor 42 is formed flat on the organic insulating layer 10. At the same time, the second electrode layer 7 is electrically connected to the thin film resistor 42 via the electrode wiring 12. Further, the electrode wiring 12 also serves as an upper external electrode, and the thin film resistor 42 is electrically connected to another upper external electrode 41.
　すなわち、この第４の実施の形態は、第１の実施の形態と同様、導電性基板１の一方の主面にはＳｉＯ２等からなる拡散防止層２が形成されると共に、該拡散防止層２の表面には密着層３が形成され、さらに、該密着層３の表面には第１の電極層５、誘電体層６及び第２の電極層７からなるキャパシタ部４が形成されている。 That is, in the fourth embodiment, similarly to the first embodiment, a diffusion prevention layer 2 made of SiO 2 or the like is formed on one main surface of the conductive substrate 1, and the diffusion prevention layer is formed. An adhesion layer 3 is formed on the surface 2, and a capacitor portion 4 including a first electrode layer 5, a dielectric layer 6, and a second electrode layer 7 is formed on the surface of the adhesion layer 3. .
　また、キャパシタ部４は、第１の実施の形態と同様、無機絶縁層９と有機絶縁層１０とからなる絶縁層８で被覆されている。 Further, the capacitor portion 4 is covered with an insulating layer 8 composed of an inorganic insulating layer 9 and an organic insulating layer 10 as in the first embodiment.
　また、基板配線１１及び電極配線１２も、第１の実施の形態と略同様の形状に形成され、第１の電極層５は基板配線１１に接続されると共に、第２の電極層７は電極配線１２に接続されている。ただし、この第４の実施の形態では、電極配線１２は、上述したように上部外部電極を兼ねている。 The substrate wiring 11 and the electrode wiring 12 are also formed in substantially the same shape as in the first embodiment, and the first electrode layer 5 is connected to the substrate wiring 11 and the second electrode layer 7 is an electrode. It is connected to the wiring 12. However, in the fourth embodiment, the electrode wiring 12 also serves as the upper external electrode as described above.
　そして、有機絶縁層１０の表面には、別の上部外部電極４１が形成され、この上部外部電極４１と電極配線１２とが薄膜抵抗４２を介して電気的に接続されている。 Further, another upper external electrode 41 is formed on the surface of the organic insulating layer 10, and the upper external electrode 41 and the electrode wiring 12 are electrically connected via a thin film resistor 42.
　そして、導電性基板１は、電極配線１２及び上部外部電極４１の部分を除き、全体が保護樹脂層４３で被覆されている。 The conductive substrate 1 is entirely covered with a protective resin layer 43 except for the electrode wiring 12 and the upper external electrode 41.
　次に、上記第４の実施の形態の製造方法を、図８及び図９に基づき詳述する。 Next, the manufacturing method according to the fourth embodiment will be described in detail with reference to FIGS.
　まず、第１の実施の形態と同様、導電性基板１上に拡散防止層２、密着層３、第１の電極層５、誘電体層６、及び第２の電極層６を順次形成し、周知のフォトリソグラフィー技術及びアルゴンイオンミリング法等を使用して所定パターンにエッチングし、キャパシタ部４を形成する。そして、誘電体層６の誘電特性を向上させるためにキャパシタ部４を酸素含有雰囲気中で熱処理する。次いで、キャパシタ部４を被覆するように無機絶縁層９、有機絶縁層１０からなる絶縁層８を形成し、反応性イオンエッチング法により無機絶縁層９を加工する。そして、図８（ａ）に示すように、孔１９、２０を形成し、第１及び第２の電極層５、７の一部を表面露出させる。 First, as in the first embodiment, the diffusion prevention layer 2, the adhesion layer 3, the first electrode layer 5, the dielectric layer 6, and the second electrode layer 6 are sequentially formed on the conductive substrate 1, The capacitor portion 4 is formed by etching into a predetermined pattern using a known photolithography technique and an argon ion milling method. And in order to improve the dielectric characteristic of the dielectric material layer 6, the capacitor | condenser part 4 is heat-processed in oxygen-containing atmosphere. Next, an insulating layer 8 composed of an inorganic insulating layer 9 and an organic insulating layer 10 is formed so as to cover the capacitor portion 4, and the inorganic insulating layer 9 is processed by a reactive ion etching method. And as shown to Fig.8 (a), the holes 19 and 20 are formed and a part of 1st and 2nd electrode layers 5 and 7 are surface-exposed.
　次に、図８（ｂ）に示すように、スパッタ法により膜厚４０～６０ｎｍのＴａＮやＮｉ－Ｃｒ合金からなる薄膜層を成膜する。次に、フォトレジストを塗布して所定のレジストパターンを形成した後、反応性イオンエッチングにより所定領域をエッチング除去し、薄膜抵抗４２を形成し、その後、フォトレジストを溶解除去する。 Next, as shown in FIG. 8B, a thin film layer made of TaN or Ni—Cr alloy having a film thickness of 40 to 60 nm is formed by sputtering. Next, after applying a photoresist to form a predetermined resist pattern, a predetermined region is etched away by reactive ion etching to form a thin film resistor 42, and then the photoresist is dissolved and removed.
　次いで、再び、フォトレジストを塗布して所定のレジストパターンを形成した後、バッファードフッ酸で拡散防止層２の一部を溶解除去し、導電性基板１の一部を表面露出させる。 Next, after applying a photoresist again to form a predetermined resist pattern, a part of the diffusion preventing layer 2 is dissolved and removed with buffered hydrofluoric acid, and a part of the conductive substrate 1 is exposed on the surface.
　その後、真空蒸着法により導電性基板１の表面露出部分に例えば膜厚３００ｎｍのＡｕを成膜させた後、リフトオフ法によりフォトレジストを除去し、図８（ｃ）に示すように、第１の接続電極１４を形成する。 Thereafter, Au having a film thickness of 300 nm, for example, is formed on the surface exposed portion of the conductive substrate 1 by a vacuum deposition method, and then the photoresist is removed by a lift-off method. As shown in FIG. A connection electrode 14 is formed.
　次に、スパッタ法により膜厚１００ｎｍのＴｉ層及び膜厚５００ｎｍのＡｕ層を成膜し、次いで、フォトレジストを塗布してレジストパターンを形成し、ウェットエッチングによりＡｕ層及びＴｉ層を加工し、フォトレジストを除去し、これにより、図９（ｄ）に示すように、基板配線１１、電極配線１２及び上部外部電極４１を形成する。その後、空気中、３７０℃で３０分間熱処理し、薄膜抵抗４２を酸化させ、安定化処理を行なう。 Next, a 100 nm thick Ti layer and a 500 nm thick Au layer are formed by sputtering, then a photoresist is applied to form a resist pattern, and the Au layer and Ti layer are processed by wet etching. The photoresist is removed, thereby forming the substrate wiring 11, the electrode wiring 12, and the upper external electrode 41 as shown in FIG. 9D. Thereafter, heat treatment is performed in air at 370 ° C. for 30 minutes to oxidize the thin film resistor 42 and perform stabilization treatment.
　その後、第１の実施の形態と同様の方法・手順により、図９（ｅ）に示すように、上部外部電極４１及び電極配線１２を除く全体を覆うように保護樹脂層４３で被覆する。 Thereafter, as shown in FIG. 9 (e), the protective resin layer 43 is covered so as to cover the whole except for the upper external electrode 41 and the electrode wiring 12 by the same method and procedure as in the first embodiment.
　次に、第１の実施の形態と同様の方法・手順で、図９（ｆ）に示すように、導電性基板１の他方の主面上に第２の接続電極１６を形成し、第２の接続電極１６上に下部外部電極１７を形成する。 Next, as shown in FIG. 9F, the second connection electrode 16 is formed on the other main surface of the conductive substrate 1 by the same method and procedure as in the first embodiment, and the second A lower external electrode 17 is formed on the connection electrode 16.
　このように本第４の実施の形態では、第１の実施の形態の作用効果に加え、薄膜抵抗４２を付加することにより、抵抗機能を複合させた高容量・高信頼性・低ＥＳＲの薄膜キャパシタを実現することが可能となる。 As described above, in the fourth embodiment, in addition to the function and effect of the first embodiment, a thin film resistor 42 is added, so that a thin film having a high capacity, high reliability, and low ESR combined with a resistance function. A capacitor can be realized.
　また、薄膜抵抗をキャパシタ部４上に形成しているので、素子の大型化を招くのを極力回避できる。 In addition, since the thin film resistor is formed on the capacitor portion 4, it is possible to avoid the increase in the size of the element as much as possible.
　また、薄膜抵抗４２を平坦状に形成しているので、抵抗値にバラツキが生じるのを抑制することができる。 Further, since the thin film resistor 42 is formed in a flat shape, it is possible to suppress variation in the resistance value.
　図１０は、第５の実施の形態を示す誘電体薄膜キャパシタの断面図である。 FIG. 10 is a cross-sectional view of a dielectric thin film capacitor showing a fifth embodiment.
　すなわち、この第５の実施の形態では、拡散防止層２上に薄膜抵抗４６を形成し、電極配線４７と上部外部電極４５とが拡散防止層２の面上で前記薄膜抵抗４６と電気的に接続されている。 That is, in the fifth embodiment, the thin film resistor 46 is formed on the diffusion preventing layer 2, and the electrode wiring 47 and the upper external electrode 45 are electrically connected to the thin film resistor 46 on the surface of the diffusion preventing layer 2. It is connected.
　この第５の実施の形態のように拡散防止層２上に薄膜抵抗４６を形成した場合であっても、第１の実施の形態の作用効果に加え、薄膜抵抗４６を付加することにより、抵抗機能を複合させた高容量・高信頼性・低ＥＳＲの薄膜キャパシタを実現することが可能となる。 Even in the case where the thin film resistor 46 is formed on the diffusion prevention layer 2 as in the fifth embodiment, the thin film resistor 46 is added in addition to the function and effect of the first embodiment. It is possible to realize a high-capacity, high-reliability, low-ESR thin-film capacitor that combines functions.
　また、第４の実施の形態と同様、薄膜抵抗４６を平坦状に形成しているので、抵抗値にバラツキが生じるのを抑制することができる。 Also, as in the fourth embodiment, since the thin film resistor 46 is formed in a flat shape, it is possible to suppress variation in resistance value.
　図１１は第６の実施の形態を示す誘電体薄膜キャパシタの断面図である。 FIG. 11 is a cross-sectional view of a dielectric thin film capacitor showing a sixth embodiment.
　本第６の実施の形態は、キャパシタ部が第３の実施の形態と略同様の構造を有している。 In the sixth embodiment, the capacitor section has a structure substantially similar to that of the third embodiment.
　すなわち、導電性基板１上に形成された拡散防止層２上に密着層４８、第１の電極層４９、及び第１の誘電体層５０が順次形成され、この第１の誘電体層５０上に電極層と誘電体層とが交互に積層されてキャパシタ部を形成している。 That is, the adhesion layer 48, the first electrode layer 49, and the first dielectric layer 50 are sequentially formed on the diffusion prevention layer 2 formed on the conductive substrate 1, and the first dielectric layer 50 is formed on the first dielectric layer 50. Electrode layers and dielectric layers are alternately stacked to form a capacitor portion.
　すなわち、前記第１の誘電体層５０上に、無機絶縁層５１を挟んで第２の電極層５２ａ、５２ｂ、第２の誘電体層５３ａ、５３ｂ、第３の電極層５４ａ、５４ｂ、第３の誘電体層５５ａ、５５ｂ、及び第４の電極層５６ａ、５６ｂ、第４の誘電体層５７ａ、５７ｂ、及び第５の電極層５８ａ、５８ｂが順次積層され、これら第１～第４の誘電体層５０、５３ａ、５３ｂ、５５ａ、５５ｂ、５７ａ、５７ｂ及び第１～第５の電極層４９、５２ａ、５２ｂ、５４ａ、５４ｂ、５６ａ、５６ｂ、５８ａ、５８ｂでキャパシタ部を形成している。そして、第５の電極層５８ａ、５８ｂ上に第５の誘電体層５９ａ、５９ｂが形成され、無機絶縁層５１は上面が有機絶縁層６０で被覆されている。 That is, on the first dielectric layer 50, the second electrode layers 52a, 52b, the second dielectric layers 53a, 53b, the third electrode layers 54a, 54b, the third, with the inorganic insulating layer 51 interposed therebetween. The dielectric layers 55a and 55b, the fourth electrode layers 56a and 56b, the fourth dielectric layers 57a and 57b, and the fifth electrode layers 58a and 58b are sequentially stacked, and the first to fourth dielectric layers are sequentially stacked. The body layers 50, 53a, 53b, 55a, 55b, 57a, 57b and the first to fifth electrode layers 49, 52a, 52b, 54a, 54b, 56a, 56b, 58a, 58b form a capacitor portion. Then, fifth dielectric layers 59 a and 59 b are formed on the fifth electrode layers 58 a and 58 b, and the upper surface of the inorganic insulating layer 51 is covered with the organic insulating layer 60.
　そして、基板配線６１及び電極配線６２、６３は第４の実施の形態と略同様の形状とされ、第１の電極層４９が基板配線１１を介して第１の接続電極１４に接続されると共に、第５の電極層５８ａ、５８ｂが上部外部電極を兼ねる電極配線６３、６２とそれぞれ電気的に接続されている。 The substrate wiring 61 and the electrode wirings 62 and 63 have substantially the same shape as that of the fourth embodiment, and the first electrode layer 49 is connected to the first connection electrode 14 via the substrate wiring 11. The fifth electrode layers 58a and 58b are electrically connected to electrode wirings 63 and 62 that also serve as upper external electrodes, respectively.
　そして、有機絶縁層６０上に薄膜抵抗６４が形成され、該薄膜抵抗６４には電極配線６３及び上部外部電極６５が電気的に接続され、これにより第５の電極層５８は電極配線６３及び薄膜抵抗６４を介して上部外部電極６５と電気的に接続されている。 A thin film resistor 64 is formed on the organic insulating layer 60, and the electrode wiring 63 and the upper external electrode 65 are electrically connected to the thin film resistance 64, whereby the fifth electrode layer 58 is connected to the electrode wiring 63 and the thin film. The upper external electrode 65 is electrically connected through the resistor 64.
　このように本第６の実施の形態においても、第１の実施の形態の作用効果に加え、薄膜抵抗６４を付加することにより、抵抗機能を複合させた高容量・高信頼性・低ＥＳＲの薄膜キャパシタを実現することが可能となる。 As described above, also in the sixth embodiment, in addition to the function and effect of the first embodiment, by adding the thin film resistor 64, the high-capacity, high reliability, and low ESR combined with the resistance function are achieved. A thin film capacitor can be realized.
　また、薄膜抵抗６４をキャパシタ部上に形成しているので、素子の大型化を招くのを極力回避できる。 Further, since the thin film resistor 64 is formed on the capacitor portion, it is possible to avoid the increase in size of the element as much as possible.
　また、薄膜抵抗６４を平坦状に形成しているので、抵抗値にバラツキが生じるのを抑制することができる。 Further, since the thin film resistor 64 is formed in a flat shape, it is possible to suppress the variation in the resistance value.
　尚、本発明は上記実施の形態に限定されるものではない。本発明は上述のように種々の変形例が可能であるが、上記各実施の形態で述べた成膜方法・成膜条件や膜厚等は例示であり、これらの方法・条件・膜厚に限定されるものではない。また、複数個分をまとめて製造する場合には、ダイシング等により個別に分割すればよいのはいうまでもない。 The present invention is not limited to the above embodiment. Although the present invention can be modified in various ways as described above, the film formation method, film formation conditions, film thickness, etc. described in the above embodiments are exemplifications. It is not limited. Needless to say, when a plurality of parts are manufactured together, they may be divided individually by dicing or the like.
　導電性基板の両側に外部電極を有する誘電体薄膜キャパシタであっても、キャパシタとしての信頼性を損なうことなく、ＥＳＲの増加を抑制できる。 Even in the case of a dielectric thin film capacitor having external electrodes on both sides of a conductive substrate, an increase in ESR can be suppressed without impairing the reliability of the capacitor.
　１　導電性基板
　４、２１ａ、２１ｂ　キャパシタ部
　５、７　電極層
　６　誘電体層
　８　絶縁層
　１１、３３、６１　基板配線
　１２、４７、６２、６３　電極配線、
　１５、４１、４５　上部外部電極（第１の外部電極）
　１７　下部外部電極（第２の外部電極）　
　２４、２６、２８、３０　電極層
　２５、２７、２９　誘電体層
　４２、４６、６４　薄膜抵抗
　４９、５２、５４、５６、５８　電極層
　５０、５３、５５、５７、５９　誘電体層 DESCRIPTION OF SYMBOLS 1 Conductive substrate 4, 21a, 21b Capacitor part 5, 7 Electrode layer 6 Dielectric layer 8 Insulating layer 11, 33, 61 Substrate wiring 12, 47, 62, 63 Electrode wiring,
15, 41, 45 Upper external electrode (first external electrode)
17 Lower external electrode (second external electrode)
24, 26, 28, 30 Electrode layer 25, 27, 29 Dielectric layer 42, 46, 64 Thin film resistor 49, 52, 54, 56, 58 Electrode layer 50, 53, 55, 57, 59 Dielectric layer

Claims (9)

  1. 　導電性基板の一方の主面側に少なくとも一つの第１の外部電極を形成し、前記導電性基板の他方の主面側に第２の外部電極を形成した誘電体薄膜キャパシタの製造方法であって、
    　誘電体層の上下両面に電極層が形成された少なくとも一つ以上の容量発生部を有するキャパシタ部を前記導電性基板の前記一方の主面上に形成するキャパシタ部形成工程と、
    　前記電極層のうちの一方の極となるべき電極層と前記導電性基板とを電気的に接続する基板配線を形成する配線形成工程とを有し、
    　前記キャパシタ形成工程と前記配線形成工程との間に前記キャパシタ部を熱処理する熱処理工程を含んでいることを特徴とする誘電体薄膜キャパシタの製造方法。     A method of manufacturing a dielectric thin film capacitor in which at least one first external electrode is formed on one main surface side of a conductive substrate and a second external electrode is formed on the other main surface side of the conductive substrate. And
    Forming a capacitor portion having at least one capacitance generating portion having electrode layers formed on both upper and lower surfaces of the dielectric layer on the one main surface of the conductive substrate; and
    A wiring forming step of forming a substrate wiring that electrically connects the electrode layer to be one of the electrode layers and the conductive substrate;
    A method of manufacturing a dielectric thin film capacitor, comprising a heat treatment step of heat treating the capacitor portion between the capacitor formation step and the wiring formation step.
  2. 　前記熱処理工程と前記配線形成工程との間に前記キャパシタ部を絶縁層で被覆する絶縁層形成工程を有し、前記基板配線の少なくとも一部を前記絶縁層上に形成することを特徴とする請求項１記載の誘電体薄膜キャパシタの製造方法。 An insulating layer forming step of covering the capacitor portion with an insulating layer between the heat treatment step and the wiring forming step, wherein at least a part of the substrate wiring is formed on the insulating layer. Item 2. A method for producing a dielectric thin film capacitor according to Item 1.
  3. 　前記キャパシタ部と電気的に接続された薄膜抵抗を形成する薄膜抵抗形成工程を前記熱処理工程と前記配線形成工程との間に有していることを特徴とする請求項１記載又は請求項２記載の誘電体薄膜キャパシタの製造方法。 The thin film resistor forming step for forming a thin film resistor electrically connected to the capacitor portion is provided between the heat treatment step and the wiring forming step. Of manufacturing a dielectric thin film capacitor.
  4. 　前記薄膜抵抗形成工程は、前記薄膜抵抗を平坦状に形成することを特徴とする請求項３記載の誘電体薄膜キャパシタの製造方法。 4. The method of manufacturing a dielectric thin film capacitor according to claim 3, wherein the thin film resistor forming step forms the thin film resistor in a flat shape.
  5. 　導電性基板の一方の主面側に少なくとも一つの第１の外部電極が形成されると共に、前記導電性基板の他方の主面側に第２の外部電極が形成された誘電体薄膜キャパシタであって、
    　誘電体層の上下両面に電極層を有する少なくとも一つ以上の容量発生部を備えたキャパシタ部が、前記導電性基板の前記一方の主面上に形成されると共に、
    　前記電極層のうちの一方の極となるべき電極層が、基板配線及び前記導電性基板を介して前記第２の外部電極と電気的に接続され、かつ、他方の極となるべき電極層が、前記第１の外部電極と電気的に接続され、
    　前記キャパシタ部が熱処理されてなると共に、少なくとも前記基板配線は、前記熱処理後に形成されることを特徴とする誘電体薄膜キャパシタ。     A dielectric thin film capacitor in which at least one first external electrode is formed on one main surface side of a conductive substrate and a second external electrode is formed on the other main surface side of the conductive substrate. And
    A capacitor unit including at least one capacitance generating unit having electrode layers on both upper and lower surfaces of the dielectric layer is formed on the one main surface of the conductive substrate;
    An electrode layer to be one of the electrode layers is electrically connected to the second external electrode through a substrate wiring and the conductive substrate, and an electrode layer to be the other electrode , Electrically connected to the first external electrode,
    The dielectric thin film capacitor, wherein the capacitor portion is heat-treated, and at least the substrate wiring is formed after the heat treatment.
  6. 　前記キャパシタ部が絶縁層で被覆されると共に、前記基板配線の少なくも一部が前記絶縁層上に形成されていることを特徴とする請求項５記載の誘電体薄膜キャパシタ。 6. The dielectric thin film capacitor according to claim 5, wherein the capacitor portion is covered with an insulating layer, and at least a part of the substrate wiring is formed on the insulating layer.
  7. 　薄膜抵抗が、前記他方の極となるべき電極層と電気的に接続されるように形成されていることを特徴とする請求項５又は請求項６記載の誘電体薄膜キャパシタ。 7. The dielectric thin film capacitor according to claim 5, wherein a thin film resistor is formed so as to be electrically connected to the electrode layer to be the other electrode.
  8. 　前記薄膜抵抗は、キャパシタ部上に形成されていることを特徴とする請求項７記載の誘電体薄膜キャパシタ。 8. The dielectric thin film capacitor according to claim 7, wherein the thin film resistor is formed on a capacitor portion.
  9. 　前記薄膜抵抗は、平坦状に形成されていることを特徴とする請求項７又は請求項８記載の誘電体薄膜キャパシタ。 9. The dielectric thin film capacitor according to claim 7, wherein the thin film resistor is formed in a flat shape.
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