KR20110024628A - Method for fabricating analysis treatment for faulty detection of metal line in semiconductor device - Google Patents

Method for fabricating analysis treatment for faulty detection of metal line in semiconductor device Download PDF

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Publication number
KR20110024628A
KR20110024628A KR1020090082700A KR20090082700A KR20110024628A KR 20110024628 A KR20110024628 A KR 20110024628A KR 1020090082700 A KR1020090082700 A KR 1020090082700A KR 20090082700 A KR20090082700 A KR 20090082700A KR 20110024628 A KR20110024628 A KR 20110024628A
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KR
South Korea
Prior art keywords
metal wiring
wiring line
etching
defect
copper
Prior art date
Application number
KR1020090082700A
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Korean (ko)
Inventor
김준동
Original Assignee
주식회사 하이닉스반도체
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Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020090082700A priority Critical patent/KR20110024628A/en
Publication of KR20110024628A publication Critical patent/KR20110024628A/en

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N1/00—Sampling; Preparing specimens for investigation
    • G01N1/28—Preparing specimens for investigation including physical details of (bio-)chemical methods covered elsewhere, e.g. G01N33/50, C12Q
    • G01N1/32—Polishing; Etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors

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  • Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
  • Biochemistry (AREA)
  • General Health & Medical Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Immunology (AREA)
  • Pathology (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

The present invention provides a method for manufacturing an analytical sample for detecting a metal wiring defect of a semiconductor device which can easily find a defect occurring in a process to improve a device manufacturing process, and detects a metal wiring defect of a semiconductor device according to the present invention. An analytical sample manufacturing method for forming a lower metal wiring line made of copper having one direction on a silicon substrate; Forming an insulating film on the entire surface including the lower metal wiring line; Forming an upper metal wiring line having a predetermined distance on the insulating layer in a direction perpendicular to the lower metal wiring line; Etching the upper metal wiring line to expose the insulating layer; Selectively etching the insulating film on the lower metal wiring line so that only a predetermined thickness remains; And forming a gap in the insulating film by etching a portion of the lower metal wiring line exposed by the hillock generation during the etching of the insulating film, by preventing the loss of a circle as much as possible in the preparation of a sample for defect analysis of the device. Unlike previous problems, it is easy to find the cause of the defect.

Hillock, metallization, copper, wet etching, sulfuric acid, voids

Description

METHODS FOR FABRICATING ANALYSIS TREATMENT FOR FAULTY DETECTION OF METAL LINE IN SEMICONDUCTOR DEVICE}

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing an analytical sample for detecting a metal wiring defect of a semiconductor device to prepare an analytical sample for metal wiring defect detection.

In the manufacture of semiconductor devices, due to the high integration of the devices and the complexity of the manufacturing process, various defects occur that cause problems in the operation of the product. The occurrence of such defects acts as a cause of deterioration of the performance of semiconductor devices and a decrease in yield, and many efforts have been made to solve them. Indeed, many efforts have been made to detect defects generated in the semiconductor manufacturing process, but the degree of defects that can be actually detected is subject to many limitations.

Recently, in order to improve the operation speed of the semiconductor device, the material of the metal wiring line is made of conventional tungsten and aluminum, and copper is used.

The defects that appear in the use of copper metal wires are different from those of conventional aluminum wires and appear in various forms.

In particular, the defects that occur in the use of copper in the use of copper cause a great defect in the semiconductor device, leading to a large decrease in yield. In particular, the use of copper is mainly used at the position to form the wiring line, so it causes voltage or current related defects (hereinafter referred to as DC Fail). Therefore, such defects cannot be repaired. It causes manufacturing loss.

In order to confirm such defects, the operation of tracking the location of the defects is performed after measuring electrical characteristics after completion of the manufacturing process. This operation usually requires the removal of the laminated materials deposited in the manufacturing process and this operation is commonly referred to as decapping.

The decapping operation is usually performed on a finished product to a finished wafer or package, which is performed by using wet or dry etching or polishing. However, in case of a device defect due to copper in a device using copper, the cause of the defect is lost when decapping by the conventional method, or it is very difficult to check the correct defect by removing only the copper. It is very difficult to present the solution to the manufacturing process.

In particular, in the case of copper, when used in combination with the conventional technique using aluminum, defects due to hillock are increasing. This is the reason why the existing process conditions are used to maintain compatibility with other processes with the equipment that used the post-copper process, that is, the insulating film deposited on the copper, and to prevent this by investing in new equipment. There is a problem that requires an increase in costs.

In addition, when such a hillock occurs and a defect occurs, a very fine copper film rises (see FIG. 1). To find such a defect, it is very difficult to find it by a conventional method or after numerous times, With the analytical equipment mobilized, further losses and increased costs are a conventional problem.

The present invention has been proposed to solve the above-mentioned problems of the prior art, which enables selective copper removal in the preparation of a sample for defect analysis of a device using copper, thereby generating a copper process in a device using copper. It is an object of the present invention to provide a method for manufacturing analytical sample for detecting defects in metallization of a semiconductor device, which makes it easy to find defects and improve device manufacturing processes.

In order to achieve the above object, a method for manufacturing an analytical sample for metal wiring defect detection of a semiconductor device of the present invention includes forming a lower metal wiring line made of copper having one direction on a silicon substrate; Forming an insulating film on the entire surface including the lower metal wiring line; Forming an upper metal wiring line having a predetermined distance on the insulating layer in a direction perpendicular to the lower metal wiring line; Etching the upper metal wiring line to expose the insulating layer; Selectively etching the insulating film on the lower metal wiring line so that only a predetermined thickness remains; And etching a portion of the lower metal interconnection line exposed by the hillock generation during the etching of the insulating layer to form voids in the insulating layer.

The present invention described above has the effect that it is possible to easily find the cause of the defect, unlike the previous problems by preventing the loss of the circle as much as possible in the production of the sample for analysis of the defect of the device.

In addition, it is possible to identify the cause of the accurate defects, enabling fast and accurate feedback (Feed-Back) in the product manufacturing process has the effect of improving the electrical characteristics of the device and improve the yield.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. do.

The analytical sample manufacturing method for the failure analysis of the semiconductor device according to the present invention is proceeding to remove the deposition materials in the reverse order to the manufacturing process of the product. Among defects of semiconductor devices that are occurring at present, defects between the metal wiring lines due to hillocks in the devices using copper metal wiring lines can be easily detected. It is an overview of the invention that the factor is caused by copper and uses a wet etching method.

In the manufacturing process of a semiconductor device, a failure of a metal wiring line generally causes a DC fail, particularly in the case of failure of wiring lines having different potentials rather than a metal wiring line of the same potential.

2 is a photograph showing a state where a defect between the same metal wiring lines is found.

As shown in Figure 2, when manufacturing a failure analysis sample by a conventional method it is very easy to find the manufacturing process or post-production. However, in the case of using copper, it is very difficult to prepare a sample for analysis or find a defect in the case of a defect of a metal wiring having a heterogeneous potential due to hillock or the like, and the process is performed in different processes.

3 is a photograph showing a state in which defects between different lines are generated by Hillock.

As shown in FIG. 3, in the case of sample fabrication for failure analysis, a defect cannot be found due to loss of the cause of the defect during the sample fabrication process, and thus, the cause of the malfunction of the device cannot be found.

Here, reference numeral 104 denotes an upper metal wiring line, 103 denotes a hillock generated, and 101 a lower metal wiring line.

3 shows a state in which only the copper wiring line is neatly removed without damaging the insulating layer using the present invention, and in this way, the sample is fabricated so that the defect between the upper metal wiring line and the lower copper wiring line can be found. It is possible.

In the case of the pores generated in the oxide film, it can also be useful to be easily detected in the SEM equipment that is widely used as a semiconductor analysis equipment without a special device.

The principles of the present invention can be applied to both semiconductor devices using a triple matal layer (TLM) structure or semiconductor devices using at least one layer of copper in semiconductor devices using a double lay metal (DLM) structure.

4A to 4D are cross-sectional views illustrating a method of manufacturing an analytical sample for detecting metal defects in semiconductor devices.

As shown in FIG. 4A, a copper film is deposited on a silicon substrate (not shown), and the copper film is selectively etched through a photo and etching process to form a lower metal wiring line 101 having a predetermined distance in one direction. .

Here, the electroplating method is used for the deposition of the copper film, in the case of using the electroplating method, the copper seed layer is deposited in advance by the IMP sputtering method, and the copper seed layer in the electrolytic solution (aqueous solution containing copper sulfate (CuSO 4 )). When the cathode potential is applied to the copper, copper ions in the electrolyte are reduced and plated on the copper seed layer.

Next, an insulating film 102 is formed on the entire surface of the silicon substrate including the lower metal wiring line 101. At this time, the surface of the lower metal wiring line 101 is raised toward the insulating film 102 by the hillock 103. Hillock 103 is a copper wiring having a coefficient of thermal expansion of about 10 times larger than the dielectric film is a sudden expansion over a certain temperature, and as a result of the increased compressive stress accumulated due to the large number of small hill-like shapes for stress relief Say what happens.

Subsequently, a plurality of upper metal wiring lines 104 having a predetermined interval in a direction perpendicular to the lower metal wiring lines 101 are deposited by depositing a metal film on the insulating film 102 and selectively etching the metal film through a photo and etching process. To form.

Here, the occurrence of the hillock 103 of the lower metal wiring line 101 generates a defect with the upper metal wiring line 104.

As shown in FIG. 4B, the upper metal wiring line 104 is removed.

After the upper metal wiring line 104 is formed, the package or passivation process may be performed and the removal process may be performed by a conventional method. That is, the package or passivation existing on the upper portion of the metal wiring line is removed in a conventional manner in order to prepare a sample for confirming defects between dissimilar copper wiring lines, and then the upper metal wiring line 104 is removed.

After the removal of the package or passivation, the upper metal wiring line 104 can check whether or not a defect occurs as shown in FIG. 2, and then remove the upper metal wiring line 104. In this case, the method of removing the upper metal wiring line 104 may use wet etching or polishing.

As shown in FIG. 4C, the insulating film 102 is etched to be at least 1000 kV or more above the lower metal wiring line 101.

The etching of the insulating layer 102 and the removing process of the upper metal wiring line 104 may be simultaneously performed or may be performed through a separate process. That is, when the upper metal wiring line 104 is removed, the etching process is continued to lower the thickness of the insulating film 102, or after removing the upper metal wiring line 14, the height of the insulating film 102 is lowered through a separate etching process. Can be.

Subsequently, when the lower metal wiring line 101 uses copper, a wet etching process using sulfuric acid is performed.

At this time, if an abnormality occurs in the upper metal wiring line 104 due to the hillock 103 of copper, voids are generated in the upper portion of the insulating film 102. If this void is not generated, the copper bulging up to the insulating film 102 by the insulating film 102 and the hillock 103 cannot be found because the shape cannot be distinguished.

In addition, sulfuric acid may be heated to 100 ° C. to 350 ° C. during wet etching of the insulating layer 102.

As shown in FIG. 4D, since the insulating film 102 has very low etching characteristics for sulfuric acid solution, almost no loss occurs, but the region where the hillock 103 occurs contains copper and copper has no etching effect against sulfuric acid. As a result, voids 105 are generated in the insulating film 102.

5A and 5B are photographs showing a case of applying and not applying an analytical sample manufacturing method for metal wiring defect detection of a semiconductor device according to the present invention, respectively.

That is, FIG. 5A is a photograph before applying the present invention, and FIG. 5B is a photograph after applying the present invention.

As shown in Fig. 5B, when the present invention is applied, the defect of the metal wiring can be detected more clearly than in Fig. 5A.

On the other hand, the present invention has been described a sample manufacturing method for defect analysis in the metal wiring line of the semiconductor device, embodiments of the present invention is not limited to the metal wiring line, PCRAM for forming the wiring line using copper, Applicable to all memory devices such as DRAM and FLASH.

As such, although the technical idea of the present invention has been specifically recorded in accordance with the above-described preferred embodiments, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a photograph showing a defect occurred in the metal wiring of the semiconductor device according to the prior art,

2 is a photograph showing a state in which a defect is found between the same metal wiring lines;

3 is a photograph showing a state in which defects between different lines are generated by Hillock,

4A to 4D are cross-sectional views illustrating a method for manufacturing an analytical sample for detecting defects in metallization of semiconductor devices;

5A and 5B are photographs showing a case of applying and not applying an analytical sample manufacturing method for metal wiring defect detection of a semiconductor device according to the present invention, respectively.

* Explanation of symbols for the main parts of the drawings

101: lower metal wiring line 102: insulating film

103: hillock 104: upper metal wiring line

105: void

Claims (5)

Forming a lower metal interconnection line made of copper having one direction on the silicon substrate; Forming an insulating film on the entire surface including the lower metal wiring line; Forming an upper metal wiring line having a predetermined distance on the insulating layer in a direction perpendicular to the lower metal wiring line; Etching the upper metal wiring line to expose the insulating layer; Selectively etching the insulating film on the lower metal wiring line so that a predetermined thickness remains; And Performing wet etching using a copper etching material on the insulating layer An analytical sample manufacturing method for metal wiring defect detection of a semiconductor device comprising a. The method of claim 1, The upper metal wiring line is an analytical sample manufacturing method for detecting the metal wiring defect of the semiconductor device to remove by wet etching or polishing etching. The method of claim 1, The wet etching is an analytical sample manufacturing method for the detection of poor metal wiring of the semiconductor device proceeds using a sulfuric acid solution. The method of claim 3, The wet etching is an analytical sample manufacturing method for the detection of poor metal wiring of the semiconductor device used by heating the sulfuric acid solution. The method of claim 4, wherein The sulfuric acid solution is heated to 100 ℃ ~ 350 ℃ analytical sample manufacturing method for the detection of poor metal wiring of the semiconductor device used.
KR1020090082700A 2009-09-02 2009-09-02 Method for fabricating analysis treatment for faulty detection of metal line in semiconductor device KR20110024628A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105097596A (en) * 2015-07-30 2015-11-25 宁波时代全芯科技有限公司 Detection method of contact hole of semiconductor apparatus
CN108039338A (en) * 2017-11-24 2018-05-15 华中科技大学 A kind of method for eliminating dielectric layer needle pore defect and influencing
CN113809048A (en) * 2021-08-26 2021-12-17 联芯集成电路制造(厦门)有限公司 Semiconductor device with a plurality of semiconductor chips

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105097596A (en) * 2015-07-30 2015-11-25 宁波时代全芯科技有限公司 Detection method of contact hole of semiconductor apparatus
CN108039338A (en) * 2017-11-24 2018-05-15 华中科技大学 A kind of method for eliminating dielectric layer needle pore defect and influencing
CN113809048A (en) * 2021-08-26 2021-12-17 联芯集成电路制造(厦门)有限公司 Semiconductor device with a plurality of semiconductor chips

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