KR0172467B1 - Fabrication method of semiconductor device with alignment key for metal contact mask - Google Patents

Abstract

Etching a predetermined portion of the insulating film (2) of the wafer scribe line region; Forming a diffusion barrier metal layer (3), a planarization metal layer (4), an antireflection layer (5) sequentially on the entire structure; And removing the anti-reflection layer (5) and the planarization metal layer (4) on the etched portion of the insulating film (2). Since a key having a clean surface can be obtained and wiring mask operation can be easily and accurately performed, there is an effect of improving reliability and yield of a semiconductor device.

Description

Method of manufacturing semiconductor device for forming alignment key of metallization mask

1A to 1E are diagrams illustrating a semiconductor device manufacturing process for forming an alignment key of a metallization mask according to an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

1 silicon substrate 2 insulating film

3: diffusion prevention metal layer 4: aluminum alloy layer

5: antireflection layer 6: alignment key

7: photosensitive film 8: spacer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device for forming an alignment key of a metallization mask during a semiconductor device manufacturing process. In particular, only a predetermined portion of a scribe line is masked after deposition of a planarized metal film. The present invention relates to a method of etching a metal layer deposited on an alignment key and using an alignment key from which a metal layer has been removed to easily and accurately perform an actual metallization mask operation.

As the integration of semiconductor devices increases, the size of a contact contacting a silicon substrate or a conductive layer decreases and the height of an insulating film increases, making it difficult to deposit a metal thin film due to a tendency to increase a step ratio. Therefore, in order to improve the layer covering of the deposited film, improvement of the deposition method or equipment has been conducted to study the filling of the contact through the planarization of the film.

However, the above methods cause problems of metallization mask work such as misalignment, poor alignment accuracy, and inability to read alignment accuracy because the metal film is planarized at the contact. Especially in the case of the aluminum alloy planarization process by a high temperature process, the degree is severe.

In other words, the alignment-related keys for general masking are formed on the scribe line of the wafer and have a symmetrical shape. After the masking, the alignment masks are measured at right, left, top and bottom symmetry. When the planarization process is performed, the aluminum film covered on the alignment key portion flows due to the flow of the aluminum alloy, so that an asymmetric phenomenon occurs in the alignment key, and grains of aluminum are grown to increase surface roughness. Incorrect alignment of the wiring mask is inevitable.

Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device for forming an alignment key in which an asymmetric phenomenon is prevented, in order to prevent alignment failure of the metallization mask.

The present invention to achieve the above object, the first step of forming a groove-shaped alignment key in a predetermined region of the wafer; A second step of sequentially stacking a diffusion barrier metal layer, a planarized wiring metal layer, and an antireflection layer on the entire structure of the wafer where the first step is completed; Forming a mask pattern in which the alignment key upper region is opened; Performing dry etching by dry etching the anti-reflection layer and the wiring metal layer using the mask pattern as an etching mask, but setting an etching target so that the diffusion preventing metal layer is not damaged; And removing the mask pattern and forming a metal wiring mask pattern aligned with the remaining wiring gold.

The present invention also provides a first step of forming an alignment key in a predetermined region of a wafer; A second step of forming a wiring metal layer on the entire structure of the wafer on which the first step is completed, and flowing the metal layer to planarize it; Selectively etching the metal layer in the upper portion of the alignment key by a mask and an etching operation to expose the alignment key; And a fourth step of forming the metallization mask pattern aligned by the alignment key.

1A to 1E illustrate a process of manufacturing a semiconductor device for forming an alignment key of a metallization mask according to an embodiment of the present invention.

First, FIG. 1A illustrates a diffusion barrier metal layer 3 and a planarized aluminum alloy layer due to a process following the alignment key 6 of the wafer scribe region formed by etching the silicon substrate 1 or the insulating layer 2 on the conductive layer. 4) and a cross-sectional view of a state in which the anti-reflection layer 5 is sequentially deposited, and as shown in the figure, the aluminum alloy layer 4 which is flowed and planarized by a high temperature process is asymmetrical in the alignment key 6 and left and right. The wiring mask alignment accuracy is difficult to read. If it is severe, perfect flattening in the alignment related key 6 is performed, and a level difference cannot be distinguished and wiring mask operation is impossible.

FIG. 1B is a cross-sectional view showing a state where a mask operation is performed to remove a metal layer in an upper region of the alignment key 6 for wiring mask operation of a scribe line. That is, the photosensitive film 7 pattern is formed in all the parts of the wafer except the alignment key 6 area.

In FIG. 1C, by etching the entire anti-reflection layer 5 and the aluminum alloy layer 4 by the deposition thickness by a dry etching method, the aluminum alloy layer on the plane is almost removed and only the aluminum alloy spacers are formed on the sidewalls of the alignment key 6. It is sectional drawing which shows the state which the spacer remains. In the dry etching process, the alignment key 6 and the metal layer around the key are removed to a predetermined thickness and the diffusion preventing metal layer 3 and the insulating film 2 forming the new alignment key 6 must be maintained without damage.

Next, FIG. 1D is a cross-sectional view illustrating a state after removing the photosensitive film 7 and removing a polymer or the like formed during dry etching. The above state may be better for the wiring mask operation than the state of FIG. 1A, but a great improvement cannot be expected.

Accordingly, in FIG. 1e, the aluminum alloy layer remaining on the diffusion barrier layer after FIG. 1d should be performed in a solution in which only the aluminum alloy is etched without the diffusion barrier metal layer and the antireflection layer etched during wet etching. After wet etching is completed and a predetermined cleaning process is performed, a wiring mask operation is performed using symmetrical alignment-related keys to form a precisely aligned metal wiring.

According to the present invention described above, after removing the aluminum alloy layer and the antireflection layer deposited on the alignment-related key of the scribe line by the first dry etching method, the aluminum alloy layer remaining on the diffusion barrier layer is secondly removed by the wet etching method. Since the key can be obtained without damage to the key and the surface is clean, the metallization mask operation can be easily and accurately performed, thereby improving the reliability and yield of the semiconductor device.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

Claims (1)

Forming a groove-shaped alignment key in a predetermined region of the wafer; A second step of sequentially stacking a diffusion barrier metal layer, a planarized wiring metal layer, and an antireflection layer on the entire structure of the wafer where the first step is completed; Forming a mask pattern in which the alignment key upper region is opened; Performing dry etching by dry etching the anti-reflection layer and the wiring metal layer using the mask pattern as an etching mask, but setting an etching target so that the diffusion preventing metal layer is not damaged; A fifth step of removing the mask pattern and wet etching the remaining metal layer for wiring; And forming a metal wiring mask pattern aligned by an alignment key covered by the diffusion barrier metal layer.