JPH07161720A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To provide a semiconductor device and its manufacturing method which can prevent generation of film thickness difference between interlayer insulating films formed on a lower layer narrow wiring and on lower layer wide wiring, regarding a semiconductor device having a multilayered wiring structure and its manufacturing method. CONSTITUTION:Each of the narrow wirings 3c1, 3c2 and 3c3 has the line width which is 1-3 times the line width of a lower layer narrow wiring 3a and is adjacently and separately arranged parallel with the wiring width direction. The tip part of each of the narrow wirings 3c1, 3c2 and 3c3 is bifurcated, and line width of each of the bifurcated parts is formed so as to be nearly equal to the line width of the lower layer narrow wiring 3a. The bifurcated parts are connected with through holes 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a multi-layer wiring structure and a manufacturing method thereof.

In a semiconductor device having a multi-layer wiring structure, if a step is formed by a lower layer wiring, it becomes difficult to form the upper layer wiring with high reliability. Therefore, it is necessary to flatten the above step during manufacturing. .

[0003]

2. Description of the Related Art FIG. 4 is a plan view showing a lower layer wiring portion of an example of a conventional semiconductor device, and FIGS. 5A and 5B are enlarged sectional views showing the steps of the main portion of FIG. In this conventional semiconductor device, first, as shown in FIG. 5A, a lower narrow wiring 3a and a lower wide wiring 3e made of, for example, an aluminum film are formed on a semiconductor substrate 1 with an insulating film 2 interposed therebetween. . Subsequently, a first interlayer insulating film 4a made of, for example, a plasma oxide film and having a thickness half that of the interlayer insulating film to be finally obtained is formed. Next, a flattening coating film 5 such as an inorganic or organic silica film is formed by a spin-on-glass method so as to fill the step in the inter-wiring region of the first interlayer insulating film 4a.

Next, as shown in FIG. 5B, after removing the portions of the flattening coating film 5 formed on the wirings 3a and 3f, the flattening coating film 5 is formed only in the inter-wiring region. Etching back is performed so that the flattening coating film 5 and the first interlayer insulating film 4a have substantially the same etching rate so that they are left. Next, for example, a second interlayer insulating film 4b made of a plasma oxide film is formed, and a flat interlayer insulating film 4 is formed.

In this way, as shown in FIG. 4, a semiconductor in which the lower layer narrow wiring 3a and the lower layer thick wiring 3f are formed on the semiconductor substrate 1 and through holes 6a and 6b are formed in the semiconductor substrate 1 respectively. The device is created.

Further, as a method for flattening an interlayer insulating film in a conventional semiconductor device having a multilayer wiring structure, there is disclosed in Japanese Patent Laid-Open No.
The one described in Japanese Patent No. 22843 is known. This is a thin first electrode formed on the diffusion layers 11 and 12 as shown in FIGS. 6 to 8 when a flat interlayer insulating film is formed by the conventional bias sputtering method or bias ECR method. 13 or wirings 16 to 1 formed on the substrate 15
Although the narrow wiring 16 and the narrow wiring 20 of 8 are easily flattened, the contact portions 14 and 21 between the electrode 13 or the wiring 20 and the second wiring, and the thick wiring 17, 18
On the pattern, if the film thickness of the interlayer insulating film 19 or the like is not sufficiently increased, it is not flattened. On the other hand, if the interlayer insulating film is too thick, the aspect ratio of the contact hole becomes large, and the contact yield and reliability are increased. The purpose of this is to solve the drawback that the property is greatly deteriorated.

That is, in this conventional device, FIGS.
As shown in FIG. 14, the contact portions between the first electrode 13 or the wiring 20 and the second wiring are provided with 14a to 14d or 21a to
A split pattern as shown in 21d (a pattern in which a thick wiring is originally divided into a set of thin linear patterns typified by comb teeth) or the wiring 18 is divided into narrow wirings 18a. It is a thing.

Thus, according to this conventional device, all the electrodes or wirings including the contact portion have a thin linear pattern, so that the interlayer insulating film formed on them by the bias sputtering method or the bias ECR method. Is shown in FIG.
Like the insulating film 22 shown in FIG. 2, the insulating film 22 can be formed to have a flat film thickness and an aspect ratio that does not increase so much. Therefore, the yield and reliability of a high density integrated circuit can be improved. is there.

Further, as another method of flattening an interlayer insulating film in a conventional semiconductor device having a multilayer wiring structure, a method disclosed in Japanese Patent Laid-Open No. 3-136330 is known. As shown in FIG. 12, this structure has electrodes 32a and wirings 32b and 32c formed on a semiconductor substrate 31, and then Si is formed on the entire surface.
When the interlayer insulating film 33 made of O ₂ or the like is formed,
Electrodes 32a and wirings 32b formed on the interlayer insulating film 33,
In order to flatten the unevenness due to 32c, an object is to solve the drawback of the method of flattening the surface by applying an insulating coating film 35 such as polyimide containing Si or BSG and then performing heat treatment. is there.

The above-mentioned drawbacks result in recesses between the wirings in a portion where the wirings are wide, and in some cases cause disconnection or metal residue when forming the wirings in the upper layer, which lowers the reliability and yield of the semiconductor device. That is. In the above-mentioned conventional method, in order to solve this drawback, as shown in FIGS. 13 and 14, electrodes 32a and wirings 32b, 32 are provided.
After the SiO ₂ film 33 is formed by the CVD method so as to have the same thickness as the electrodes 32a and the wirings 32b and 32c on the semiconductor substrate 31 on which the unevenness due to c or the like is formed,
₂ the concave portion of the film 33 is covered, and the electrode 32a and the wiring 3
The photoresist pattern 34 is formed so that the upper portions of the protrusions formed by 2b and 32c are exposed.

Next, the SiO ₂ film 33 on the upper and side portions of the electrodes 32a and the wirings 32b and 32c or only on the upper portion is removed by wet etching, and the photoresist pattern 34 is further removed. After that, as a second insulating film,
The SiO ₂ film 33a or the insulating coating film 35 is formed so as to fill the recesses, and a flat interlayer insulating film can be formed regardless of the wiring interval.

Further, as another method of flattening an interlayer insulating film in a semiconductor device having a conventional multilayer wiring structure, a semiconductor device described in Japanese Patent Publication No. 2-21138 is known. As shown in FIG. 15, after forming lower layer wirings 43a and 43b on the surface of an insulating film 42 on a semiconductor substrate 41, an interlayer insulating film 44 is formed on the lower wirings 43a and 43b, and further on the insulating film 44. In the case where the interlayer insulating film 44 is flattened by spin-coating an organic resin such as a photoresist resin, performing a curing treatment, and etching back the organic resin and the insulating film 44 at substantially the same rate. The purpose is to take measures.

That is, in the above case, since the organic resin film thickness at the time of coating becomes thicker as the line width of the lower layer wiring becomes wider, the lower layer wiring 4 having a narrow line width after the etching back flattening.
An extremely thick interlayer insulating film 44 remains on the lower layer wiring 43a having a wider line width than that on 3b. Therefore, as compared with the through hole 45b formed on the lower layer wiring 43b having a narrow line width, the depth of the through hole 45a formed on the lower layer wiring 43a having a wide line width is very deep, and the step coverage of the upper layer wiring is covered. And the reliability of the upper wiring is broken due to electromigration.

Therefore, in the conventional semiconductor device shown in FIG.
As shown in FIG. 6, the through hole 45 is formed by forming the lower layer wiring removal pattern 46 between a plurality of through holes 45a formed on the lower layer wiring 43a having a wide line width.
The coating thickness of the organic resin at the formation location a is almost the same as the coating thickness on the lower layer wiring 43b having a narrow line width, and does not depend on the line width after the etching back flattening and is the film of the interlayer insulating film 44 in the through hole portion. Since the thickness is almost the same, the through holes 45a and 45b can be formed to have substantially the same depth.
This is intended to prevent disconnection of the upper layer wiring due to electromigration at the through hole portion.

[0015]

However, in the conventional semiconductor device shown in FIGS. 4 and 5, the flattening coating film 5 is formed and then the etching back is performed for flattening. The coating film 5 is formed only very thin on the lower layer narrow wiring 3a such as inside the element, whereas it is thickly formed on the lower layer wide wiring 3f. Therefore, etching back is performed to finally form the interlayer insulating film 4
In this case, a film thickness difference occurs between the two wirings 3a and 3f, and the lower thick wiring 3f becomes thicker.

Therefore, the through holes 6a and 6b formed on the lower layer narrow wiring 3a and the lower layer thick wiring 3f have shape variations with different aspect ratios, and the step coverage of the upper layer wiring deteriorates. There is a problem that the reliability of the system and the yield of semiconductor devices are reduced.

Further, when the thick flattening coating film layer is exposed on the side wall of the through hole, moisture or the like is easily adsorbed, and conduction failure occurs due to the release of moisture or the like when the upper layer wiring is formed. The flattening coating film 5 so that the film 5 hardly remains (thus remaining thin)
It is necessary to carry out etching back. Therefore, the extra flattening coating film 5 thickly formed on the lower wide wiring 3f is formed.
It takes a long time to etch back. However, although the etching back is performed under the condition that the etching rates of the flattening coating film 5 and the first interlayer insulating film 4a are substantially the same, the longer the time required for the etching back is, the flattening coating film 5 is formed. In addition, since the difference in etching rate between the interlayer insulating film 4a appears remarkably, the semiconductor device shown in FIGS. 4 and 5 has a problem that the flatness becomes worse than the flatness at the time of applying the flattening coating film 5. There is also.

Further, in the conventional semiconductor device disclosed in Japanese Patent Laid-Open No. 2-22843, the thickness of the gate electrode 13 is changed to the thickness of the gate electrode 13 as in the basic cell pattern of the gate array using MOS transistors as shown in FIG. For contact part 14
Is the maximum of all gate electrode patterns, and is at most 3 ~
For patterns that are four times larger, 14a ...
As shown in FIG. 14d, the contact portion can be formed in a split pattern, and the contact portion and the contact portion can be formed in a thin linear pattern.

However, in the wiring patterns such as the first layer wiring and the second layer wiring, the power source and the ground wiring generally have a line width of several tens μm to several hundreds μm in order to prevent a voltage drop.
A thick wiring is used, and for a pattern in which the maximum thickness of all wiring patterns is several tens μm to several hundreds μm, the through hole part is a split pattern,
It is not realistic to form all of these thick wirings in a thin linear pattern including the through hole because wiring resistance increases, and this conventional device is applied to wiring patterns such as first layer wiring and second layer wiring. Is difficult to do.

Further, although it is possible to apply this conventional device by forming the above-mentioned thick wiring from a line segment having a certain practical thickness, in this case, a flat interlayer insulating film is formed. In order to form the film, the film thickness is inevitably increased, the aspect ratio of the through hole is increased, and the yield and reliability of the through hole are greatly deteriorated.

Further, in the conventional semiconductor device disclosed in Japanese Patent Laid-Open No. 3-136330, as shown in FIGS. 13 and 14, after the photoresist pattern 34 is formed, it is formed on the electrodes 32a and the wirings 32b and 32c. SiO ₂
Although the film 33 is removed by wet etching, since the wet etching is isotropic etching, as shown in FIG.
b, and removed to between the SiO ₂ film 33 side of the 32c, SiO ₂ covered with the photoresist pattern 34
The film 33 is also laterally etched by the film thickness.

For example, the wiring width / wiring interval is 1.0
When the wiring film thickness is 0.5 μm / μm / 1.0 μm, the photoresist pattern 34 is formed at an interval of 2.0 μm or less, and when the wiring film thickness is 1.0 μm,
Similarly, there is a problem in that the SiO ₂ film 33 does not remain in the space of 4.0 μm or less due to side etching, and the interlayer insulating film cannot be flattened at the same position.

Further, as shown in FIG. 14B, the SiO ₂ film 33 above the electrodes 32a and the wirings 32b and 32c.
The above-mentioned problem can be solved by stopping the wet etching at the time when is removed by etching. However, in any case, the electrodes 32a and the wirings 32b, 32c are removed.
Since the wet etching solution comes into contact therewith, there is a problem that the reliability of the wiring is deteriorated due to damage such as erosion due to the wet etching solution. Further, since the photoresist pattern 34 is formed, the number of manufacturing steps is increased, such as the number of aligning exposure steps, and the manufacturing time is extended.

Further, in the conventional semiconductor device disclosed in Japanese Patent Publication No. 2-21138, as shown in FIG. 16, the through hole 45b on the lower layer wiring 43b having a narrow line width and the lower layer wiring 43a having a wide line width are provided. Since the depth of the through holes is substantially the same as that of the through holes 45a, a plurality of through holes 4
Although the lower layer wiring removal pattern 46 is provided between the lower layer wiring 5a and the lower layer wiring 5a, an extremely thick interlayer insulating film 44 still remains on the lower layer wiring 43a having a wide line width other than the formation region of the through hole 45a. The flatness of a typical interlayer insulating film is poor, and if wirings are formed in multiple layers on the interlayer insulating film, the absolute level difference becomes larger outside the area where the through hole 45a is formed, which is not suitable for multilayering. .

Further, in this conventional apparatus, an interlayer insulating film having a thickness equal to or larger than the lower layer wiring film thickness (step) is formed, a photoresist resin is applied and formed, and then etching back is performed to transfer a flat surface shape of the photoresist resin. To do. However, in order to obtain a photoresist resin having a flat surface shape, a thickness of about 1.0 μm is required. To etch back the photoresist resin and the convex portion of the interlayer insulating film formed on the lower wiring, Since it takes a long time, it is difficult to finish the etching back so that an optimal flat shape can be obtained with high reproducibility because of large variations in etching. Therefore, depending on the wafer, there is a problem that a film thickness is generated in the interlayer insulating film on the lower wiring, and the depth of the through hole varies.

Further, the etching back is carried out under the etching conditions in which the photoresist resin and the interlayer insulating film have substantially the same speed. However, if the etching back takes a long time, the difference in the etching speed between the two becomes remarkable. Another problem is that the flatness after etching back is worse than the flatness when the photoresist resin is formed.

The present invention has been made in view of the above points, and a semiconductor device and a semiconductor device capable of preventing a difference in film thickness from occurring in an interlayer insulating film formed on a lower layer narrow wiring and a lower layer wide wiring. It is intended to provide a manufacturing method.

[0028]

In order to achieve the above object, a semiconductor device of the present invention is a semiconductor device having a multilayer wiring structure in which a plurality of wiring layers are formed on a semiconductor substrate with an interlayer insulating film interposed therebetween. The lower wide wiring of the lower wiring layer under the insulating film is composed of a plurality of narrow wirings arranged close to each other in the wiring width direction. In addition, the lower wide wiring is composed of a plurality of narrow wirings arranged close to each other in the wiring width direction, and has a length 1 to 3 times the line width of the lower narrow wiring in the wiring length direction. By means of a section, adjacent narrow wirings of the plurality of narrow wirings are connected at a predetermined interval.

The method of manufacturing a semiconductor device according to the present invention is
The step of forming the lower layer wide wiring and the lower layer narrow wiring, and the entire layer including the lower layer narrow wiring and a plurality of narrow wiring,
A step of coating the first interlayer insulating film, a step of coating a flattening coating film on the first interlayer insulating film so that the surface is substantially flat, and a portion of the flattening coating film above the inter-wiring region And a step of etching back so as to leave only the flattening coating film portion, and a step of forming a second interlayer insulating film on the entire surface including the flattening coating film that has been etched back. .

[0030]

In the present invention, the lower wide wiring of the lower wiring layer is composed of a plurality of narrow wirings closely spaced in the wiring width direction, and the line width of each of the plurality of narrow wirings is set. Since the line width is about 1 to 3 times the line width of the lower-layer narrow wiring, the flattening coating film formed on the lower-layer wiring layer is thin, and also on the lower-layer narrow wiring and on the plurality of narrow-width wirings. With, it is possible to form with almost no difference in film thickness.

[0031]

EXAMPLES Next, examples of the present invention will be described. 1 is a plan view showing a lower layer wiring portion of a first embodiment of a semiconductor device according to the present invention. As shown in FIG.
A lower narrow wiring 3a and a lower wide wiring 3b are formed on the upper side. This embodiment is characterized in that the lower layer wide wiring 3b is composed of three narrow wirings 3c1, 3c2 and 3c3.

Each of the narrow wirings 3c1, 3c2 and 3c3 has a line width which is 1 to 3 times the line width of the lower layer thin wiring 3a and is arranged close to and spaced in parallel to the wiring width direction.
Further, each of the narrow wirings 3c1, 3c2 and 3c3 has a bifurcated tip portion, and the line width of each branch portion is formed to be substantially equal to the line width of the lower layer thin wiring 3a. This branch portion is connected to the through hole 6.

Next, a first embodiment of the method of the present invention for manufacturing the semiconductor device shown in FIG. 1 will be described with reference to FIG.
FIG. 2 is an enlarged cross-sectional view of a portion along the line XX ′ in FIG. 1 in each manufacturing process, and the same components as those in FIG. 1 are designated by the same reference numerals. As shown in FIG. 2A, first, on a semiconductor substrate 1 made of, for example, silicon (Si), a lower layer narrow wiring 3a made of, for example, an aluminum (Al) film is provided with an insulating film 2 made of, for example, SiO ₂ interposed therebetween. , Multiple thin lines 3c
The lower wide wiring 3b composed of 1, 3c2 and the like is formed.

At this time, the narrow wirings 3c1 and 3c2 have a line width three times the line width of the lower layer thin wiring 3a, and the same line width as that of the lower layer thin wiring 3a in the through hole opening. Formed in width.

Next, a first interlayer insulating film 4a made of, for example, a plasma oxide film and having a thickness about half the film thickness of the interlayer insulating film to be finally obtained is formed. Then, a flattening coating film 5 such as an inorganic or organic silica film is formed by a spin-on-glass method so as to fill the step in the inter-wiring region such as the lower narrow wiring 3a and the plural thin wirings 3c1 and 3c2. To form.

Next, as shown in FIG. 2B, the flattening coating film 5 formed on the wirings 3a and 3b is removed, and the flattening coating film 5 is left only in the inter-wiring region to be flattened. Etching back is performed using the RIE (reactive ion etching) method under the condition that the coating film 5 and the first interlayer insulating film 4a have substantially the same etching rate. Subsequently, the second interlayer insulating film 4b made of, for example, a plasma oxide film is formed,
The surface of the planarization coating film 5 and the first interlayer insulating film 4a above the inter-wiring region is coated and formed to form a flat interlayer insulating film 4. After that, the through holes 6 connected to necessary positions of the lower layer narrow wiring 3a and the lower layer thick wiring 3b are opened.

According to this embodiment, the three narrow wirings 3c1 are provided.
3c3 are respectively connected to upper layer wirings (not shown) to which the lower layer wide wirings 3b are to be connected via through holes 6, so that the line width of the lower layer narrow wirings 3a is 1
Since one thin lower layer wiring 3b is composed of three thin wirings 3c1 to 3c3 having a line width of about 3 times, a flattening coating film 5 is conventionally formed on the lower wirings 3a and 3b. It is thinner than the above, and can be formed without any difference in film thickness.

Therefore, during the etching back,
It is only necessary to remove the thin and flattening coating film 5 above the lower layer wirings 3a and 3b and applied without any difference in film thickness.
Therefore, the etching back requires only a short time. Therefore, variations in etching back are small, flatness is hardly deteriorated, and etching back can be easily performed.

Further, when the flattening coating film 5 applied above the lower layer wirings 3a and 3b can be formed to be thinner than usual, about 1000 Å or less, even if the flattening coating film layer is exposed on the side wall of the through hole. It has been confirmed by the present inventor that there is no adverse effect such as defective conduction when the upper wiring is formed due to adsorption or release of water or the like. In this case, therefore, it is not necessary to perform the above-mentioned full-scale etching back. In this case, the interlayer insulating film 4 can be formed with the excellent flatness of the flattening coating film 5.

As described above, in this embodiment, the lower narrow wiring 3
Since there is no film thickness difference above a and the lower wide wiring 3b and the interlayer insulating film 4 can be formed, the through hole 6 formed above both wirings 3a and 3b does not have a variation in shape, and the upper wiring It is possible to obtain stable step coverage.

Next, a second embodiment of the semiconductor device of the present invention will be described. FIG. 3 is a plan view showing a lower layer wiring portion of a second embodiment of the semiconductor device according to the present invention. In the figure, the same components as those in FIG. 1 are designated by the same reference numerals. In the embodiment shown in FIG. 3, the lower wide wiring 3d is the lower narrow wiring 3a.
4 narrow wirings 3 having a line width of 1 to 3 times the line width of
It is characterized in that it is composed of c1 to c3 and a connecting portion 3e that connects two adjacent narrow wirings of the narrow wirings 3c1 to 3c4.

The connecting portion 3e has a length 1 to 3 times the line width of the lower narrow wiring 3a in the wiring length direction of the lower wide wiring 3d, and is formed at intervals of 10 μm to 200 μm. It is something. Thereby, according to the present embodiment,
There is an effect that the wiring resistance of the lower wide wiring 3d can be reduced without impairing the flatness of the interlayer insulating film 4.

A method of manufacturing a semiconductor device according to this embodiment is shown in FIG.
Basically the same as that of the first embodiment shown in FIG. 3, and FIG. 3 shows the shape (pattern) of the wiring pattern mask for patterning the lower layer narrow wiring 3a and the lower layer wide wiring 3d on the semiconductor substrate 1. All you have to do is change it.

[0044]

As described above, according to the present invention,
A thin flattening coating film formed on the lower wiring layer,
Since it can be formed with almost no film thickness difference between the lower narrow wiring and the plurality of narrow wiring, there is no difference in film thickness between the lower narrow wiring and the plurality of narrow wiring, In addition, an interlayer insulating film having improved flatness can be formed. Therefore, it is possible to prevent the variation in the shape of the through hole formed for each of the lower layer narrow wiring and the plurality of narrow wirings, and to obtain stable step coverage of the upper layer wiring. The reliability and the yield of semiconductor devices can be improved as compared with the conventional one.

Further, according to the present invention, when the flattening coating film applied above the lower layer wiring can be formed to be thinner than about 1000 Å or less than usual, the flattening coating film formed on the lower layer wiring is formed. Since etching back for removing and leaving the planarization coating film only in the inter-wiring region can be eliminated, the number of manufacturing steps can be reduced as compared with the conventional case. Further, the lower layer wide wiring is composed of a plurality of lower narrow wirings and the connecting portion 3e for connecting two adjacent narrow wirings among them, whereby the wiring resistance can be reduced. .

[Brief description of drawings]

FIG. 1 is a plan view of a lower wiring portion of a first embodiment of a semiconductor device of the present invention.

FIG. 2 is an enlarged cross-sectional view showing each step of the first embodiment of the manufacturing method of the present invention.

FIG. 3 is a plan view of a lower wiring portion of a second embodiment of the semiconductor device of the present invention.

FIG. 4 is a plan view of a lower wiring portion of an example of a conventional semiconductor device.

5A to 5C are enlarged cross-sectional views showing the main part of FIG. 4 in the order of steps.

FIG. 6 is a diagram showing an example of a pattern described in JP-A-2-22843.

FIG. 7 is a cross-sectional view of an example of a semiconductor device described in JP-A-2-22843.

FIG. 8 is a diagram showing another example of the pattern described in Japanese Patent Application Laid-Open No. 2-22843.

FIG. 9 is a diagram showing an example of a split pattern described in JP-A-2-22843.

FIG. 10 is a diagram showing another example of the split pattern described in Japanese Patent Application Laid-Open No. 2-22843.

FIG. 11 is a cross-sectional view of a conventional semiconductor device proposed in Japanese Patent Laid-Open No. 2-22843.

FIG. 12 is a cross-sectional view illustrating an example of a conventional manufacturing method described in Japanese Patent Laid-Open No. 3-136330.

FIG. 13 is a cross-sectional view illustrating an example of a conventional manufacturing method proposed in Japanese Patent Laid-Open No. 3-136330.

FIG. 14 is a cross-sectional view illustrating another example of the conventional manufacturing method proposed in Japanese Patent Laid-Open No. 3-136330.

FIG. 15 is a cross-sectional view and a plan view of an example of a lower layer wiring portion described in Japanese Patent Publication No. 2-21138.

FIG. 16 is a cross-sectional view and a plan view of an example of a lower layer wiring portion of a semiconductor device proposed in Japanese Patent Publication No. 2-21138.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Insulating film 3a Lower layer narrow wiring 3b, 3d Lower layer wide wiring 3c1 to 3c4 Narrow wiring 3e Connection portion 4 Interlayer insulating film 4a First interlayer insulating film 4b Second interlayer insulating film 5 Flattening coating film 6 through holes

Claims (7)

[Claims] 1. A semiconductor device having a multilayer wiring structure in which a plurality of wiring layers are formed on a semiconductor substrate with an interlayer insulating film interposed therebetween, wherein lower wide wirings of a lower wiring layer under the interlayer insulating film have wiring widths of one another. A semiconductor device comprising a plurality of narrow wirings arranged close to each other in a direction. 2. The semiconductor device according to claim 1, wherein each of the plurality of narrow wirings has a line width which is 1 to 3 times the line width of the lower layer narrow wiring. 3. The plurality of narrow wirings are formed such that a line width at a position connected to each through hole is substantially equal to a line width of the lower narrow wiring.
The semiconductor device described. 4. A method of manufacturing a semiconductor device having a multilayer wiring structure in which a plurality of wiring layers are formed on a semiconductor substrate via an interlayer insulating film, wherein a lower narrow wiring and a wiring width are mutually formed on the semiconductor substrate or the insulating film. Forming a lower wide wiring consisting of a plurality of narrow wirings arranged close to each other in the direction, and a first interlayer insulating film on the entire surface including the lower narrow wiring and the plurality of narrow wirings. And a step of forming a flattening coating film on the first interlayer insulating film so that the surface is substantially flat, and a flattening coating above the inter-wiring region of the flattening coating film. Manufacturing a semiconductor device comprising: a step of etching back so as to leave only a film portion; and a step of forming a second interlayer insulating film on the entire surface including the flattened coating film that has been etched back. Method. 5. A step of applying a flattening coating film on the first interlayer insulating film to a film thickness of a predetermined value or less, and the second interlayer on the flattening coating film without performing the etching back. 5. The method of manufacturing a semiconductor device according to claim 4, further comprising the step of forming an insulating film by coating. 6. A semiconductor device having a multi-layer wiring structure in which a plurality of wiring layers are formed on a semiconductor substrate with an interlayer insulating film interposed therebetween, wherein a lower wide wiring of a lower wiring layer under the interlayer insulating film has a mutual wiring width. Is composed of a plurality of narrow wirings arranged close to each other in the direction
A semiconductor device in which adjacent narrow wirings of the plurality of narrow wirings are connected at a predetermined interval by a connecting portion having a length of 3 times. 7. A method of manufacturing a semiconductor device having a multi-layer wiring structure in which a plurality of wiring layers are formed on a semiconductor substrate via an interlayer insulating film, wherein a lower narrow wiring and a wiring width are mutually formed on the semiconductor substrate or the insulating film. Narrow wirings that are arranged close to each other in the wiring length direction and are connected at a predetermined interval between adjacent narrow wirings by a connecting portion having a length 1 to 3 times the line width of the lower narrow wiring in the wiring length direction. A step of forming a lower wide wiring formed of: a step of forming a first interlayer insulating film over the entire surface of the layer including the lower narrow wiring and a plurality of narrow wiring; A step of forming a flattening coating film on the film so that the surface is substantially flat, and a step of etching back so as to leave only the flattening coating film portion above the inter-wiring region of the flattening coating film, The entire surface including the flattened coating film that has been etched back The method of manufacturing a semiconductor device which comprises a step of coating a second interlayer insulating film.