JPH05275539A - Method of manufacturing semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate the photographing step and the etching away step by a method wherein the flattening step of the insulating film interposed between a conductor wiring and another conductor wiring as well as the making step of a contact hole for connecting metallic wirings are simultaneously performed. CONSTITUTION:A metallic wiring 3 is formed and then an interlayer insulating film B is deposited thereon. Next, when a resist A5 in the inverse state of the metallic wiring 3 is formed to be coated with another resist B6, the surface of the resist 6 is flattened regardless of the existence of the metallic wiring 3. Next, the resist B6 for flattening is patterned to make a viahole. Later, the flattening step of the resist and an interlayer insulating film B4 as well as the taper etching step of the viahole 7 are performed simultaneously. Accordingly, the photographing step and the etching away step can be eliminated. Furthermore, the inside of the viahole 7 can take a taper shape thereby enabling the step coverage to be enhanced while avoiding the disconnection inside the viahole 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip manufacturing method in a semiconductor manufacturing process.

[0002]

2. Description of the Related Art In the VLSI manufacturing process, elements are becoming finer and higher in density. Further, as the density of the device increases, the metal wiring length becomes longer, and the wiring width and wiring space become narrower. Further, since the unevenness of the interlayer insulating film is becoming large, it is also very important to flatten the interlayer insulating film. Currently, the SOG is mainly used for the flattening process of the insulating film.
A flattening process using, a method of etching back a resist and an interlayer insulating film, etc. are mainly used.

FIG. 4 is a sectional view of a semiconductor device showing a conventional method of flattening an interlayer insulating film by an etch back method. In FIG. 4, reference numeral 1 is a silicon substrate for forming active elements such as transistors. Reference numeral 2 is an interlayer insulating film A. Usually, after forming an element such as a MOS transistor on the silicon substrate 1, the interlayer insulating film A is deposited.
As the interlayer insulating film A, for example, a BPSG film or the like is used. 3 is a metal wiring such as an AlSiCu film.
The metal wiring 3 and an active element such as a MOS transistor are usually connected by a contact hole. An interlayer insulating film B 4 is for insulating between the metal wiring 3 and the upper metal wiring. 5 is a resist A, which is usually
It is a reverse pattern (shrinked to some extent) of the pattern of the metal wiring 3. 6 is a resist B. By coating the resist, the resist surface is flattened by the resist A and the resist B of 5. Reference numeral 7 is a contact hole [via hole] for connecting the metal wiring 3 and the upper metal wiring.
]]. (Hereinafter, contact holes between metal wirings are
It is described as a hole. ) 8 is a resist for via hole etching.

The conventional process will be described below with reference to FIG. (A) shows a state in which the metal wiring 3 is formed on the insulating film 2 and the interlayer insulating film B4 is deposited on the metal wiring 3.
(B) shows a state in which the resist A5 which is the inverted state of the metal wiring 3 is formed. (C) is a state in which the resist 6 is coated, and the resist surface is in a flat state comparing the region where the metal wiring 3 is present and the region where it is not present. (D) is a state in which the resist and the interlayer insulating film B are etched back (selection ratio of dry etching between the resist and the interlayer insulating film is 1: 1), and the interlayer insulating film is flat. (E) is a state in which a resist pattern for via holes is formed, and (f) is a state in which the via pattern is formed on the interlayer insulating film B.
This is a state in which a hole is opened by etching. Then, the second metal wiring is sputtered and the metal wiring 3 and the second metal wiring are connected by a via hole.

[0005]

However, in the above manufacturing method, the photo step is required twice for the planarization of the interlayer insulating film and the opening of the via hole. Further, dry etching also requires etching twice for etching back and for opening via holes. Therefore, the number of processing steps increases, which is disadvantageous in terms of cost. In addition, dust generation also increases due to an increase in the number of processing steps. Furthermore, via
In the hole etching, since the etching shape becomes vertical, the step coverage in the subsequent metal film sputtering becomes a problem. That is, disconnection or the like occurs in the via hole.

[0006]

In order to solve the above problems, a method of manufacturing a semiconductor device according to the present invention comprises a step of flattening an insulating film existing between a metal wiring and another metal wiring, and a metal wiring. A method of manufacturing a semiconductor device is characterized in that the step of opening a contact hole connecting the two is simultaneously performed.

[0007]

According to the present invention, the step of flattening an insulating film existing between a metal wiring and another metal wiring and the step of opening a contact hole [via hole] for connecting the metal wirings are simultaneously performed. And a resist used for planarization and a resist for via holes. Further, flattening and dry etching of via holes are performed at the same time. Therefore, the photo process and the dry etching process are respectively reduced once, and the effect is very large in terms of time and work. Furthermore, v
Since the resist for opening the ia hole has some taper, the resist recedes in the lateral direction when the dry etching selectivity between the resist and the interlayer insulating film is close to, for example, 1: 1. Therefore, the shape of the via hole is
Become a dad. Therefore, the step coverage is improved and v
It is possible to prevent disconnection in the ia hole.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a semiconductor device according to an embodiment of the present invention will be described below with reference to FIG. In FIG. 1, reference numeral 1 is a silicon substrate for forming elements such as transistors. Two
Is an interlayer insulating film A. Usually, after forming the element on the silicon substrate 1, the interlayer insulating film A is deposited. Interlayer insulation film A
Is, for example, a BPSG film. 3 is a metal wiring such as an AlSiCu film. The metal wiring 3 and the element are usually connected by a contact hole formed in the lower layer. An interlayer insulating film B 4 is for insulating between the metal wiring 3 and the upper metal wiring. 5 is resist A
And is usually an inverted pattern of the pattern of the metal wiring 3 (shrinked to some extent). Reference numeral 6 is a resist B, and by coating the resist on the entire surface, the resist surface is flattened by the resist A and the resist B of 5.
Reference numeral 7 denotes a via hole resist pattern, which connects the metal wiring 3 and the upper metal wiring after opening the interlayer insulating film B.

The steps (a) to (d) will be sequentially described below. (A) shows a state in which the metal wiring 3 is formed and the interlayer insulating film B is deposited on the metal wiring 3. (B) shows a state in which the resist A5 which is the inverted state of the metal wiring 3 is formed. (C) is a state in which the resist 6 is coated, and the resist surface is in a flat state comparing the region where the metal wiring 3 is present and the region where it is not present. (D) is
This is a state in which patterning is performed to open the via holes in the resist B for flattening. That is, (d)
Flattened by etching back the interlayer insulating film B and v
This is the state before the etching of the ia holes is performed at the same time.

(E) to (h) show the planarization and the etching of the via hole with time. The resist and the interlayer insulating film B are planarized and the via holes are simultaneously etched, and finally the interlayer insulating film B is planarized and via.
The taper etching of the holes is performed.

The changes over time in the etching shown in FIGS. 2A to 2E are shown in detail. FIG. 2 shows an example in which the dry etching selection ratio between the resists A and B and the interlayer insulating film B is 1: 1. FIG. 2A shows the state of FIG. The state of (b) is a state in which the resist and the via hole are being etched, and the state of (c) is a state in which the interlayer insulating film B on the metal wiring 3 other than the via hole appears. In the state of (c), the via hole is just opened. In the state (d), the resist on the region where the metal wiring 3 does not exist is also etched and disappeared. Further etching is performed, and the state of (e) is reached, and the flattening and the etching of the via holes are completed. The end result is about 40% via hole overetch. Furthermore, when the via hole is opened, the resist recedes in the lateral direction, so that the via hole has a tail.
You have a party.

In the present embodiment, the wiring is a metal wiring (eg AlSiCu), but silicide or Poly is used.
Conductor wiring such as Si may be used. Also, flattening and via ho
In the dry etching for the opening of the opening, the selection ratio of the dry etching to the interlayer insulating film of the resist used is 1 in this embodiment, but may be in the range of 0.5 to 1.5.

FIG. 3 is a sectional view of a semiconductor device according to another embodiment. Comparing FIG. 3 with FIG. 2, in this example, except that there is no resist A which is a reverse resist of metal wiring,
Same process. That is, the step of forming the reverse resist of the metal wiring and the mask are unnecessary.

The steps will be described below with reference to FIG.
1A shows a state in which the metal wiring 3 is formed and the interlayer insulating film B is deposited on the metal wiring 3, which is the same state as FIG. 1A. (B) is a state in which the resist 8 is coated.
Since the resist is applied by spin coating, it flows to a portion having a low step, that is, a portion having no metal wiring. Further, the resist becomes thinner at the end of the metal wiring. Then, a resist is opened for the via hole. Therefore, the state of (c) is obtained. After that, the interlayer insulating film B is flattened and the via holes are simultaneously etched. The selection ratio between the resist and the interlayer insulating film B is, for example, 1: 1. (D) is a state during etching. The interlayer insulating film B4 appears from the end portion on the metal wiring where the resist is thin, and is etched. Therefore, although it is not possible to perform almost complete flattening as in the first embodiment, some flattening is possible. Eventually, it becomes the state of (e),
The planarization of the interlayer insulating film B and the etching of the via holes are completed.

Also in this embodiment, metal wiring (eg, Al
(SiCu), but conductor wiring such as silicide or PolySi may be used. Further, the selection ratio of the dry etching of the resist used to the interlayer insulating film may be in the range of 0.5 to 1.5.

[0016]

As described above, the step of flattening the insulating film existing between the conductor wiring and another conductor wiring and the contact hole [via hole] for connecting the metal wirings are opened. By performing the steps at the same time, the number of photo steps and the number of etching steps can be reduced. Further, since the via hole has a taper, there is no fear of disconnection between metal wirings. Therefore, the effect of the present invention is very large.

[Brief description of drawings]

FIG. 1 is a sectional view showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a change with time in etching in the first embodiment of the present invention.

FIG. 3 is a sectional view showing a method of manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 4 is a sectional view showing a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Interlayer insulating film A 3 Metal wiring (Example: AlSiCu) 4 Interlayer insulating film B 5 Resist A 6 Resist B 7 via hole 8 via hole resist

Claims (4)

[Claims] 1. A method of manufacturing a semiconductor device, wherein a step of flattening an insulating film existing between a conductor wiring and another conductor wiring and a step of opening a contact hole for connecting the conductor wiring are performed at the same time. Method. 2. A step of forming a resist on an interlayer insulating film existing on a metal wiring, a step of forming a pattern for opening a contact hole in the resist, and a step between the metal wiring using the resist. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of sequentially planarizing an interlayer insulating film and opening a contact hole. 3. A step of forming a metal wiring, a step of depositing an interlayer insulating film for insulation on the metal wiring, and a step of forming a reverse resist pattern of the metal wiring pattern, and then uniformly applying a resist over the entire surface. And a step of forming a pattern for opening a contact hole in the resist, and a step of planarizing the interlayer insulating film and opening the contact hole at the same time. A method for manufacturing a semiconductor device according to claim 1 or 2. 4. In the dry etching for flattening an interlayer insulating film and opening a contact hole, the selection ratio of the dry etching of the resist used to the interlayer insulating film is 0.5 to.
Use in the range of 1.5, 1.
2. The method for manufacturing a semiconductor device according to any one of 2 and 3.