JP3130726B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a multilayer wiring structure and a method of manufacturing the same.

In a semiconductor device having a multilayer wiring structure, if a step is caused by a lower wiring, it is difficult to form an upper wiring with high reliability. Therefore, it is necessary to flatten the above-mentioned step during manufacturing. .

[0003]

2. Description of the Related Art FIG. 4 is a plan view showing a lower wiring portion of an example of a conventional semiconductor device, and FIGS. 5A and 5B are enlarged cross-sectional views showing the main steps of FIG. In this conventional semiconductor device, first, as shown in FIG. 5A, a lower-layer narrow wiring 3a and a lower-layer wide wiring 3e made of, for example, an aluminum film are formed on a semiconductor substrate 1 with an insulating film 2 interposed therebetween. . Subsequently, a first interlayer insulating film 4a made of, for example, a plasma oxide film and having a thickness half that of the interlayer insulating film to be finally obtained is formed. Next, a flattening coating film 5 of, for example, an inorganic or organic silica film is formed by a spin-on-glass method so as to fill a step in the inter-wiring region of the first interlayer insulating film 4a.

[0005] Next, as shown in FIG. 5 (B), portions of the flattening coating film 5 formed on the wirings 3 a and 3 f are removed.
The etching back is performed under the condition that the etching rates of the flattening coating film 5 and the first interlayer insulating film 4a are almost the same so that the flattening coating film 5 is removed and the flattening coating film 5 is left only in the inter-wiring region. Next, for example, a second interlayer insulating film 4b made of a plasma oxide film is formed, and a flat interlayer insulating film 4 is formed.

In this manner, as shown in FIG. 4, a semiconductor in which the lower layer narrow wiring 3a and the lower layer wide wiring 3f are formed on the semiconductor substrate 1 and the through holes 6a and 6b are opened respectively. The device is created.

Further, a conventional method for planarizing an interlayer insulating film in a semiconductor device having a multilayer wiring structure is disclosed in
The one described in JP-A-22843 is known. When a flat interlayer insulating film is formed by using a conventional bias sputtering method or a bias ECR method, a thin first electrode formed on diffusion layers 11 and 12 is formed as shown in FIGS. 13 or wirings 16-1 formed on the substrate 15
8, the narrow wiring 16 and the narrow wiring 20 are easily flattened, but the contact parts 14 and 21 between the electrode 13 or the wiring 20 and the second wiring, the wide wiring 17, 18
On the pattern (1), the interlayer insulating film 19 and the like are not flattened unless the film thickness is sufficiently large. On the other hand, if the interlayer insulating film is too thick, the aspect ratio of the contact hole becomes large, and the contact yield and reliability are increased. An object of the present invention is to solve the disadvantage that the performance is greatly deteriorated.

That is, in this conventional apparatus, FIGS.
As shown in FIG. 3, contact portions between the first electrode 13 or the wiring 20 and the second wiring are formed at 14a to 14d or 21a to 21d.
A split pattern (a pattern in which a thick wiring is originally divided into a set of thin linear patterns represented by comb teeth) as shown in 21d, or the wiring 18 is divided into narrow wirings 18a Things.

Thus, according to this conventional device, all the electrodes or wirings have a thin linear pattern including the contact portion. Therefore, an interlayer insulating film formed thereon by a bias sputtering method or a bias ECR method. Figure 11
Can be formed with a film thickness that is all flat and the aspect ratio does not become too large, thus improving the yield and reliability of the high-density integrated circuit. is there.

As another method of flattening an interlayer insulating film in a conventional semiconductor device having a multilayer wiring structure, a method described in Japanese Patent Application Laid-Open No. 3-136330 is known. As shown in FIG. 12, an electrode 32a and wirings 32b and 32c are formed on a semiconductor substrate 31, and then a Si
When the interlayer insulating film 33 made of O ₂ or the like is formed,
An electrode 32a or a wiring 32b formed on the interlayer insulating film 33;
The object of the present invention is to solve the drawback of the method of flattening the surface by applying an insulating coating film 35 such as polyimide containing Si or BSG in order to flatten the irregularities due to 32c, and then performing a heat treatment. is there.

[0010] The above-mentioned drawbacks cause a dent to remain between the wirings in a portion where the wiring interval is wide, and in some cases, disconnection or residual metal may occur at the time of forming an upper layer wiring, thereby lowering the reliability and yield of the semiconductor device. That is. In the conventional method described above, in order to solve this drawback, as shown in FIGS. 13 and 14, the electrodes 32a and the wirings 32b and 32b are used.
After the SiO ₂ film 33 is formed on the semiconductor substrate 31 on which the unevenness due to c is formed by the CVD method so as to have the same thickness as the electrodes 32a and the wirings 32b and 32c,
₂ is covered with the concave portions of the film 33, and the electrode 32a and the wiring 3
A photoresist pattern 34 is formed such that the upper portions of the protrusions formed by 2b and 32c are exposed.

Next, the SiO ₂ film 33 on the upper and side portions or only the upper portions of the electrodes 32a and the wirings 32b and 32c is removed by wet etching, and the photoresist pattern 34 is further removed. Then, as a second insulating film,
The SiO ₂ film 33a or the insulating coating film 35 is formed so as to fill the recess, so that a flat interlayer insulating film can be formed regardless of the wiring interval.

Further, as another flattening method of an interlayer insulating film in a conventional semiconductor device having a multilayer wiring structure, a semiconductor device described in Japanese Patent Publication No. 2-2138 is known. As shown in FIG. 15, lower wirings 43a and 43b are formed on the surface of an insulating film 42 on a semiconductor substrate 41, and then an interlayer insulating film 44 is deposited thereon. For example, when an organic resin such as a photoresist resin is spin-coated, a hardening process is performed, and the organic resin and the insulating film 44 are etched back at substantially the same speed to planarize the interlayer insulating film 44. The purpose of this is to take measures.

That is, in the above case, since the organic resin film thickness at the time of application increases as the line width of the lower wiring increases, the lower wiring 4 having a narrow line width after etching back flattening.
An extremely thick interlayer insulating film 44 remains on the lower wiring 43a having a wider line width than on the lower wiring 3b. For this reason, the through hole 45a formed on the lower wiring 43a having a large line width is much deeper than the through hole 45b formed on the lower wiring 43b having a small line width, and the step coverage of the upper wiring is reduced. However, there is a problem in reliability that the upper layer wiring is broken due to electromigration.

Thus, in this conventional semiconductor device, FIG.
As shown in FIG. 6, by providing a lower wiring extraction pattern 46 between a plurality of through holes 45a formed on the lower wiring 43a having a large line width, the through holes 45a are formed.
The coating thickness of the organic resin at the formation location a is almost the same as the coating thickness on the lower wiring 43b having a small line width, and the film of the interlayer insulating film 44 in the through-hole portion is independent of the line width after the etching back flattening. Since the thicknesses are almost the same, the depths of the through holes 45a and 45b can be formed almost the same.
This is to prevent disconnection of the upper wiring due to electromigration at the through hole.

[0015]

However, in the conventional semiconductor device shown in FIGS. 4 and 5, after the flattening coating film 5 is formed, etching back is performed for flattening. The coating film 5 has a characteristic that it is formed only extremely thinly on the lower layer narrow wiring 3a such as inside the element, whereas it is formed thicker on the lower layer wide wiring 3f. Therefore, etching back is performed, and the finally formed interlayer insulating film 4 is formed.
In this case, a difference in film thickness occurs between the two wirings 3a and 3f, and the thickness on the lower layer wide wiring 3f becomes thick.

For this reason, shape variations having different aspect ratios occur in the through holes 6a and 6b formed on the lower narrow wiring 3a and the lower wide wiring 3f, and the step coverage of the upper wiring is reduced. There is a problem that the reliability of the system and the yield of the semiconductor device are reduced.

Further, when the thick flattening coating film layer is exposed on the side wall of the through-hole, moisture and the like are easily adsorbed, and when the upper wiring is formed, the release of the moisture and the like causes conduction failure, so that the flattening coating is applied to the through-hole opening. The flattened coating film 5 is formed so that the film 5 hardly remains (so that the film 5 remains thin).
Need to be etched back. For this reason, the excessive flattened coating film 5 thickly formed on the lower layer wide wiring 3f.
It takes a long time to etch back. However, the etching back is performed under the condition that the etching rates of the flattening coating film 5 and the first interlayer insulating film 4a are substantially the same. 4 and FIG. 5, the flatness of the semiconductor device shown in FIGS. 4 and 5 is deteriorated as compared with the flatness when the flattening coating film 5 is applied. There is also.

In the conventional semiconductor device described in Japanese Patent Application Laid-Open No. 2-22843, the thickness of the gate electrode 13 is reduced as in the basic cell pattern of a gate array using MOS transistors as shown in FIG. Contact section 14
Is the largest of all gate electrode patterns, and at most 3 to
For a pattern that is four times as large, FIG.
As shown in FIG. 14D, the contact portion is formed into a split pattern, and the entire line including the contact portion can be formed by a thin linear pattern.

However, in the wiring patterns such as the first layer wiring and the second layer wiring, the power supply and the ground wiring generally have a line width of several tens μm to several hundred μm in order to prevent a voltage drop or the like.
Thick wiring is used, and for a pattern in which the maximum thickness of all wiring patterns is about several tens μm to several hundred μm, the through-hole part is a split pattern,
It is not practical to form all of these thick wirings including the through-holes in a thin linear pattern because the wiring resistance increases, and this conventional device is applied to wiring patterns such as a first layer wiring and a second layer wiring. It is difficult to do.

In addition, it is possible to apply this conventional device by forming the above-mentioned thick wiring from a line segment having a certain practical thickness. In this case, however, a flat interlayer insulating film is formed. To form the film, the film thickness is inevitably increased, the aspect ratio of the through hole is increased, and the problem that the yield and reliability of the through hole are largely deteriorated remains.

In the conventional semiconductor device described in Japanese Patent Application Laid-Open No. 3-136330, as shown in FIGS. 13 and 14, after a photoresist pattern 34 is formed, it is formed on the electrodes 32a and the wirings 32b and 32c. SiO ₂
Although the film 33 is removed by wet etching, since the wet etching is isotropic etching, as shown in FIG.
b, and removed to between the SiO ₂ film 33 side of the 32c, SiO ₂ covered with the photoresist pattern 34
The film 33 is also side-etched in the lateral direction by the thickness.

This is because, for example, the line width / interval is 1.0
In the case of μm / 1.0 μm and the wiring thickness of 0.5 μm, at the interval of 2.0 μm or less where the photoresist pattern 34 is formed, and in the case of the wiring thickness of 1.0 μm,
Similarly, there is a problem that the SiO ₂ film 33 does not remain by the side etching at the interval of 4.0 μm or less, and the interlayer insulating film cannot be flattened at the same location.

As shown in FIG. 14B, the SiO ₂ film 33 over the electrodes 32a and the wirings 32b and 32c is formed.
The above problem can be solved by stopping the wet etching at the time when is removed by etching, but in any case, the electrode 32a and the wirings 32b and 32c
Since the wet etching solution comes into contact with the substrate, there is a problem that the wet etching solution is damaged by erosion and the like, and the reliability of the wiring is reduced. Further, there is a problem that the number of manufacturing steps increases, such as an increase in the number of alignment exposure steps in order to form the photoresist pattern 34, and the manufacturing time increases.

Further, in the conventional semiconductor device described in Japanese Patent Publication No. 2-2138, as shown in FIG. 16, a through hole 45b on a lower wiring 43b having a small line width and a lower wiring 43a having a wide line width are formed. To make the depth of the through hole 45a substantially the same as that of the through hole 45a, a plurality of through holes 4
The lower wiring pattern 46 is provided between the wirings 5a. However, in this case, a very thick interlayer insulating film 44 still remains on the lower wiring 43a having a large line width except for the region where the through hole 45a is formed. Is poor in the flatness of a typical interlayer insulating film, and when wiring is formed in multiple layers thereon, the absolute step becomes larger and larger in regions other than the region where the through hole 45a is formed, which is not suitable for multilayering. .

In this conventional apparatus, an interlayer insulating film having a thickness equal to or greater than the thickness of a lower wiring layer (step) is formed, a photoresist resin is applied and etched back, and a flat surface shape of the photoresist resin is transferred. Is what you do. However, in order to obtain a photoresist resin having a flat surface shape, a thickness of about 1.0 μm is required, and it is necessary to etch back the photoresist resin and the protrusions of the interlayer insulating film formed on the lower wiring. Since it takes a long time, it is difficult to end the etching back so as to obtain an optimum flat shape with great reproducibility with a large variation in etching. For this reason, depending on the wafer, there is a problem that the film thickness is generated in the interlayer insulating film on the lower wiring, and the depth of the through hole varies.

Further, the etching back is performed under the etching conditions at which the photoresist resin and the interlayer insulating film have almost the same speed. However, if a long time is required for the etching back, the difference between the two etching speeds becomes remarkable. Also, there is a problem that the flatness after etching back is deteriorated as compared with the flatness when forming the photoresist resin.

The present invention has been made in view of the above points, and it is an object of the present invention to provide a semiconductor device capable of preventing a thickness difference from occurring in an interlayer insulating film formed on a lower narrow wiring and a lower wide wiring. It is intended to provide a manufacturing method.

[0028]

In order to achieve the above object, a semiconductor device according to the present invention comprises a semiconductor substrate and the semiconductor substrate.
An insulating film on the board, and a lower narrow wiring and a lower layer thick on the insulating film.
A lower layer wiring composed of a width wiring, the insulating film and the lower layer
A first interlayer insulating film on the wiring, and a first interlayer insulating film on the first interlayer insulating film;
Flattening coating film, and a second interlayer insulation on the flattening coating film
An edge film, and at least the
Via a first interlayer insulating film and the second interlayer insulating film,
Lower wiring and upper wiring formed on the second interlayer insulating film
In a semiconductor device including a through-hole for connecting a line , the lower-layer wide wiring is composed of a narrow wiring divided into a plurality of wirings, and the narrow wirings are closely separated from each other in a wiring width direction. Are arranged, each having a line width of 1 to 3 times the line width of the lower layer narrow wiring, and two adjacent ones of the plurality of narrow wirings are arranged in the wiring length direction of the lower layer wide wiring. The connection is made by a connection portion having a length of 1 to 3 times the line width of the lower layer narrow wiring.

Further, a method of manufacturing a semiconductor device according to the present invention
A semiconductor substrate; an insulating film on the semiconductor substrate;
Lower layer wiring consisting of lower layer narrow wiring and lower layer wide wiring on the film
And a first interlayer insulating film on the insulating film and on the lower wiring
A planarizing coating film on the first interlayer insulating film;
A second interlayer insulating film on the supported coating film, and the lower wiring region
Forming at least the first interlayer insulating film and the second
The lower wiring and the second interlayer through two interlayer insulating films.
Through holes for connecting to the upper wiring formed on the insulating film
In a method of manufacturing a semiconductor device including
A lower-layer narrow wiring on an insulating film covered and formed on a body substrate ,
It is composed of a narrow wiring divided into a plurality of wirings, the narrow wirings are arranged close to each other in the wiring width direction, and each has a line width of 1 to 3 times the line width of the lower layer narrow wiring,
Two adjacent narrow wires among the plurality of narrow wires are connected to each other by a connection portion having a length of 1 to 3 times the line width of the lower narrow wire in the wiring length direction of the lower thick wire. Lower layer consisting of wiring
Forming a wiring, on the entire surface including the lower wiring, the coating formed so that the step of coating a first interlayer insulating film, the surface planarization coating film on the first interlayer insulating film becomes substantially flat And etching back so as to leave only the portion of the flattening coating film above the inter-wiring region in the flattening coating film, and forming a second interlayer insulating film on the entire surface including the etched back flattening coating film. Forming a first layer,
An opening is formed in the interlayer insulating film and the second interlayer insulating film to form a lower layer.
The wiring is connected to an upper wiring formed on the second interlayer insulating film.
Forming a through hole for connection
It is what it was. Further, manufacture of the semiconductor device of the present invention.
The method includes forming a flattened coating film on the first interlayer insulating film.
Coating to a film thickness less than or equal to the value, and etching back
The second interlayer insulation on the flattened coating film without performing
Covering the edge film.

[0030]

According to the present invention, the lower wide wiring of the lower wiring layer is constituted by a plurality of narrow wirings arranged close to each other in the width direction of the wiring, and the line width of each of the plurality of narrow wirings is reduced. Since the line width is about 1 to 3 times the line width of the lower-layer narrow wiring, the flattening coating film formed on the lower-layer wiring layer is thinner. And can be formed with almost no difference in film thickness. Further, split
Two adjacent narrow wirings out of a plurality of narrow wirings
Of the line width of the lower layer narrow wiring in the wiring length direction of the lower layer wide wiring.
The layers are connected by the connection part of 1-3 times length.
Wiring resistance of lower wide wiring without deteriorating the flatness of the inter-insulation film
Can be reduced.

[0031]

Next, an embodiment of the present invention will be described. FIG. 1 is a plan view showing a lower wiring section of a reference example of a semiconductor device according to the present invention. As shown in FIG. 1, a lower-layer narrow wiring 3a and a lower-layer wide wiring 3b are formed on a semiconductor substrate 1. This reference example is characterized in that is constituted by the lower layer wide interconnect 3b 3 pieces of narrow wiring 3c1,3c2 and 3c3.

Each of the narrow wirings 3c1, 3c2, and 3c3 has a line width that is one to three times the line width of the lower layer narrow wiring 3a, and is arranged close to and away from and parallel to the wiring width direction.
Further, each of the narrow wires 3c1, 3c2 and 3c3 has a tip portion branched into two branches, and the line width of each branch portion is formed substantially equal to the line width of the lower layer narrow wire 3a. This branch is connected to the through hole 6.

Next, a reference example of the method of the present invention for manufacturing the semiconductor device shown in FIG. 1 will be described with reference to FIG. FIG.
1 is an enlarged sectional view of a portion along the line XX 'in FIG. 1 in each manufacturing step, and the same components as those in FIG. 1 are denoted by the same reference numerals. As shown in FIG. 2A, first, on a semiconductor substrate 1 made of, for example, silicon (Si), a lower layer narrow wiring 3a made of, for example, an aluminum (Al) film via an insulating film 2 made of, for example, SiO2; Plural narrow wirings 3c1
Is formed.

At this time, the narrow wiring 3 c 1 has a line width that is three times the line width of the lower narrow wiring 3 a, and has the same line width as the lower narrow wiring 3 a at the through hole opening. Formed.

Next, a first interlayer insulating film 4 a made of, for example, a plasma oxide film having a thickness of about half the thickness of the interlayer insulating film to be finally obtained is formed. Next, spin
For example, a flattening coating film 5 such as an inorganic or organic silica film is formed by an on-glass method so as to fill a step in an inter-wiring region such as a lower narrow wiring 3a and a plurality of narrow wirings 3c1.

Next, as shown in FIG. 2B, the flattening coating film 5 formed on the wirings 3a and 3b is removed, and the flattening coating film 5 is left only in the region between the wirings. Etching back is performed by RIE (Reactive Ion Etching) under the condition that the etching rates of the coating film 5 and the first interlayer insulating film 4a are almost the same. Subsequently, a second interlayer insulating film 4b made of, for example, a plasma oxide film is
The surface of the flattening coating film 5 and the first interlayer insulating film 4a above the inter-wiring region is formed by coating to form a flat interlayer insulating film 4. Thereafter, through holes 6 connected to required positions of the lower-layer narrow wiring 3a and the lower-layer wide wiring 3b are opened.

According to the present reference example, three narrow lines 3c1
To 3c3 are connected to the upper layer wiring (not shown) to which the lower layer wide wiring 3b is to be connected via the through hole 6, so that each of the lower layer narrow wirings 3a has one line width.
Since one lower thick wiring 3b is constituted by three narrow wirings 3c1 to 3c3 having a line width of about 3 times, a flattening coating film 5 is conventionally formed on these lower wirings 3a and 3b. And can be formed without a difference in film thickness.

Therefore, at the time of the etching back,
It is only necessary to remove the thin and flat coating film 5 applied above the lower wirings 3a and 3b without any difference in film thickness.
Therefore, only a short time is required for etching back. Therefore, the variation of the etching back is small, and the flatness is hardly deteriorated, so that the etching back can be easily performed.

When the flattening coating film 5 applied above the lower wirings 3a and 3b can be formed to be thinner than usual at about 1000 ° or less, even if the flattening coating film layer is exposed on the side wall of the through hole. The present inventor has confirmed that there is no adverse effect such as causing conduction failure during the formation of the upper layer wiring due to adsorption or release of moisture or the like. In this case, it is not necessary to perform the above-described overall etching back. In this case, the interlayer insulating film 4 can be formed with excellent flatness of the flattening coating film 5.

[0040] Thus, the lower narrow wiring in the present reference example 3
Since there is no difference in film thickness above the upper wiring 3a and the lower layer wide wiring 3b and the interlayer insulating film 4 can be formed, there is no variation in the shape of the through holes 6 formed above both wirings 3a and 3b, and the upper wiring Can obtain a stable step coverage.

Next, a description will be given of an embodiment of the present invention a semiconductor device. FIG. 3 is a plan view showing a lower wiring portion of one embodiment of the semiconductor device according to the present invention. In the figure, the same components as those in FIG. 1 are denoted by the same reference numerals. In the embodiment shown in FIG. 3, the lower thick wiring 3d has four narrow wirings 3c1 each having a line width of about 1 to 3 times the line width of the lower thin wiring 3a.
3c4 and a connecting portion 3e connecting two adjacent narrow wires among the narrow wires 3c1 to 3c4.

The connecting portions 3e have a length of 1 to 3 times the line width of the lower narrow wiring 3a in the wiring length direction of the lower thick wiring 3d, and are formed at intervals of 10 μm to 200 μm. Things. Thereby, according to the present embodiment,
There is an effect that the wiring resistance of the lower thick wiring 3d can be reduced without impairing the flatness of the interlayer insulating film 4.

The method of manufacturing the semiconductor device according to the present embodiment is shown in FIG.
3 is basically the same as that of the reference example shown in FIG. 3, and the shape (pattern) of a wiring pattern mask for patterning the lower layer narrow wiring 3a and the lower layer wide wiring 3d on the semiconductor substrate 1 is shown in FIG.
All you have to do is change it to the one shown in.

[0044]

As described above, according to the present invention,
Make the flattening coating film formed on the lower wiring layer thin,
Since there is almost no difference in film thickness between the lower layer narrow wiring and the plurality of narrow lines, there is no difference in film thickness between the lower layer narrow wiring and the plurality of narrow lines. In addition, an interlayer insulating film with improved flatness can be formed. For this reason, it is possible to prevent variations in the shape of the through hole formed for each of the lower layer narrow wiring and the plurality of narrow wirings, and to obtain stable step coverage of the upper layer wiring. The reliability of the semiconductor device and the yield of the semiconductor device can be improved as compared with the related art.

Further, according to the present invention, when the flattening coating film applied above the lower wiring can be formed to be thinner than usual at about 1000 ° or less, the flattening coating film formed on the lower wiring is formed. Since the etching back for removing and removing the flattening coating film only in the inter-wiring region can be eliminated, the number of manufacturing steps can be reduced as compared with the related art. In addition, the lower layer wide wiring is composed of a plurality of lower layer narrow wirings and a connecting portion 3e connecting between two adjacent narrow wirings, whereby the wiring resistance can be reduced. .

[Brief description of the drawings]

FIG. 1 is a plan view of a lower wiring portion of a reference example of a semiconductor device of the present invention.

FIG. 2 is an enlarged sectional view showing each step of a reference example of the manufacturing method of the present invention.

FIG. 3 is a plan view of a lower wiring portion of one embodiment of the semiconductor device of the present invention.

FIG. 4 is a plan view of a lower wiring portion of an example of a conventional semiconductor device.

5 is an enlarged cross-sectional view showing a main part in FIG. 4 in the order of steps.

FIG. 6 is a diagram showing an example of a pattern described in JP-A-2-22843.

FIG. 7 is a cross-sectional view of an example of a semiconductor device described in JP-A-2-22843.

FIG. 8 is a diagram showing another example of the pattern described in Japanese Patent Application Laid-Open No. H2-222843.

FIG. 9 is a diagram showing an example of a split pattern described in Japanese Patent Application Laid-Open No. 2-22843.

FIG. 10 is a diagram showing another example of the split pattern described in Japanese Patent Application Laid-Open No. H2-222843.

FIG. 11 is a cross-sectional view of a conventional semiconductor device proposed in Japanese Patent Application Laid-Open No. 2-22843.

FIG. 12 is a cross-sectional view illustrating an example of a conventional manufacturing method described in JP-A-3-136330.

FIG. 13 is a cross-sectional view illustrating an example of a conventional manufacturing method proposed in Japanese Patent Application Laid-Open No. 3-136330.

FIG. 14 is a cross-sectional view illustrating another example of a conventional manufacturing method proposed in Japanese Patent Application Laid-Open No. 3-136330.

FIG. 15 is a cross-sectional view and a plan view of an example of a lower wiring section described in Japanese Patent Publication No. 2-2138.

16A and 16B are a cross-sectional view and a plan view of an example of a lower wiring portion of a semiconductor device proposed in Japanese Patent Publication No. 2-2138.

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-61-113262 (JP, A) JP-A-61-152038 (JP, A) JP-A-2-172261 (JP, A) JP-A-4- 92428 (JP, A) JP-A-62-81734 (JP, A)

Claims (3)

(57) [Claims] 1. A semiconductor substrate, and an insulator on the semiconductor substrate.
Film, lower narrow wiring and lower wide wiring on the insulating film.
A lower wiring layer comprising:
A first interlayer insulating film, and a flattening coating on the first interlayer insulating film.
A cloth film, a second interlayer insulating film on the flattening coating film,
At least the first interlayer formed on the lower wiring region
The lower wiring through an insulating film and the second interlayer insulating film;
Connecting to an upper wiring formed on the second interlayer insulating film;
The lower layer wide wiring is composed of narrow wiring divided into a plurality of wirings, and the narrow wirings are arranged close to and separated from each other in a wiring width direction. 1 of the line width of the lower layer narrow wiring
And having two to three times the line width of the plurality of narrow wires, one to three times the line width of the lower narrow wires in the wiring length direction of the lower thick wires. A semiconductor device characterized by being connected by a connection portion having a length. 2. A semiconductor substrate, and an insulator on the semiconductor substrate.
Film, lower narrow wiring and lower wide wiring on the insulating film.
A lower wiring layer comprising:
A first interlayer insulating film, and a flattening coating on the first interlayer insulating film.
A cloth film, a second interlayer insulating film on the flattening coating film,
At least the first interlayer formed on the lower wiring region
The lower wiring through an insulating film and the second interlayer insulating film;
Connecting to an upper wiring formed on the second interlayer insulating film;
A method of manufacturing a semiconductor device including a through-hole for forming a lower-level narrow wiring on an insulating film covered and formed on a semiconductor substrate.
And a narrow wiring divided into a plurality of wirings,
The narrow wirings are arranged close to each other in the wiring width direction,
Each of the plurality of narrow wires has a line width of 1 to 3 times the line width of the lower narrow wire, and two of the plurality of narrow wires are adjacent to each other in the wiring length direction of the lower thick wire. Forming a lower wiring composed of a lower thick wiring connected by a connection portion having a length of 1 to 3 times the line width of the width wiring, and forming a first interlayer insulating film on the entire surface including the lower wiring. a step of coating formation, a step of surface planarization coating film on the first interlayer insulating film coats formed to be substantially flat, the planarized coating the wiring between the areas above of the flattened coating layer wherein the step of back etching to leave only the film portion, and a step of coating a second interlayer insulating film on the entire surface including the etch-back planarization coating film, and the first interlayer insulating film first Opening between two interlayer insulating films
Is formed on the lower wiring and the second interlayer insulating film.
Form a through hole to connect to the upper layer wiring
And a method of manufacturing a semiconductor device. Wherein said the step of applying a planarizing coating film to a thickness equal to or less than a predetermined value in the first interlayer insulating film, the second interlayer to the planarizing coating film without performing the etch-back 3. The method of manufacturing a semiconductor device according to claim 2, further comprising the step of forming an insulating film.