JPH06224196A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To make the depths of connection holes small and uniform and improve the yield of the connection hole, by providing dummy wirings under the connection holes respectively. CONSTITUTION:A semiconductor integrated circuit device, which is provided with connection holes for connecting in an electroconductive way the conductive layer over an insulation film with the one under the insulation film, has a silicon oxide film 12 formed in the upper part of an Si substrate 20, a connection hole 13 pattern-cut in the silicon oxide film 12 whereby a gate electrode 11 and a first layer wiring 14 are connected, and a connection hole 16 pattern-cut in an interlayer insulation film 15 whereby the first layer wiring 14 and a second layer wiring 17 are connected. Further, in this semiconductor integrated circuit device, connection holes 19a, 19b, 19c pattern-cut in an interlayer insulation film 18 whereby the second layer wiring 17 and a third layer wiring are connected are formed, and moreover, dummy wirings 14a, 14b provided in the interlayer insulation film 15 which are laid respectively just under the connection holes 19a, 19b are formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device in a semiconductor manufacturing technique, and more particularly to a technique for forming a contact hole in an insulating film in a semiconductor integrated circuit device having a multilayer wiring structure.

[0002]

2. Description of the Related Art Conventionally, in the process of forming a multilayer wiring structure of a semiconductor integrated circuit device, as a technique for forming a contact hole such as a contact hole or a through hole formed in an insulating film, photolithography technique or dry / wet etching Techniques and the like are known.

Further, in the process of forming a multilayer wiring structure of a semiconductor integrated circuit device, as a technique for improving the flatness of an insulating film, a SOG (spin on glass) method, a combination method of SOG and etch back, and a resist etch back method are used. The quartz sputtering method, polishing method and the like are known.

FIG. 3 is a partial sectional view showing an example of the structure of a conventional semiconductor integrated circuit device.

First, the structure of the semiconductor integrated circuit device will be described with reference to FIG. 3. A gate electrode 1 which is a diffusion layer is provided on an upper portion of a Si substrate 10, and silicon oxide which functions as a passivation film is further provided. The film 2 is formed.

Further, on the upper portion of the silicon oxide film 2,
An interlayer insulating film 5 provided with the first layer wiring 4 is formed, and an interlayer insulating film 8 is formed on the interlayer insulating film 5. Here, the interlayer insulating film 8 is provided with a second layer wiring 6, and further, connection holes 9a, 9b, 9c for connecting the second layer wiring 6 and the third layer wiring 7 are formed. .

Further, the SOG 3 is accumulated in the recess 2a of the silicon oxide film 2 located under the connection hole 9b and around the connection hole 9b in the recess 5a of the interlayer insulating film 5.

[0008]

However, as semiconductor integrated circuit devices have become finer, faster, and have multiple wiring structures,
The limitations of the prior art are becoming clear.

First, the connection holes 9a, 9b, 9 shown in FIG.
With the miniaturization of c, fine processing (photolithography, etching, etc.) has become more and more difficult. This is because the step difference shown in the silicon oxide film 2 and the interlayer insulating film 5 becomes steeper (higher aspect ratio) as the wiring structure becomes finer and multilayered. Therefore,
It is necessary to flatten the step.

Further, when the silicon oxide film 2 and the interlayer insulating film 5 are flattened, no problem will occur if the films are successively flattened, but the flattening is necessary for various reasons such as the process being complicated. Often minimal. Therefore, the depths of the connection holes 9a, 9b, 9c greatly vary due to the unevenness of the underlying interlayer insulating film 5.

That is, the variation in the depth of the connection holes 9a, 9b, 9c causes the variation in the speed of the electric signal, so that the yield and reliability of the connection holes 9a, 9b, 9c are greatly affected. Will be affected.

When SOG3 is used as the flattening method, SOG3 may accumulate in the recess 5a of the interlayer insulating film 5, which makes it difficult to form the connection hole 9b.

Further, SOG3 is provided near the side surface of the connection hole 9b.
In some cases, the interlayer insulating film 8 and the SOG3 layer are easily separated from each other, and the metal film of the connection hole 9b may be cut.

Therefore, an object of the present invention is to reduce the depth of the connection hole by providing a dummy wiring under the connection hole.
Another object of the present invention is to provide a semiconductor integrated circuit device which is made uniform and which facilitates formation of the connection hole when performing planarization using SOG.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0016]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, a dummy wiring by a lower layer wiring is provided below the connection hole formed through the insulating film.

The dummy wiring is made of a conductive material.

[0019]

According to the above-mentioned means, since the dummy wiring by the lower layer wiring is provided under the connection hole, the vicinity of the place where the connection hole is arranged can be made higher than the surroundings. It is possible to make the depth shallow and uniform.

Also, when flattening is performed using a coating film of an SOG material or the like, the SOG material is formed into a contact hole because the area where the connection hole is formed is flat or convex. It no longer accumulates thickly in the vicinity.

[0021]

1 is a partial sectional view showing an example of the structure of a semiconductor integrated circuit device according to an embodiment of the present invention.

First, the structure of the semiconductor integrated circuit device of this embodiment will be described with reference to FIG. 1. The gate electrode 11 as a diffusion layer and the silicon oxide film 12 functioning as a passivation film are formed on the Si substrate 20. And are formed.

Further, in the silicon oxide film 12, a connection hole 13 for connecting the gate electrode 11 and the first layer wiring 14 is formed by pattern cutting.

Further, a connection hole 16 for connecting the first layer wiring 14 and the second layer wiring 17 is formed by pattern cutting in the interlayer insulating film 15 on the silicon oxide film 12, and Interlayer insulating film 1 on the interlayer insulating film 15
In FIG. 8, connection holes 19a, 19b, 19c for connecting the second layer wiring 17 and a third layer wiring (not shown) are formed by pattern cutting.

Incidentally, the connection holes 13, 16, 19a, 1
On the surfaces of 9b and 19c, a metal film (not shown) for establishing conduction between the upper and lower wirings is deposited.

Dummy wirings 14a and 14b are provided in the interlayer insulating film 15 just below the connection holes 19a and 19b, respectively.

Therefore, the place where the dummy wirings 14a and 14b are provided on the surface of the interlayer insulating film 15 can be made equal to or higher than the surroundings to form a convex state. Therefore, the connection holes 19a, 19b, 1
It is possible to make the depth of 9c shallow and uniform.

Further, the interlayer insulating film 15 is flattened by SOG3.
Also in the case of using the above-mentioned method, since the portions directly below the connection holes 19a and 19b are flat or convex, the SOG3 does not remain directly below the connection holes 19a and 19b, and the above-mentioned SOG3 is formed by the etch-back method. SOG3 can be easily removed.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, in this embodiment, the case where the dummy wiring is provided immediately below the connection hole has been described. However, as shown in FIG. 2, the dummy wiring 14c provided in the interlayer insulating film 21 is connected to the connection hole. Below 19d, the same effect can be obtained even when the dummy wiring 14c is formed with a minimum space within the standard.

[0031]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.

(1). By providing the dummy wiring under the connection hole, the depth of the connection hole can be made shallow and uniform, so that the yield of the connection hole can be improved.

(2). Since the dummy wiring is provided under the connection hole, the depth of the connection hole can be made shallow and uniform, so that reliability design such as migration resistance can be facilitated.

(3). When flattening is performed using a coating film such as SOG, etchback is facilitated, so that the yield of connection holes can be improved, and reliability design such as migration resistance can be facilitated. it can.

(4). When flattening is performed using a coating film such as SOG, SOG does not remain around the connection hole, so that the processing of the connection hole can be facilitated.

(5). Since the dummy wiring is provided below the connection hole, the depth of the connection hole can be reduced, and thus the speed of the electric signal can be improved.

(6). By using a conductive material such as metal for the dummy wiring provided under the connection hole, the dummy wiring can be formed in the same step as the step of forming the first layer wiring.

[Brief description of drawings]

FIG. 1 is a partial cross-sectional view showing an example of the structure of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 2 is a partial cross-sectional view showing an example of the structure of a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 3 is a partial cross-sectional view showing an example of the structure of a conventional semiconductor integrated circuit device.

[Explanation of symbols]

 1, 11 Gate electrode 2, 12 Silicon oxide film 2a, 5a Recess 3 SOG 4, 14 First layer wiring 5, 15, 8, 18, 21 Interlayer insulating film 6,17 Second layer wiring 7 Third layer wiring 9a- 9c, 13, 16, 19a to 19d Connection hole 10, 20 Si substrate 14a to 14c Dummy wiring

Claims (2)

[Claims] 1. A semiconductor having a structure in which a conductive film is deposited on a surface of a connection hole formed by penetrating an insulating film adhered to a base portion to electrically connect conductive layers above and below the insulating film. A semiconductor integrated circuit device, wherein a dummy wiring is provided below the connection hole. 2. The semiconductor integrated circuit device according to claim 1, wherein the dummy wiring is made of a conductive material.