JP3052892B2 - Method for manufacturing semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor integrated circuit device, and more particularly to a method of manufacturing a semiconductor integrated circuit device for increasing the operation speed and improving the reliability of a wiring pattern.

[0002]

2. Description of the Related Art In semiconductor integrated circuit devices, multilayer wiring patterns are used for higher density. FIG. 5 shows a cross section of a wiring portion of such a conventional semiconductor integrated circuit device. A lower wiring 402 is formed on a semiconductor substrate 401.
Then, a first insulating film 403 and a second insulating film 404 are formed, and an upper wiring 407 is formed thereon. S
The OG (Spin On Glass) film 406 is provided for the purpose of planarizing the insulating film. By flattening the insulating film with the SOG film, the reliability of the wiring pattern can be improved.

FIG. 6 shows another conventional example of a wiring of a semiconductor integrated circuit device in which an air-filled space having the lowest dielectric constant is provided between the wirings of the wiring pattern in order to speed up the operation of the device. 2 shows a cross section of the portion (Japanese Patent Application Laid-Open No. 7-326670). A lower wiring 502 is formed on a semiconductor substrate 501. Then, a first insulating film 503 and a second insulating film 504 are formed, and an upper wiring 507 is formed thereon. In the first insulating film 503, a gap 505 is formed between lower wirings. This gap is formed simultaneously under specific conditions when depositing the first insulating film by the CVD method or the sputtering method.

[0004]

However, the above prior art has the following problems.

In the structure shown in FIG. 5, since the interlayer insulating film has a specific dielectric constant, which is larger than air, the capacitance generated between the wirings is larger than air.
Therefore, the operating speed of the device is restricted by its wiring capacity,
There is a problem that it is difficult to increase the operation speed.

Further, in the structure shown in FIG. 6, although air gaps are provided between wirings, it is difficult to flatten the interlayer insulating film. This is because it is necessary to change the thickness of the insulating film on the wiring and the thickness of the insulating film between the wirings in order to provide a gap between the wirings. In addition, if the insulating film is flattened before forming the upper wiring, there are problems such as deformation and breakage of the void, and polishing components used for the flattening process entering the void. As described above, since it is difficult to flatten the interlayer insulating film, there is a problem that the reliability of the wiring pattern formed thereon is poor.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made to solve the above-described problems, and it is an object of the present invention to reduce the capacitance between wirings and to planarize an interlayer insulating film. An object of the present invention is to provide a method for manufacturing a device.

[0008]

SUMMARY OF THE INVENTION According to the present invention, there is provided a process of forming a first insulating film on a semiconductor substrate having a wiring pattern formed thereon such that a void is formed between wirings, and wherein the void is buried. Forming a flattening film on the first insulating film so as to leave the flattening film in the gap, flattening the first insulating film on the wiring while leaving the flattening film in the gap, The present invention relates to a method for manufacturing a semiconductor integrated circuit device, comprising a step of selectively removing and a step of forming a second insulating film so that the gap remains between wirings.

[0009]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a cross section of a wiring portion of a semiconductor integrated circuit device formed by the manufacturing method of the present invention. The lower wiring 102 on the semiconductor substrate 101 is formed of a conductive material such as a metal. The first insulating film 103 is disposed on the lower wiring pattern. The second insulating film 104 is provided on the first insulating film 103. The air gap 105 is disposed between the lower wirings and between the first insulating film 103 and the second insulating film 104. The thickness of the first insulating film is made uniform by CMP or etching. Further, if necessary, the thickness of the second insulating film is also made uniform by CMP or etching.

A gap 10 containing air is provided between the lower wirings and between the first insulating film 103 and the second insulating film 104.
Since the presence of 5, the dielectric constant is 1 which is the smallest, the capacitance C between the wirings represented by the following equation becomes small. Thus, the operation speed of the semiconductor integrated circuit device can be increased.

C = ε (S / d) (ε is the dielectric constant, S is the area of the wiring, d is the thickness of the interlayer film) Further, the first insulating film 103 (the second insulating film 104 if necessary) By making the thickness uniform by CMP or etching, the reliability of the upper wiring pattern can be improved. Since the thickness of the insulating film becomes uniform, there is no step, so that there is no disconnection in the wiring. Further, since the thickness of the upper layer wiring is made uniform, the current is not locally concentrated and the wiring does not melt.

Next, the manufacturing method of the present invention will be described with reference to the drawings.

As shown in FIG. 2A, the semiconductor substrate 20
A lower wiring 202 is formed on the substrate 1 with a thickness of 5000 angstroms by a sputtering method or a CVD method.

On top of that, as shown in FIG.
As the insulating film 203, SiO _x film, SiN _x film or S
The io _x N _y film is formed by CVD or sputtering to a thickness of 100
It is formed with a thickness of 00 angstroms.

Next, as shown in FIG. 2C, a low-temperature-forming glass coating material is applied so as to fill the voids, and heated at about 400 ° C. to vitrify the low-temperature-forming glass coating material to form an SOG film. Step 206 is formed.

Subsequently, from the upper surface of the SOG film 206,
CMP or etching is performed until the first insulating film 203 reaches the first insulating film 203 and the thickness of the first insulating film on the lower wiring becomes uniform (FIG. 3D). Due to the formation of the SOG film, the first insulating film between the wirings is not etched.

Next, etching (for example, penetration into a solution of hydrogen fluoride) in which the etching rate of the SOG film 206 is faster than the etching rate of the first insulating film 203 is performed.
Only the SOG film 206 is etched to form a void 205 as shown in FIG.

After this etching step, the second insulating film 20
The thickness of the insulating film on the wiring (thickness of the first insulating film and the second insulating film) is 1000 by CVD or sputtering.
It is formed to be about 0 Å (FIG. 3
(F)).

At this time, depending on the layout pattern of the lower layer, such as the width of the lower layer wiring being wide, it is desirable to subject the second insulating layer to a flattening process such as CMP or etching, if necessary.

In the semiconductor integrated circuit device manufactured as described above, the interlayer insulating films 203 and 20
Since there is an air gap between the wires 4, the dielectric constant of the insulating film is reduced, the capacitance between the wirings can be reduced, and the operation speed of the device can be improved. Also,
By making the thickness of the interlayer insulating film uniform, the reliability of the upper wiring pattern can be improved.

Next, a case where a polyimide film is formed in place of the SOG film of the above embodiment will be described below.

As shown in FIG. 4A, a lower wiring 302 and a first insulating film 303 are formed on a semiconductor substrate 301 in the same manner as in the above embodiment.

Thereafter, a polyimide solution is applied on the substrate, and then heated at about 300 ° C. to solidify the polyimide film.
08 (FIG. 4B). Subsequently, CMP or etching is performed in the same manner as in the above embodiment to make the thickness of the first insulating film 303 on the lower wiring uniform.

Next, the polyimide film 308 on the first insulating film is removed by immersion in fuming nitric acid to form a void 305.

After the step of removing the polyimide film, a second insulating film 304 is formed on the first insulating film 303 by a CVD method or a sputtering method. As a result, as shown in FIG. 4C, a second insulating film having a uniform thickness similar to that of the above-described embodiment can be formed, and between the lower wiring and the first and second insulating films. Void 305 can be formed in

[0027]

As apparent from the above description, according to the present invention, the speed of the semiconductor integrated circuit device can be increased, and the reliability of the upper wiring pattern of the device can be improved.

The reason is that the gap between the lower wirings is formed between the first and second insulating films, thereby lowering the capacitance between the lower wirings and forming the air gap. In this case, a step of making the first interlayer insulating film uniform is provided, and the second interlayer insulating film as an upper layer is formed uniformly.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a wiring structure of a semiconductor integrated circuit device manufactured by a manufacturing method of the present invention.

FIG. 2 is an explanatory diagram of a manufacturing method of the present invention.

FIG. 3 is an explanatory view of the manufacturing method of the present invention.

FIG. 4 is an explanatory view of a manufacturing method of the present invention.

FIG. 5 is a cross-sectional view showing a wiring structure of a conventional semiconductor integrated circuit device.

FIG. 6 is a cross-sectional view showing a wiring structure of a conventional semiconductor integrated circuit device.

[Explanation of symbols]

101, 201, 301, 401, 501 Semiconductor substrate 102, 202, 302, 402, 502 Lower wiring 103, 203, 303, 403, 503 First insulating film 104, 204, 304, 404, 504 Second insulating film 105, 205, 305, 505 Air gap 206, 406 SOG film 107, 207, 407, 507 Upper layer wiring 308 Polyimide film

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int. Cl. ⁷ , DB name) H01L 21/3205 H01L 21/321 H01L 21/3213 H01L 21/768

Claims (5)

(57) [Claims] 1. A step of forming a first insulating film on a semiconductor substrate on which a wiring pattern is formed so that voids are formed between wirings, and a first insulating film such that the voids are buried. Forming a flattening film thereon, flattening the first insulating film on the wiring while leaving the flattening film in the gap, selectively removing the flattening film in the gap, wiring A method for manufacturing a semiconductor integrated circuit device, comprising a step of forming a second insulating film so as to leave the gap therebetween. 2. The method according to claim 1, further comprising the step of forming a wiring pattern on the second insulating film. 3. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the first insulating film is formed by a CVD method or a sputtering method. . 4. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the first insulating film is planarized by CMP or etching. 5. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the flattening film is formed of a material having a higher etching rate than the first insulating film.