KR940007069B1 - Planerizing method using sog film - Google Patents

Abstract

The method includes the steps of forming a conductive layer 3 on a first insulating layer 2 to be contacted with a substrate 1 through a contact hole 10, forming a second insulating layer 4 on the conductive layer to a predetermined thickness, coating a SOG in a groove formed on the second insulating layer caused by the contact hole, hardening the SOG, forming a third insulating layer 5 on the SOG layer and exposed the second insulating layer to a predetermined thickness, flowing third insulating layer at the high temperature to be planarized, and forming a metal line 7 on third insulating layer, thereby increasing the tolerance to electromigration.

Description

Insulation planarization method using SOG thin film

1A is a sectional view of a state in which an insulating layer is formed in a groove by a conventional technique.

FIG. 1B is a cross-sectional view after forming the planarization process by the high temperature flow process after FIG. 1A process.

2A to 2C are cross-sectional views of a state in which a metal wiring layer is formed after filling a groove with a SOG thin film, planarizing a third insulating layer according to the present invention.

* Explanation of symbols for main parts of the drawings

1 silicon substrate 2 first insulating layer

3: polysilicon wiring layer 4: second insulating layer

5: third insulating layer (BPSG thin film) 6: SOG thin film (Spin-on-Glass)

7: metallization layer 8: void

10: Contact Home

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of planarizing a groove portion of a submicron using an SOG thin film in a manufacturing process of a highly integrated semiconductor device. In particular, when an insulation layer is formed in a recess and a metal wiring layer is formed, The present invention relates to an insulating film planarization method using an SOG thin film that fills a groove with an SOG thin film to form a flattened insulating layer without voids, and then forms a third insulating layer flat.

In general, when the metal layer is formed on the substrate where the unevenness is generated, the BPSG thin film is deposited for flattening under the metal layer and then flattened by a flow process. However, this method has excellent characteristics of the BPSG thin film and is easy to process. When the BPSG thin film is deposited in a recess having a small size of submicro and a step ratio (groove height / groove width) of 2: l or more, there is a disadvantage in that a step coverage is poor and a cavity occurs even after the flow.

Accordingly, an object of the present invention is to provide an insulating film planarization method using an SOG thin film that can reduce the step difference ratio of the groove by forming the SOG thin film before the deposition of the BPSG thin film in order to solve the above disadvantages.

That is, the SOG thin film may be applied to a groove area having a high step ratio, and then cured through heat treatment. Then, the BPSG thin film may be deposited and flowed at a high temperature of 850 ° C. or higher to form a planarized insulating film without generation of a cavity.

SOG thin films are used for planarization of the insulating film between the metal wiring layers without being used in contact with the metal wiring layer due to poor thin film characteristics, and thus have been used only in heat treatment below 500 ° C. However, even under high temperature heat treatment using the present invention under the metal wiring layer, it is possible to obtain good thin film properties, so that the SOG thin film can be applied under the metal wiring layer subjected to high temperature heat treatment to be used together with the BPSG thin film to planarize the insulating film. .

According to the present invention, a first insulating layer is formed on a silicon substrate (or a conductive layer), a conductive layer is formed on the first insulating layer, and is connected to a lower silicon substrate through a contact groove, and an insulating layer is formed on the conductive layer. In the semiconductor manufacturing method of forming a metal wiring layer thereon, in order to prevent the formation of a cavity in the insulating layer filled in the groove by the cone step ratio of the groove, the conductive layer is formed on the first insulating layer. Forming a layer, connecting the lower silicon substrate through contact grooves, and then forming a second insulating layer on the conductive layer to a predetermined thickness; and forming an SOG thin film in the groove on the second insulating layer caused by the contact groove. Coating to fill the layer, performing a curing process of the SOG thin film, and then forming a third insulating layer to a predetermined thickness on the upper surface of the second insulating layer exposed to the SOG thin film, and forming the third insulating layer at a high temperature. And the right to the flat sound, characterized by comprising the step of forming a metal wiring on its top.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

FIG. 1A shows a contact groove 10 formed on a first insulating layer 2 formed on the silicon substrate 1, for example, an oxide film, and a polysilicon wiring layer 3 on an exposed silicon substrate 1 according to the related art. , A second insulating layer 4, for example, an oxide film is formed on the polysilicon wiring layer 3, and a BPSG thin film is deposited on the second insulating groove 4 by the third insulating layer 5. As a cross-sectional view of FIG. 3, the third insulating layer 5 is overhanged on the large groove 10.

FIG. 1B is a cross-sectional view after the process of FIG. 1A and after the high temperature flow process, and the third insulation layer 5 of the contact groove 10 is maintained even after the high temperature flow process due to poor step coverage after the deposition of the third insulation layer 5. It can be seen that the cavity 8 is formed inside.

2A to 2C are sectional views showing the step of planarizing the insulating film in the contact groove according to the present invention.

FIG. 2A shows that the contact grooves 10 are formed in the first insulating layer 2 formed on the silicon substrate 1, and the polysilicon wiring layer 3 is formed to have a predetermined thickness as a conductive layer thereon, and then the polysilicon wiring layer is formed. (3) form a second insulating layer (4) on the top and apply a SOG thin film (6) on the second insulating layer (4) to a predetermined thickness to fill the groove on the contact groove 10, the initial curing furnace For example, it is a cross-sectional view which is maintained at 90 ° C., 180 ° C., and 320 ° C. for 1 minute, and cured for 1 hour at 420 ° C., for example, by post curing.

FIG. 2B is a cross-sectional view after depositing a third insulating layer 5, for example, a BPSG thin film, on the SOG thin film 6 and the exposed second insulating layer 4 to a predetermined thickness after the process. The stepped ratio is greatly reduced by the SOG thin film 6 at the recessed portion, so that the step coverage is improved after the third insulating layer 6 is deposited.

FIG. 2C shows that after the process, the third insulating layer 5 is subjected to a high temperature flow (for example, 850 ° C. for 30 minutes of heat treatment) to be planarized, and then the metal wiring layer 7 is placed on the third insulating layer 5. As a cross-sectional view of the formed state, it can be seen that there is no cavity at all in the groove portion and the flattening is performed.

As described above, the cavity is generated in the groove during the high temperature flow process due to the overhang generated when the BPSG thin film is deposited in the groove having a high step ratio. In the present invention, the cavity is filled by filling the groove with SOG thin film and then depositing the BPSG thin film. It does not occur.

In addition, since the metal wiring side is formed on the planarized BPSG thin film, the resistance of the EM (Electromigration) of the metal wiring layer can be increased, thereby improving the reliability of the semiconductor device.

Claims (4)

A first insulating layer is formed on the silicon substrate (or conductive layer), a conductive layer is formed on the first insulating layer, and the lower silicon substrate is connected through a contact groove, and an insulating layer is formed on the conductive layer. In the semiconductor manufacturing method of forming a metal wiring layer thereon, in order to prevent the cavity (8) from occurring in the insulating layer filled in the recess by the step of the contact groove, the upper portion of the first insulating layer (2) Forming a conductive layer 3 and connecting the silicon substrate 1 to the lower silicon substrate 1 through the contact grooves 10, and then forming a predetermined thickness of the second insulating layer 4 on the conductive layer. Applying the SOG thin film 6 to the grooves on the second insulating layer so that the SOG thin film 6 can be filled, and performing a curing process of the SOG thin film, and then applying a third insulating layer 5 to the upper surface of the second insulating layer exposed to the SOG thin film. ) To a predetermined thickness, and the third insulating layer at a high temperature flow. On the flat and well, how the planarizing insulating film using the SOG films, characterized in that in an upper made of a step of forming a metal wiring layer (7). The method of claim 1, wherein the second insulating layer (4) is formed of an oxide film. The method of claim 1, wherein the SOG thin film curing process is maintained for 1 minute at 90 ℃, 180 ℃, 320 ℃ in the initial curing, and curing for 1 hour at 420 ℃ for the late curing Insulation planarization method. The method of claim 1, wherein the third insulating layer is formed of a BPSG thin film.