KR930011112B1 - Metal wiring method of semiconductor device - Google Patents
Metal wiring method of semiconductor device Download PDFInfo
- Publication number
- KR930011112B1 KR930011112B1 KR1019900019184A KR900019184A KR930011112B1 KR 930011112 B1 KR930011112 B1 KR 930011112B1 KR 1019900019184 A KR1019900019184 A KR 1019900019184A KR 900019184 A KR900019184 A KR 900019184A KR 930011112 B1 KR930011112 B1 KR 930011112B1
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- South Korea
- Prior art keywords
- metal layer
- barrier metal
- sog film
- barrier
- contact hole
- Prior art date
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 97
- 239000002184 metal Substances 0.000 title claims abstract description 97
- 238000000034 method Methods 0.000 title claims description 16
- 239000004065 semiconductor Substances 0.000 title description 3
- 230000004888 barrier function Effects 0.000 claims abstract description 44
- 238000000151 deposition Methods 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 7
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 5
- 229910052715 tantalum Inorganic materials 0.000 claims abstract description 5
- 229910052718 tin Inorganic materials 0.000 claims abstract description 5
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 5
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims abstract description 5
- 229910021342 tungsten silicide Inorganic materials 0.000 claims abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 229910008599 TiW Inorganic materials 0.000 abstract description 3
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 230000008021 deposition Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 2
- 239000004952 Polyamide Substances 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229920002647 polyamide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
제1도는 종래 기술에 의해 금속층 및 절연층을 형성하였을 때 공동이 발생된 상태를 도시한 단면도.1 is a cross-sectional view showing a state in which a cavity is generated when the metal layer and the insulating layer are formed by the prior art.
제2a도 내지 제2c도는 본 발명의 제1실시예에 의해 콘택홀 상부에 제1금속층, 제1베리어 금속층, SOG막, 제2베리어 금속층 및 제2금속층을 형성하는 단계를 나타낸 단면도.2A through 2C are cross-sectional views illustrating a step of forming a first metal layer, a first barrier metal layer, an SOG film, a second barrier metal layer, and a second metal layer on a contact hole in accordance with a first embodiment of the present invention.
제3a도 내지 제3b도는 본 발명의 제2실시예에 의해 콘택홀 상부에 제1금속층, 제1베리어 금속층, SOG막, 제2베리어 금속층 및 제2금속층을 형성하는 단계를 나타낸 단면도.3A to 3B are cross-sectional views illustrating a step of forming a first metal layer, a first barrier metal layer, an SOG film, a second barrier metal layer, and a second metal layer on a contact hole by a second embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘 기판 2 : 제1절연층1 silicon substrate 2 first insulating layer
3 : 제1금속층 4 : 제2절연층3: first metal layer 4: second insulating layer
5 : 제1베리어 금속층 6 : SOG막(Spion-On-Glass)5: first barrier metal layer 6: SOG film (Spion-On-Glass)
7 : 제2베리어 금속층 8 : 제2금속층7: second barrier metal layer 8: second metal layer
본 발명은 고접적 반도체 소자의 제조공정중 서브 마이크론의 콘택홀을 통해 하층의 실리콘 기판 또는 도전층에 콘택하는 평탄화된 금속배선 형성방법에 관한 것으로, 특히 콘택홀 측벽에 증착하는 금속배선의 스텝커버리지의 불량으로 절연층 형성시 공동이 발생되는 것을 방지하기 위해 SOG막을 도포하여 평탄화된 금속배선을 형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a planarized metal wiring contacting a lower silicon substrate or a conductive layer through a submicron contact hole during a manufacturing process of a highly integrated semiconductor device, and in particular, a step coverage of a metal wiring deposited on a sidewall of a contact hole. The present invention relates to a method for forming a planarized metal interconnection by applying a SOG film to prevent a cavity from being formed when an insulation layer is formed due to poor quality.
일반적으로 금속층 예를 들어 알루미늄을 증착할 때 스퍼터링 제조방법으로 사용하는데 이 방법은 제조단가가 적게 들고 공정이 용이하지만 단자가 있는 콘택홀 등에 증착할 때 스텝커버리지(Step Coverage)가 나쁘고 오버행(Over Hang)이 생겨서 상부에 절연막을 형성할 때에 공동(Void)이 발생되는 문제가 발생된다.Generally, it is used as a sputtering method for depositing a metal layer, for example, aluminum, which is low in manufacturing cost and easy to process, but has poor step coverage and overhang when deposited in contact holes with terminals. ), A problem arises in that voids are generated when an insulating film is formed thereon.
따라서, 본 발명은 상기의 문제를 해결하기 위해 제1금속층을 단차가 심한 콘택홀 영역에 증착한다음, SOG막막을 도포하여 평탄화 공정을 거친다음, 제2금속층을 형성하는 평탄화된 금속배선 형성방법을 제공하는데 그 목적이 있다.Accordingly, in order to solve the above problem, the present invention deposits a first metal layer in a region of high contact hole, and then applies a SOG film to perform a planarization process, and then forms a second metal layer. The purpose is to provide.
본 발명에 의하면 실리콘 기판 상부에 콘택홀이 형성된 절연층을 형성하고, 그 상부에 금속층을 형성하여 상기 콘택홀을 통하여 실리콘 기판에 접속하는 금속배선 제조방법에 있어서, 상기 콘택홀 및 절연층 상부에 제1금속층 및 제1베리어 금속층을 각각 예정된 두께로 증착 단계와, 상기 제1금속층 및 제1베리어 금속층이 증착된 상부에 SOG막을 충분히 도포하여 평탄화시키는 단계와, 상기 SOG막과 제1금속층, 제1베리어 금속층의 식각비율을 동일하게한 상태에서 상기 SOG막, 제1금속층, 제1베리어 금속층을 소정두께 에치백하는 단계와, 상기 공정후 노출된 SOG막 및 제1베리어 금속층 상부에 제2베리어 금속층 및 제2금속층을 순차적으로 증착하는 단계로 이루어지는 것을 특징으로 한다.According to the present invention, an insulating layer having a contact hole formed on a silicon substrate is formed, and a metal layer is formed thereon, and the metal wiring manufacturing method is connected to the silicon substrate through the contact hole. Depositing a first metal layer and a first barrier metal layer to a predetermined thickness, and applying and planarizing an SOG film on the upper part of the first metal layer and the first barrier metal layer, respectively, to planarize the SOG film and the first metal layer, and Etching back the SOG film, the first metal layer, and the first barrier metal layer by a predetermined thickness in the same etching rate of the one barrier metal layer, and the second barrier on the exposed SOG film and the first barrier metal layer after the process. And sequentially depositing a metal layer and a second metal layer.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제1도는 종래 기술에 의해 실리콘 기판(1) 또는 도전층 상부에 제1절연층(2)을 형성하고, 소정부분을 제거하여 콘택홀(20)을 형성한다음, 제1금속층(3)을 증착하고 그 상부에 제2절연층(4)을 형성한 상태의 단면도로서, 상기 콘택홀(20)에 형성된 제2절연층(10) 내부에 공동(10)이 형성된 것을 알 수 있다.1 illustrates a first insulating layer 2 formed on a silicon substrate 1 or a conductive layer, and removes a predetermined portion to form a contact hole 20 according to the prior art, and then forms the first metal layer 3. As a cross-sectional view of the deposition and the second insulating layer 4 formed thereon, it can be seen that the cavity 10 is formed inside the second insulating layer 10 formed in the contact hole 20.
제2a도 내지 제2c도는 본 발명의 제1실시예에 의해 평탄화된 금속배선을 형성하는 방법이다.2A to 2C illustrate a method of forming a planarized metal wiring according to a first embodiment of the present invention.
제2a도는 실리콘 기판(1) 또는 도전체 상부에 제1절연층(2)을 형성하고, 소정부분을 제거하여 콘택홀(20)을 형성한다음, 전체적으로 제1금속층(3) 및 제1베리어 금속층(5)을 순차적으로 예정된 두께로 증착한다음, 그 상부에 SOG막(6) 또는 폴리이미드(Polyimide) 또는 폴리아마이드산(Polyamide Acid)을 두껍게 도포하여 플로우(Flow)시킨다음, 초기 경화 예를 들어 90℃, 180℃, 320℃에서 각각 1분 동안 경화시키고, 후기 경화 예를 들어 420℃에서 60분 동안 경화시킨 상태의 단면도이다. 여기에서 상기 제1금속층(3)은 일반적으로 콘택홀(20) 벽면에서는 얇게 형성된다. 상기 제1금속층(3)은 예를 들어 알루미늄 또는 텅스턴 실리사이드를 증착하고, 제1베리어 금속층(5)은 Ti, Ta, TiW 또는 TiN등을 증착한다.FIG. 2A shows the first insulating layer 2 formed on the silicon substrate 1 or the conductor, and removes a predetermined portion to form the contact hole 20. Then, the first metal layer 3 and the first barrier as a whole. The metal layer 5 was sequentially deposited to a predetermined thickness, and then the SOG film 6 or polyimide or polyamide acid was thickly applied thereon to flow thereon. For example, it is a cross-sectional view of curing at 90 ° C., 180 ° C., 320 ° C. for 1 minute, and curing at a post-cure, for example, 60 minutes at 420 ° C. In this case, the first metal layer 3 is generally formed thin on the wall of the contact hole 20. The first metal layer 3 deposits aluminum or tungsten silicide, for example, and the first barrier metal layer 5 deposits Ti, Ta, TiW or TiN.
제2b도는 상기 제1금속층(3), 제1베리어 금속층(5)과 SOG막(6)의 식각선택비(Etch Selectivity)를 1 : 1 : 1로 한 상태에서 제1절연층(2) 표면 상부의 제1금속층(3), 제1베리어 금속층(5) 및 SOG막(6)을 소정두께 에치백(Etch Back)하여 평탄하게 한 상태의 단면도이다.FIG. 2B illustrates the surface of the first insulating layer 2 with the etching selectivity of the first metal layer 3, the first barrier metal layer 5, and the SOG film 6 being 1: 1: 1. The first metal layer 3, the first barrier metal layer 5, and the SOG film 6 in the upper portion are etched back to have a predetermined thickness to be flat.
제2c도는 상기 공정후 제1금속층(3)과 남아있는 SOG막(6) 상부에 제2베리어 금속층(7) 예를 들어 Ti, Ta, TiW 또는 TiN등을 예정된 얇은 두께로 형성하고, 그 상부에 제2금속층(8) 예를 들어 알루미늄층 또는 텅스텐 실리사이드를 증착한 상태의 단면도로서, 제2금속층(8) 표면은 평탄한 구조로 되어 후에 제2절연막(도시안됨)을 형성해도 공동이 발생되지 않는다.FIG. 2C shows that the second barrier metal layer 7, for example, Ti, Ta, TiW or TiN, is formed on the first metal layer 3 and the remaining SOG film 6 after the process to a predetermined thin thickness. A cross-sectional view of a state in which a second metal layer 8, for example, an aluminum layer or tungsten silicide is deposited, has a flat structure so that no cavity is formed even when a second insulating film (not shown) is formed later. Do not.
제3a도 내지 제3b도는 본 발명의 제2실시예에 의해 평탄한 금속배선 형성단계를 도시한 단면도이다.3A to 3B are cross-sectional views illustrating a step of forming a flat metal wiring according to a second embodiment of the present invention.
제3a도 내지 상기 제2a도 공정후에 SOG막(8)만 식각되도록 하되, 상기 제1베리어 금속층(5)의 최상부 표면보다 낮게 상기 SOG막(6)을 에치백한 상태의 단면도이다.3A to 2A are sectional views in which only the SOG film 8 is etched after the process, but the SOG film 6 is etched back lower than the top surface of the first barrier metal layer 5.
제3b도는 상기 노출된 제1베리어 금속층(5)과 SOG막(6) 상부에 제2베리어 금속층(7)을 얇은 두께로 형성하고 그 상부에 제2금속층(8)을 증착한 상태의 단면도이다. 제2베리어 금속층(7)은 제1베리어 금속층(5)과 동일한 물질이고 역시 제2금속층(8)도 제1금속층(3)과 동일한 물질을 사용하면 된다.FIG. 3B is a cross-sectional view of the second barrier metal layer 7 formed on the exposed first barrier metal layer 5 and the SOG film 6 in a thin thickness and the second metal layer 8 deposited thereon. . The second barrier metal layer 7 may be made of the same material as the first barrier metal layer 5, and the second metal layer 8 may also be made of the same material as the first metal layer 3.
상기한 본 발명에 의하면 단차가 심한 콘택홀에서 금속층 증착시 발생되는 오버행(Over Hang)에 의해 후공정으로 절연층 증착시 발생되는 공동을 제거할 수 있으며, 제1금속층 및 제2금속층 사이에 베리어 금속층을 첨가시켜 EM 내성을 높일 수 있으므로 반도체 소자의 신뢰성을 향상시킬 수 있다.According to the present invention described above, the cavity generated during the deposition of the insulating layer may be removed by an overhang generated during the deposition of the metal layer in the stepped contact hole, and the barrier between the first metal layer and the second metal layer may be removed. Since the EM resistance can be increased by adding a metal layer, the reliability of the semiconductor device can be improved.
Claims (8)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019900019184A KR930011112B1 (en) | 1990-11-26 | 1990-11-26 | Metal wiring method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019900019184A KR930011112B1 (en) | 1990-11-26 | 1990-11-26 | Metal wiring method of semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| KR920010864A KR920010864A (en) | 1992-06-27 |
| KR930011112B1 true KR930011112B1 (en) | 1993-11-24 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019900019184A KR930011112B1 (en) | 1990-11-26 | 1990-11-26 | Metal wiring method of semiconductor device |
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| Country | Link |
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| KR (1) | KR930011112B1 (en) |
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- 1990-11-26 KR KR1019900019184A patent/KR930011112B1/en not_active IP Right Cessation
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| KR920010864A (en) | 1992-06-27 |
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