KR100187687B1 - Metal layer forming method of semiconductor device - Google Patents
Metal layer forming method of semiconductor device Download PDFInfo
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- KR100187687B1 KR100187687B1 KR1019960011716A KR19960011716A KR100187687B1 KR 100187687 B1 KR100187687 B1 KR 100187687B1 KR 1019960011716 A KR1019960011716 A KR 1019960011716A KR 19960011716 A KR19960011716 A KR 19960011716A KR 100187687 B1 KR100187687 B1 KR 100187687B1
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- metal layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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Abstract
본 발명은 반도체 소자의 금속층 형성방법을 제공하는 것으로 저온챔버를 이용하여 콜리메이티드 방법으로 제1금속층을 증착한 후 고온챔버를 이용한 고온공정에서 온도를 낮추어 제2금속층을 증착하므로써 금속층의 층덮힘을 양호하게 할 수 있는 효과가 있다.The present invention provides a method for forming a metal layer of a semiconductor device, by depositing a first metal layer by a collimated method using a low temperature chamber and then lowering the temperature in a high temperature process using a high temperature chamber to deposit a second metal layer to cover the layer of the metal layer. There is an effect that can be made good.
Description
제1a 내지 1d도는 본 발명에 따른 반도체 소자의 금속층 형성방법을 설명하기 위한 소자의 단면도.1A to 1D are cross-sectional views of a device for explaining a method of forming a metal layer of a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 콘택홀 11 : 실리콘기판10 contact hole 11: silicon substrate
12 : 접합영역 13 : 절연막12 junction region 13 insulating film
14 : 베리어금속층 14 : 티타늄 웨팅막14 barrier metal layer 14 titanium wetting film
16 : 제1금속층 17 : 제2금속층16: first metal layer 17: second metal layer
본 발명은 반도체 소자의 금속층 형성방법에 관한 것으로, 특히 저온챔버 및 고온챔버를 이용하여 콘택홀 내에 금속층을 완전히 매립할 수 있도록 한 반도체 소자의 금속층 형성방법에 관한 것이다.The present invention relates to a method of forming a metal layer of a semiconductor device, and more particularly, to a method of forming a metal layer of a semiconductor device in which a metal layer can be completely embedded in a contact hole using a low temperature chamber and a high temperature chamber.
일반적으로 소자가 고집적화 됨에 따라 신뢰성 있는 소자의 제작을 위해 새로운 공정이 도입되고, 특히 금속콘택의 크기가 서브-하프 미크론(Sub-Half Micron) 이하로 감소함에 따라 기존의 스퍼터링(Sputtering)에 의한 증착 방법으로는 신뢰성 있는 소자의 제조를 위한 충분한 스텝 커버리지(Step Coverage)를 확보할 수 없게 되었다. 그래서 이를 개선하고자 고온재용융법(Reflow), 2단계 증착법 및 레이져(Laser)를 이용한 멜팅(Melting)법 등이 이용되고 있다. 그러나 이러한 고온공정 도입으로 인하여 베리어 금속(Barrier Metal)의 취약성에 의한 접합파괴(Junction Spiking)현상이 증대되었다.In general, as the device is highly integrated, a new process is introduced for the fabrication of a reliable device, and in particular, as the metal contact size decreases below Sub-Half Micron, deposition by conventional sputtering is performed. The method is unable to ensure sufficient step coverage for the manufacture of reliable devices. Therefore, in order to improve this, a reflow, a two-step deposition method, and a melting method using a laser are used. However, the introduction of high temperature process has increased the junction spiking phenomenon due to the vulnerability of barrier metal.
또, 2단계 증착법에서는 금속을 증착할 경우 1단계 금속층 증착시 기존의 스퍼터링 방식으로는 콘택홀 측벽에 충분한 스텝커버리지를 확보할 수 없고, 이에 따라 2단계 금속층 증착시 플로우를 원할하게 하기 위하여 높은 온도에서 금속층 증착을 하게 되는데, 이는 금속층 표면의 거칠기가 증대하고, 후속공정으로 리소그래피 공정(Lithography Process)이 어려운 문제가 있다.In addition, in the two-step deposition method, when the metal is deposited, sufficient step coverage cannot be secured on the sidewalls of the contact holes by the conventional sputtering method. In the metal layer deposition, the surface roughness of the metal layer increases, there is a problem that the lithography process (Lithography process) is difficult to follow.
따라서 본 발명은 저온챔버(Cold Chamber)를 이용하여 콜리메이티드(Collimated) 방법으로 증착한 후 고온챔버(Hot Chamber)를 이용한 고온고정에서 온도를 낮추어 증착하므로써 상기한 단점을 해소할 수 있는 반도체 소자의 금속층 형성방법을 제공하는 데 그 목적이 있다.Therefore, the present invention is a semiconductor device that can solve the above disadvantages by depositing by lowering the temperature at a high temperature fixing using a hot chamber after the deposition by a collimated method using a cold chamber (Cold Chamber) Its purpose is to provide a method for forming a metal layer.
상기한 목적을 달성하기 위한 본 발명은 소정의 제조공정을 거친 실리콘기판상에 절연막을 형성한 후 접합영역이 노출되도록 절연막을 패터닝하여 콘택홀을 형성하는 단계와, 상기 단계로부터 절연막 및 접합영역상에 베리어금속층을 형성한 후 경화처리를 하여 베리어금속층을 조밀화 하는 단계와, 상기 단계로부터 베리어금속층상에 티타늄 웨팅막을 형성하는 단계와, 상기 단계로부터 콜리메이티드 증착방법으로 티타늄 웨팅막상에 제1금속층을 증착하여 형성하는 단계와, 상기 단계로부터 제1 금속층상에 제2금속층을 증착하여 형성하는 단계로 이루어지는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a method for forming a contact hole by forming an insulating film on a silicon substrate that has been subjected to a predetermined manufacturing process and then patterning the insulating film to expose the junction region. Forming a barrier metal layer on the barrier metal layer to harden the barrier metal layer, forming a titanium wetting film on the barrier metal layer from the step, and collimating deposition method from the step. And depositing a second metal layer on the first metal layer.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제1a 내지 1d도는 반도체 소자의 금속층 형성방법을 설명하기 위한 소자의 단면도이다.1A to 1D are cross-sectional views of a device for explaining a method of forming a metal layer of a semiconductor device.
제1a도는 소정의 제조공정을 거친 실리콘기판(11)상에 절연막(13)을 형성한 후 접합영역(12)이 노출되도록 절연막(13)을 패터닝하여 콘택홀(10)을 형성한 상태의 단면도이다.1A is a cross-sectional view of a state in which a contact hole 10 is formed by forming an insulating film 13 on a silicon substrate 11 that has undergone a predetermined manufacturing process and then patterning the insulating film 13 to expose the junction region 12. to be.
제1b도는 절연막(13) 및 접합영역(12)상에 베리어금속층(14)을 형성한 후 경화처리를 하여 베리어금속층(14)을 조밀화 하고, 그 위에 티타늄 웨팅막(15)을 형성한 상태의 단면도이다. 베리어금속층(14)은 티타늄(Ti) 및 티타늄 나이트라이드(TiN)로 이루어지고, 티타늄 웨팅막(15)은 400 내지 700Å의 두께를 갖는 티타늄(Ti)막으로 후속공정에서 제1금속층(16)의 표면 이동도 및 흡착성을 좋게 하기 위하여 형성된다.FIG. 1B shows the barrier metal layer 14 formed on the insulating film 13 and the junction region 12 and then cured to densify the barrier metal layer 14, and the titanium wetting film 15 is formed thereon. It is a cross section. The barrier metal layer 14 is made of titanium (Ti) and titanium nitride (TiN), and the titanium wetting film 15 is a titanium (Ti) film having a thickness of 400 to 700 GPa, and the first metal layer 16 in a subsequent process. It is formed to improve the surface mobility and adsorptivity of the.
제1c도는 저온챔버에서 콜리메이티드 증착방법으로 티타늄 웨팅막(15)상에 제1금속층(16)을 증착시킨 상태의 단면도이다. 이때 제1금속층(16)은 알루미늄(Al)이 25 내지 200℃의 온도, 8 내지 15KW의 전력 및 1 내지 5mTorr의 압력 조건으로 1000 내지 3000Å의 두께가 되도록 형성된다.FIG. 1C is a cross-sectional view of depositing the first metal layer 16 on the titanium wetting film 15 by the collimated deposition method in a low temperature chamber. At this time, the first metal layer 16 is formed such that aluminum (Al) has a thickness of 1000 to 3000 Pa at a temperature of 25 to 200 ° C., an electric power of 8 to 15 KW, and a pressure of 1 to 5 mTorr.
제1d도는 고온챔버에서 제2금속층(17)을 제1금속층(16)상에 증착시킨 상태의 단면도이다. 이때 제2금속층(17)은 알루미늄(Al)이 450 내지 500℃의 온도, 2 내지 5KW의 전력 및 1 내지 5mTorr의 압력조건으로 형성된다.FIG. 1D is a cross-sectional view of the second metal layer 17 deposited on the first metal layer 16 in the high temperature chamber. In this case, the second metal layer 17 is formed of aluminum (Al) at a temperature of 450 to 500 ° C., power of 2 to 5 KW, and pressure of 1 to 5 mTorr.
즉, 저온챔버를 이용한 알루미늄(Al) 증착시 균일하게 증착된 콜리메이티드 알루미늄(Al)으로 인하여 작은 구동력으로도 고온 알루미늄(Al)증착시 플로우가 용이하게 일어나 종래의 저온에서 고온으로의 연속 증착에 비해 고온증착 온도를 낮출 수 있으며, 또 콘택홀(10)의 매립효과도 매우 뛰어나다.That is, due to the uniformly deposited collimated aluminum (Al) during the low temperature chamber deposition, the flow easily occurs when the high temperature aluminum (Al) is deposited even with a small driving force, so that the continuous deposition from the conventional low temperature to the high temperature is performed. Compared with this, the high temperature deposition temperature can be lowered, and the filling effect of the contact hole 10 is also excellent.
일 실시예로 고온챔버에서 제2금속층(17)인 알루미늄(Al)을 450℃에서 증착하였을 경우 0.36×0.45㎛2의 넓이를 갖는 콘택홀(10)에서도 완전히 매립되며, 종래의 스퍼터링 방식에 의한 저온에서 고온으로의 연속 공정시에는 500℃에서 증착하여도 보이드(Void)가 발생하게 된다.In an embodiment, when aluminum (Al), which is the second metal layer 17, is deposited at 450 ° C. in a high temperature chamber, the contact hole 10 having a width of 0.36 × 0.45 μm 2 is completely buried, and according to the conventional sputtering method. In the continuous process from low temperature to high temperature, voids are generated even when deposited at 500 ° C.
이와같이 콜리메이티드 알루미늄(Al)을 저온챔버에서 실시할 때 알루미늄(Al)의 층덮힘이 좋아지고, 저온챔버 및 고온챔버를 이용한 2단계 증착단계에서는 증착온도의 감소로 인하여 고온공정에서 문제되는 접합 파괴 현상을 줄일 수 있으며 표면특성의 개선으로 인하여 후속공정인 리소그래피 공정을 용이하게 실시할 수 있다.Thus, when the collimated aluminum (Al) is carried out in a low temperature chamber, the layer covering of aluminum (Al) is improved, and in the two-stage deposition step using the low temperature chamber and the high temperature chamber, a problem arises in the high temperature process due to the decrease of the deposition temperature. The fracture phenomenon can be reduced and the lithography process, which is a subsequent process, can be easily performed due to the improvement of the surface properties.
본 실시예에서는 1층의 금속배선에 적용하였으나 본 발명은 이것에 한정되는 것은 아니다. 즉, 소자의 고집적화에 따라 다층 배선공정에서 비아홀(Via Hole)의 매립을 위하여 실시하면 더욱 좋은 효과를 얻을 수 있다.In the present embodiment, but applied to the metal wiring of one layer, the present invention is not limited thereto. That is, according to the higher integration of the device, a better effect can be obtained when the via hole is buried in the multilayer wiring process.
상술한 바와같이 본 발명에 의하면 저온챔버를 이용하여 콜리메이티드 방법으로 제1금속층을 증착한 후 고온챔버를 이용한 고온공정에서 온도를 낮추어 제2 금속층을 증착하므로써 금속층의 층덮힘을 양호하게 할 수 있는 탁월한 효과가 있다.As described above, according to the present invention, the first metal layer is deposited by a collimated method using a low temperature chamber, and then the temperature is lowered in a high temperature process using a high temperature chamber to deposit a second metal layer, thereby improving the layer covering of the metal layer. That has an excellent effect.
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