KR100582372B1 - A method for forming damascene type metal wire - Google Patents

A method for forming damascene type metal wire Download PDF

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KR100582372B1
KR100582372B1 KR1019990062201A KR19990062201A KR100582372B1 KR 100582372 B1 KR100582372 B1 KR 100582372B1 KR 1019990062201 A KR1019990062201 A KR 1019990062201A KR 19990062201 A KR19990062201 A KR 19990062201A KR 100582372 B1 KR100582372 B1 KR 100582372B1
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film
forming
insulating film
metal wiring
interlayer insulating
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KR20010064081A (en
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박상수
이정석
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02131—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being halogen doped silicon oxides, e.g. FSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners

Abstract

본 발명은 반도체 기술에 관한 것으로, 특히 반도체 소자 제조 공정 중 금속 배선 기술에 관한 것이며, 더 자세히는 듀얼 대머신(dual damascene) 타입의 금속배선 형성 기술에 관한 것이다. 본 발명은 대머신 공정에 저유전율의 SiOF막을 층간절연막으로 적용하여 RC-지연을 줄일 수 있는 반도체 소자의 대머신 타입 금속배선 형성방법을 제공하는데 그 목적이 있다. 본 발명은 SiOF막을 대머신 공정에 적용함에 있어서, 금속배선 사이의 간극에 SiOF막을 두어 인접 금속배선간 정전용량을 감소시키고, 스페이서 절연물질(예컨대, 실리콘산화막)을 금속배선과 SiOF막 사이에 형성하여 SiOF막 내의 F기에 의한 금속배선의 열화를 방지한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor technology, and more particularly, to metal wiring technology in a semiconductor device manufacturing process, and more particularly, to a dual damascene type metal wiring forming technology. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a large-machine-type metal wiring of a semiconductor device which can reduce RC-delay by applying a low dielectric constant SiOF film as an interlayer insulating film in a large-machine process. In the present invention, in applying a SiOF film to a damascene process, a SiOF film is placed in a gap between metal wirings to reduce capacitance between adjacent metal wirings, and a spacer insulating material (eg, silicon oxide film) is formed between the metal wiring and the SiOF film. This prevents deterioration of metal wiring due to F groups in the SiOF film.

대머신 공정, 금속배선, SiOF막, 스페이서 절연막, RC-지연Large Machine Process, Metallization, SiOF Film, Spacer Insulator, RC-Delay

Description

대머신 타입 금속배선 형성방법{A METHOD FOR FORMING DAMASCENE TYPE METAL WIRE} A METHOD FOR FORMING DAMASCENE TYPE METAL WIRE}             

도 1은 종래기술에 따라 다층 금속배선이 형성된 반도체 소자의 단면도.1 is a cross-sectional view of a semiconductor device in which a multilayer metal wiring is formed according to the prior art.

도 2a 내지 도 2e는 본 발명의 일 실시예에 따른 듀얼 대머신 타입의 금속배선 형성 공정도.2a to 2e is a process diagram of forming a metal wire of the dual damascene type according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

20 : 하부층 21 : 하부 금속배선20: lower layer 21: lower metal wiring

22, 26 : 실리콘산화막 23 : 실리콘질화막22, 26: silicon oxide film 23: silicon nitride film

24 : SiOF막 25, 27 : 포토레지스트 패턴24: SiOF film 25, 27: photoresist pattern

28 : 알루미늄막28: aluminum film

본 발명은 반도체 기술에 관한 것으로, 특히 반도체 소자 제조 공정 중 금속 배선 기술에 관한 것이며, 더 자세히는 듀얼 대머신(dual damascene) 타입의 금속배선 형성 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor technology, and more particularly, to metal wiring technology in a semiconductor device manufacturing process, and more particularly, to a dual damascene type metal wiring forming technology.

반도체 제조시 금속배선을 형성함에 있어서, 통상적으로 알루미늄을 배선 재료로 사용하여 왔다. 알루미늄은 보통 스퍼터링(Sputtering)과 같은 물리기상증착(Physical Vapor Deposition, PVD)법을 사용하여 증착해 왔는데, 비저항이 2.7μΩcm 정도로 매우 낮은 장점이 있는 반면, 스텝 커버리지(step coverage)가 좋지 않고 일렉트로마이그레이션(electromigration) 특성 등에 의해 열화되는 문제점이 있었다.In forming metal wiring in semiconductor manufacturing, aluminum has been commonly used as a wiring material. Aluminum has been deposited using physical vapor deposition (PVD), such as sputtering, which has the advantage of very low resistivity as low as 2.7μΩcm, while poor step coverage and electromigration. There was a problem of deterioration due to (electromigration) characteristics.

반도체 소자가 고집적화와 더불어 디자인 룰(design rule)의 축소가 가속화되고 있으며, 이에 따라 콘택홀의 단차비(aspect ratio)가 크게 증가하게 되었다. 이에 기존의 PVD 방식을 이용하여 알루미늄을 증착하게 되면, 콘택홀 내에 보이드(void)가 형성되는 것을 방지할 수 없게 되었다.As semiconductor devices become more integrated, shrinking of design rules is accelerating, resulting in a significant increase in the aspect ratio of contact holes. Therefore, when aluminum is deposited using the conventional PVD method, it is impossible to prevent voids from being formed in the contact hole.

이러한 알루미늄의 열악한 스텝 커버리지를 고려하여 현재 양산 중인 반도체 메모리에는 대부분 알루미늄에 비해 스텝 커버리지가 매우 우수한 장점이 있는 화학기상증착(Chemical Vapor Deposition, CVD) 방식의 텅스텐을 플러그 물질로 사용하고, 배선은 비저항이 낮은 알루미늄으로 형성하는 기술이 적용되고 있다.Considering the poor step coverage of aluminum, the semiconductor memory currently produced in mass production uses tungsten, which is a chemical vapor deposition (CVD) method, which has a very good step coverage compared to aluminum, as a plug material. The technique of forming with this low aluminum is applied.

그러나, 디자인 룰(design rule)이 0.13㎛ 이하인 차세대 초고집적 반도체 소자에서는 금속배선의 피치(pitch)가 매우 작기 때문에 통상의 텅스텐 플러그 금속배선 공정을 적용할 경우에는 고단차비를 가지는 금속배선의 형성시 금속배선의 CD(critical dimension) 균일도(uniformity), 라인 식각 프로파일(line etch profile) 및 포토레지스트의 식각 선택비 등에서 만족할만한 결과를 얻기 힘들다. 이를 개선하기 위해서는 하드 마스크(hard mask) 등을 사용하여야 하나, 이 경우 제조비용의 증가와 소자 개발 일정의 지연이라는 문제점이 도출된다.However, in the next generation ultra-high density semiconductor device having a design rule of 0.13 µm or less, the pitch of the metal wiring is very small. It is difficult to obtain satisfactory results in the CD (critical dimension) uniformity of the metallization, the line etch profile and the etching selectivity of the photoresist. In order to improve this, a hard mask or the like should be used, but in this case, problems such as an increase in manufacturing cost and a delay in device development schedule are derived.

이러한 문제점을 해결하기 위한 기술로 제안된 것이 대머신(damascene) 공정이다. 디자인 룰(design rule)이 0.13㎛ 이하인 차세대 초고집적 반도체 소자에서는 통상 3층 이상의 배선 구조를 가지게 되며, 이러한 다층 배선 구조를 형성함에 있어서 기존의 금속배선 공정과 함께 대머신 공정을 적용하고 있다. The damascene process is proposed as a technique to solve this problem. Next-generation ultra-high density semiconductor devices having a design rule of 0.13 μm or less usually have a wiring structure of three or more layers. In forming such a multilayer wiring structure, a conventional machine wiring process is applied together with a conventional metal wiring process.

그러나, 이와 같이 대머신 공정을 적용하는 경우에도 문제점은 있다. 즉, 금속배선간의 피치가 작아짐에 따른 RC-지연의 증가가 여전히 해결되지 않고 있다.However, there is a problem also in applying the damascene process in this way. In other words, the increase in RC-delay as the pitch between the metal wires becomes smaller is still not solved.

최근, 이러한 금속배선의 RC-지연을 줄이기 위한 하나의 방법으로 저유전체인 SiOF막을 사용하는 기술이 제안되었다.Recently, a technique using a low dielectric SiOF film has been proposed as one method for reducing the RC-delay of such metal wiring.

그런데 SiOF막은 박막 내에 포함된 F기가 후속 공정시 금속배선(알루미늄)과 반응하여 소자의 열화를 초래하는 문제점이 있기 때문에 첨부된 도면 도 1에 도시된 바와 같이 상하부 금속배선 간의 층간절연막으로만 적용되어 인접 금속배선간의 정전용량을 줄이는데 도움이 되지 못하고 있는 실정이며, 특히 대머신 공정에는 적용되지 못하고 있다. 도면 부호 '10'은 하부층, '11', '15'는 금속배선(Al), '12', '14'는 실리콘산화막(SiO2)을 '13'은 SiOF막을 각각 나타낸 것이다.However, since the SiOF film has a problem in that the F group contained in the thin film reacts with the metal wiring (aluminum) in a subsequent process to cause deterioration of the device, it is applied only as an interlayer insulating film between the upper and lower metal wirings as shown in FIG. It does not help to reduce the capacitance between adjacent metal lines, and in particular, it is not applied to the machining process. Reference numeral '10' denotes a lower layer, '11', '15' denotes a metal wiring (Al), '12' and '14' denotes a silicon oxide film (SiO 2 ), and '13' denotes an SiOF film.

본 발명은 대머신 공정에 저유전율의 SiOF막을 층간절연막으로 적용하여 RC- 지연을 줄일 수 있는 반도체 소자의 대머신 타입 금속배선 형성방법을 제공하는데 그 목적이 있다.
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a large-machine-type metallization of a semiconductor device which can reduce RC- delay by applying a low dielectric constant SiOF film as an interlayer insulating film in a large-machine process.

상기의 기술적 과제를 해결하기 위한 본 발명의 특징적인 반도체 소자의 대머신 타입 금속배선 형성방법은, 소정의 전도층이 형성된 하부층 상에 층간절연막을 형성하는 제1 단계; 상기 층간절연막 상에 SiOF막을 형성하는 제2 단계; 배선용 트렌치 영역의 상기 SiOF막을 선택 식각하는 제3 단계; 상기 제3 단계를 마친 전체 구조 표면을 따라 불소(F)기의 확산을 방지하기 위한 스페이서 절연막을 형성하는 제4 단계; 콘택홀 형성 영역의 상기 스페이서 절연막 및 상기 층간절연막을 선택 식각하는 제5 단계; 및 상기 콘택홀 및 상기 배선용 트렌치 영역에 배선금속을 매립하는 제6 단계를 포함하여 이루어진다.In order to solve the above technical problem, a method of forming a metal-machined metal wiring of a semiconductor device according to the present invention includes: a first step of forming an interlayer insulating film on a lower layer on which a predetermined conductive layer is formed; Forming a SiOF film on the interlayer insulating film; A third step of selectively etching the SiOF film in the wiring trench region; A fourth step of forming a spacer insulating film for preventing diffusion of fluorine (F) groups along the entire structure surface after the third step; A fifth step of selectively etching the spacer insulating film and the interlayer insulating film in the contact hole forming region; And a sixth step of filling a wiring metal in the contact hole and the wiring trench region.

즉, 본 발명은 SiOF막을 대머신 공정에 적용함에 있어서, 금속배선 사이의 간극에 SiOF막을 두어 인접 금속배선간 정전용량을 감소시키고, 스페이서 절연물질(예컨대, 실리콘산화막)을 금속배선과 SiOF막 사이에 형성하여 SiOF막 내의 F기에 의한 금속배선의 열화를 방지한다.That is, in applying the SiOF film to the damascene process, the present invention places the SiOF film in the gap between the metal wirings to reduce the capacitance between adjacent metal wirings, and a spacer insulating material (eg, silicon oxide film) is formed between the metal wiring and the SiOF film. It is formed in the film to prevent deterioration of the metal wiring due to the F group in the SiOF film.

이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

첨부된 도면 도 2a 내지 도 2e는 본 발명의 일 실시예에 따른 듀얼 대머신 타입의 금속배선 형성 공정을 도시한 것으로, 이하 이를 참조하여 설명한다.2A to 2E illustrate a dual damascene type metal wiring forming process according to an embodiment of the present invention, which will be described below with reference to the drawings.

본 실시예에 따른 듀얼 대머신 타입의 금속배선 형성 공정은, 우선 도 2a에 도시된 바와 같이 소정의 하부층(20) 상에 하부 금속배선(21)을 형성하고, 전체 구조 상부에 층간절연막인 실리콘산화막(22), 식각 정지막인 실리콘질화막(23) 및 SiOF막(24)을 차례로 증착한다.In the dual damascene type metal wiring forming process according to the present embodiment, first, as shown in FIG. 2A, a lower metal wiring 21 is formed on a predetermined lower layer 20, and silicon, which is an interlayer insulating film, is formed on the entire structure. The oxide film 22, the silicon nitride film 23 as an etch stop film, and the SiOF film 24 are sequentially deposited.

다음으로, 도 2b에 도시된 바와 같이 금속배선 마스크 공정을 통해 SiOF막(24) 상에 포토레지스트 패턴(25)을 형성하고, 이를 식각 마스크로 하여 SiOF막(24)을 선택 식각한다. 이때, 실리콘질화막(23)이 식각 정지를 유발한다.Next, as shown in FIG. 2B, the photoresist pattern 25 is formed on the SiOF film 24 through the metallization mask process, and the SiOF film 24 is selectively etched using this as an etching mask. At this time, the silicon nitride film 23 causes the etch stop.

계속하여, 도 2c에 도시된 바와 같이 포토레지스트 패턴(25)을 제거하고, 전체 구조 표면을 따라 실리콘산화막(26)을 증착한다. 실리콘산화막(26)은 SiOF막(24)과 알루미늄(금속배선)의 접촉을 방지하기 위한 스페이서(spacer) 역할을 위해 증착한 것이므로, 그 두께가 너무 얇거나 두껍지 않아야 한다.Subsequently, as shown in FIG. 2C, the photoresist pattern 25 is removed, and the silicon oxide film 26 is deposited along the entire structure surface. Since the silicon oxide film 26 is deposited to serve as a spacer for preventing the contact between the SiOF film 24 and aluminum (metal wiring), the thickness of the silicon oxide film 26 should not be too thin or too thick.

이어서, 도 2d에 도시된 바와 같이 전체 구조 상부에 포토레지스트를 도포하고, 콘택홀 마스크를 사용한 노광 공정과 현상 공정을 거쳐 포토레지스트 패턴(27)을 형성한다.Subsequently, as shown in FIG. 2D, a photoresist is applied over the entire structure, and a photoresist pattern 27 is formed through an exposure process and a development process using a contact hole mask.

끝으로, 도 2e에 도시된 바와 같이 포토레지스트 패턴(27)을 제거하고, 콘택 및 금속배선용 알루미늄막(28)을 증착한 다음, 에치백 또는 화학적기계적평탄화(CMP) 공정을 통해 알루미늄막(28)을 리세스 시켜 상부 금속배선을 형성한다.Finally, as shown in FIG. 2E, the photoresist pattern 27 is removed, the aluminum film 28 for contact and metallization is deposited, and the aluminum film 28 is subjected to an etch back or chemical mechanical planarization (CMP) process. ) To form upper metal wiring.

상기와 같은 공정을 진행하는 경우, SiOF막(24)이 인접 금속배선 간의 정전용량을 낮춰주게 되고, 스페이서 실리콘산화막(26)이 SiOF막(24)과 알루미늄막(28)의 접촉을 방지하여 F기에 의한 금속배선의 열화를 방지할 수 있다.In the process as described above, the SiOF film 24 lowers the capacitance between adjacent metal wirings, and the spacer silicon oxide film 26 prevents the contact between the SiOF film 24 and the aluminum film 28 so as to prevent F. Deterioration of the metal wiring by the group can be prevented.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

예컨대, 전술한 실시예에서는 배선금속으로 알루미늄을 사용하는 경우를 일례로 들어 설명하였으나, F기의 침투시 대부분의 금속이 열화될 가능성이 있으므로 대부분의 금속이 적용 가능하다.For example, in the above-described embodiment, the case in which aluminum is used as the wiring metal has been described as an example. However, since most metals may deteriorate when the F group penetrates, most metals are applicable.

또한, 전술한 실시예에서는 층간절연막으로 실리콘산화막을 사용하고 식각 정지막으로 실리콘질화막을 사용하는 경우를 일례로 들어 설명하였으나, 본 발명은 이에 한정되지 않고 기타 다른 절연막의 적용이 가능하다.In addition, in the above-described embodiment, a case in which a silicon oxide film is used as an interlayer insulating film and a silicon nitride film is used as an etch stop film is described as an example. However, the present invention is not limited thereto, and other insulating films may be applied.

또한, 전술한 실시예에서는 스페이서 절연막으로 실리콘산화막을 사용하는 경우를 일례로 들어 설명하였으나, 본 발명은 이에 한정되지 않고 기타 다른 절연막의 적용이 가능하다.In addition, in the above-described embodiment, the case where the silicon oxide film is used as the spacer insulating film has been described as an example, but the present invention is not limited thereto, and other insulating films may be applied.

전술한 본 발명은 F기에 의한 금속배선의 열화를 방지하면서 인접 금속배선 간의 정전용량을 크게 낮출 수 있는 효과가 있으며, 이로 인하여 소자의 RC-지연을 줄이는 효과가 있다. 또한, 본 발명은 SiOF막을 대머신 공정에 적용할 수 있어 차세대 반도체 메모리 소자의 개발 기간을 단축할 수 있는 효과가 있다.

The present invention described above has the effect of significantly lowering the capacitance between adjacent metal wires while preventing deterioration of the metal wires by the F group, thereby reducing the RC-delay of the device. In addition, the present invention can apply the SiOF film to the machining process, there is an effect that can shorten the development period of the next-generation semiconductor memory device.

Claims (5)

삭제delete 삭제delete 소정의 전도층이 형성된 하부층 상에 층간절연막을 형성하는 제1 단계;A first step of forming an interlayer insulating film on a lower layer on which a predetermined conductive layer is formed; 상기 층간절연막 상에 SiOF막을 형성하는 제2 단계;Forming a SiOF film on the interlayer insulating film; 배선용 트렌치 영역의 상기 SiOF막을 선택 식각하는 제3 단계;A third step of selectively etching the SiOF film in the wiring trench region; 상기 제3 단계를 마친 전체 구조 표면을 따라 불소(F)기의 확산을 방지하기 위한 스페이서 실리콘 산화막을 형성하는 제4 단계;A fourth step of forming a spacer silicon oxide film for preventing diffusion of fluorine (F) groups along the entire structure surface of the third step; 콘택홀 형성 영역의 상기 스페이서 절연막 및 상기 층간절연막을 선택 식각하는 제5 단계; 및A fifth step of selectively etching the spacer insulating film and the interlayer insulating film in the contact hole forming region; And 상기 콘택홀 및 상기 배선용 트렌치 영역에 배선금속을 매립하는 제6 단계를 포함하며, 상기 층간절연막이 그 최상부에 식각 정지 절연막을 포함하는 것을 특징으로 하는 반도체 소자의 대머신 타입 금속배선 형성방법.And embedding a wiring metal in the contact hole and the wiring trench region, wherein the interlayer insulating film includes an etch stop insulating film at an uppermost portion thereof. 제3항에 있어서,The method of claim 3, 상기 층간절연막이,The interlayer insulating film, 차례로 적층된 실리콘산화막과 실리콘질화막을 포함하는 것을 특징으로 하는 반도체 소자의 대머신 타입 금속배선 형성방법.A method of forming a large-machine-type metallization of a semiconductor device, comprising a silicon oxide film and a silicon nitride film stacked in sequence. 제4항에 있어서,The method of claim 4, wherein 상기 배선금속이 알루미늄으로 이루어진 것을 특징으로 하는 반도체 소자의 대머신 타입 금속배선 형성방법.Forming a large machine-type metal wiring of the semiconductor device, characterized in that the wiring metal is made of aluminum.
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KR0138295B1 (en) * 1994-11-30 1998-06-01 김광호 Fabrication of an electronic component using chemical mechanical polishing

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