KR100471404B1 - Method for forming metal wiring of semiconductor device using chemical mechanical polishing process - Google Patents
Method for forming metal wiring of semiconductor device using chemical mechanical polishing process Download PDFInfo
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- KR100471404B1 KR100471404B1 KR10-1998-0045311A KR19980045311A KR100471404B1 KR 100471404 B1 KR100471404 B1 KR 100471404B1 KR 19980045311 A KR19980045311 A KR 19980045311A KR 100471404 B1 KR100471404 B1 KR 100471404B1
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- film
- interlayer insulating
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- diffusion barrier
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 40
- 239000002184 metal Substances 0.000 title claims abstract description 40
- 238000000034 method Methods 0.000 title claims abstract description 33
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 239000000126 substance Substances 0.000 title claims abstract description 8
- 238000007517 polishing process Methods 0.000 title claims abstract description 7
- 239000011229 interlayer Substances 0.000 claims abstract description 39
- 230000004888 barrier function Effects 0.000 claims abstract description 25
- 238000009792 diffusion process Methods 0.000 claims abstract description 25
- 238000005530 etching Methods 0.000 claims abstract description 12
- 229910052802 copper Inorganic materials 0.000 claims description 26
- 239000010410 layer Substances 0.000 claims description 25
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 238000005240 physical vapour deposition Methods 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
- 150000004767 nitrides Chemical class 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 238000007733 ion plating Methods 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 26
- 239000010949 copper Substances 0.000 description 25
- 229910052782 aluminium Inorganic materials 0.000 description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 9
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 229910000838 Al alloy Inorganic materials 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000005012 migration Effects 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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Abstract
본 발명은 화학적 기계적 연마 공정을 이용한 반도체 소자의 금속배선 형성 방법에 관한 것으로, 층간절연막을 선택적으로 식각하여 금속배선 형성 위치를 정의하고 제1 확산장벽막, 금속막 및 제2 확산장벽막을 형성한 후 화학적 기계적 연마 공정을 실시하여 금속배선을 형성하는데 그 특징이 있으며, 상기 층간절연막을 식각하는 과정에서 층간절연막에 언더컷(under cut) 또는 경사면을 형성하는데 또 다른 특징이 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in a semiconductor device using a chemical mechanical polishing process, wherein the interlayer insulating film is selectively etched to define a position for forming metal wirings and to form a first diffusion barrier film, a metal film, and a second diffusion barrier film. After the chemical mechanical polishing process is carried out to form a metal wiring, there is another feature to form an under cut or inclined surface in the interlayer insulating film in the process of etching the interlayer insulating film.
Description
본 발명은 반도체 소자 제조 방법에 관한 것으로, 특히 반도체 소자의 금속배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming metal wiring of a semiconductor device.
차세대 반도체 소자의 금속 배선 재료로서 각광을 받기 시작한 구리 금속은 내산화성이 취약하고, 산화막질 또는 Si 내로 구리 원자가 침투하여 전기적 특성이 악화되는 단점이 있다. 따라서, 이와 같은 단점을 해결하기 위하여 구리막을 확산장벽막으로 감싸주어 구리 금속배선을 형성한다.As a metal wiring material of the next-generation semiconductor device, copper metal, which has been spotlighted, has a weak oxidation resistance and has a disadvantage in that electrical characteristics are deteriorated due to penetration of copper atoms into oxide film or Si. Therefore, in order to solve this disadvantage, the copper film is wrapped with the diffusion barrier film to form a copper metal wiring.
첨부된 도면 도1은 종래 기술에 따른 구리 금속배선 형성 공정 단면도로서, 소정의 하부층이 형성된 반도체 기판(10) 상에 제1 확산장벽막(11)을 형성하고, 구리막(12)을 증착한 후 구리막(12)을 선택적으로 식각하여 구리 금속배선을 형성하고, 제2 확산장벽막(13)을 증착하고 식각한 상태를 보이고 있다.1 is a cross-sectional view illustrating a process of forming a copper metal wiring according to the prior art, in which a first diffusion barrier film 11 is formed on a semiconductor substrate 10 on which a predetermined lower layer is formed, and a copper film 12 is deposited. After that, the copper film 12 is selectively etched to form a copper metal wiring, and the second diffusion barrier film 13 is deposited and etched.
전술한 바와 같은 종래의 금속 배선 형성 방법은 다수 번의 식각 공정이 수반되어야 하기 때문에 제조 공정이 복잡한 단점이 있다.The conventional metal wire forming method as described above has a disadvantage in that the manufacturing process is complicated because a plurality of etching processes must be involved.
상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은 다수 번의 식각 과정을 수반하지 않고 비교적 간단한 공정 이루어질 수 있는, 화학적 기계적 연마 공정을 이용한 반도체 소자의 금속배선 형성 방법을 제공하는데 그 목적이 있다. The present invention devised to solve the above problems is to provide a method for forming a metal wiring of a semiconductor device using a chemical mechanical polishing process, which can be made in a relatively simple process without involving a plurality of etching processes.
상기와 같은 목적을 달성하기 위한 본 발명은 반도체 기판 상의 층간절연막 상에 금속배선 형성 영역을 정의하는 감광막 패턴을 형성하는 제1 단계; 상기 감광막 패턴을 식각마스크로 상기 층간절연막을 식각하여 비아(via)를 형성하는 제2 단계; 상기 비아 저면, 비아 측벽 및 상기 층간절연막 상에 제1 확산장벽막을 형성하는 제3 단계; 금속막을 형성하여 상기 비아 저면의 상기 제1 확산장벽막 상에 금속막 패턴을 형성하는 제4 단계; 상기 비아 내에 제2 확산장벽막을 형성하는 제5 단계; 및 상기 층간절연막이 노출될 때까지 화학적 기계적 연마 공정을 실시하는 제6 단계를 포함하는 반도체 소자의 금속배선 형성 방법을 제공한다.The present invention for achieving the above object is a first step of forming a photosensitive film pattern defining a metal wiring formation region on the interlayer insulating film on a semiconductor substrate; A second step of forming a via by etching the interlayer insulating layer using the photoresist pattern as an etching mask; Forming a first diffusion barrier layer on the bottom of the via, the sidewalls of the via, and the interlayer dielectric layer; Forming a metal film to form a metal film pattern on the first diffusion barrier film on the bottom of the via; A fifth step of forming a second diffusion barrier film in the via; And a sixth step of performing a chemical mechanical polishing process until the interlayer insulating film is exposed.
본 발명은 층간절연막을 선택적으로 식각하여 금속배선 형성 위치를 정의하고 제1 확산장벽막, 금속막 및 제2 확산장벽막을 형성한 후 화학적 기계적 연마 공정을 실시하여 금속배선을 형성하는데 그 특징이 있으며, 상기 층간절연막을 식각하는 과정에서 층간절연막에 언더컷(under cut) 또는 경사면을 형성하는데 또 다른 특징이 있다.The present invention is characterized by forming metal wiring by selectively etching the interlayer insulating film to define the metal wiring formation position, forming the first diffusion barrier film, the metal film and the second diffusion barrier film, and then performing a chemical mechanical polishing process. In the process of etching the interlayer insulating layer, an undercut or an inclined surface is formed in the interlayer insulating layer.
도2a 내지 도2c를 참조하여 본 발명의 일실시예에 따른 반도체 소자의 금속배선 형성 방법을 설명한다.2A to 2C, a method of forming metal wirings in a semiconductor device according to an embodiment of the present invention will be described.
먼저, 도2a에 도시한 바와 같이 알루미늄 배선(21) 형성이 완료된 반도체 기판(20) 상에 층간절연막(22)을 형성하고, 층간절연막(22) 상에 구리 금속배선 형성 영역을 정의하는 감광막 패턴(23)을 형성한 다음, 층간절연막(22)을 선택적으로 식각하여 알루미늄 배선(21)을 노출시키는 비아(via)(24)를 형성한다. 이때, SF6를 이용한 식각을 실시하여 비아 측벽이 경사지도록 한다.First, as shown in FIG. 2A, an interlayer insulating film 22 is formed on a semiconductor substrate 20 on which aluminum wiring 21 is formed, and a photosensitive film pattern defining a copper metal wiring forming region on the interlayer insulating film 22. Next, the interlayer insulating layer 22 is selectively etched to form vias 24 exposing the aluminum interconnects 21. At this time, the sidewalls of the via are inclined by etching using SF 6 .
다음으로, 도2b에 도시한 바와 같이 감광막 패턴(23)을 제거하고 알루미늄 배선(21), 비아(24) 측벽 및 층간절연막(22) 상에 제1 확산장벽막(25)을 형성한 다음, 콜리메이티드(collimated) 물리 기상증착법(physical vapor deposition), 이온 플레이팅(ion plating) 또는 스퍼터링(sputtering) 방법 등의 물리기상증착법으로 구리막(26)을 증착한다. 이때, 구리막(26) 증착시 구리막(26)이 비아(24) 입구 부분에서 끊겨지면서 자연스럽게 비아(24) 내에 구리막(26) 패턴이 형성된다.Next, as shown in FIG. 2B, the photoresist layer pattern 23 is removed, and the first diffusion barrier layer 25 is formed on the aluminum wiring 21, the sidewalls of the vias 24, and the interlayer insulating layer 22. The copper film 26 is deposited by physical vapor deposition such as collimated physical vapor deposition, ion plating, or sputtering. At this time, when the copper film 26 is deposited, the copper film 26 is cut off at the inlet portion of the via 24 so that a copper film 26 pattern is naturally formed in the via 24.
다음으로, 도2c에 도시한 바와 같이 제2 확산장벽막(27)을 형성하여 비아(24)를 매립하고, 상기 층간절연막(22)이 노출될 때까지 화학적 기계적 연마(chemical & mechanical polishing, 이하 CMP라 함) 공정을 실시하여 평탄화를 이룸으로써 구리 금속배선 형성 공정을 완료한다.Next, as shown in FIG. 2C, a second diffusion barrier layer 27 is formed to fill the vias 24, and chemical and mechanical polishing (hereinafter, referred to as “interlayer insulating layer 22”) is exposed. CMP) process to achieve planarization to complete the copper metal wiring forming process.
전술한 본 발명의 일실시예는 금속배선 형성 과정 중 구리 금속배선 형성을 예로서 설명한 것이며, 구리막(26)을 대신하여 Ag, Pt, Au 또는 Co 등을 형성할 수도 있다. 또한 상기 알루미늄 배선(21)은 알루미늄 합금막으로 형성될 수도 있다. 상기 층간절연막(22)은 플라즈마 화학기상증착(plasma chemical vapor deposition) 방법으로 형성된 질화막 또는 산화막이거나, TEOS(tetraethyl ortho silicate glass), BPSG(boron phosphorous silicate glass) 또는 열산화막(thermal oxide) 중 어느 하나이며, 상기 제1 확산장벽막(25) 및 상기 제2 확산장벽막(27)은 화학기상증착법으로 형성된 TiN, CrN, TiW 또는 WN이다.One embodiment of the present invention described above is described as an example of forming a copper metal wiring during the metal wiring forming process, it may be formed Ag, Pt, Au or Co, etc. in place of the copper film 26. In addition, the aluminum wiring 21 may be formed of an aluminum alloy film. The interlayer insulating layer 22 is a nitride film or an oxide film formed by plasma chemical vapor deposition, or any one of tetraethyl ortho silicate glass (TEOS), boron phosphorous silicate glass (BPSG), or thermal oxide (thermal oxide) The first diffusion barrier film 25 and the second diffusion barrier film 27 are TiN, CrN, TiW, or WN formed by chemical vapor deposition.
이하, 본 발명의 다른 실시예를 도3a 내지 도3e를 참조하여 설명한다.Hereinafter, another embodiment of the present invention will be described with reference to FIGS. 3A to 3E.
먼저, 도3a에 도시한 바와 같이 알루미늄 배선(31) 형성이 완료된 반도체 기판(30) 상에 제1 층간절연막(32) 및 제2 층간절연막(33)을 형성한다. 이때, 제1 층간절연막(32)은 플라즈마 화학기상증착 방법으로 형성된 산화막, TEOS, BPSG 또는 열산화막 등과 같은 산화막계로 형성하고, 제2 층간절연막(33)은 플라즈마 화학기상증착 방법으로 형성된 질화막 또는 Si3N4 등과 같은 질화막계로 형성한다.First, as shown in FIG. 3A, a first interlayer insulating film 32 and a second interlayer insulating film 33 are formed on the semiconductor substrate 30 on which the aluminum wiring 31 is formed. In this case, the first interlayer insulating film 32 is formed of an oxide film such as an oxide film formed by a plasma chemical vapor deposition method, TEOS, BPSG, or a thermal oxide film, and the second interlayer insulating film 33 is formed of a nitride film or Si formed by a plasma chemical vapor deposition method. It is formed of a nitride film system such as 3N 4 .
다음으로, 도3b에 도시한 바와 같이 제2 층간절연막(33) 상에 구리 금속배선 형성 영역을 정의하는 감광막 패턴(34)을 형성한 다음, 제2 층간절연막(33) 및 제1 층간절연막(32)을 선택적으로 식각하여 알루미늄 배선(31)을 노출시키는 비아(via)(25)를 형성한다. 이때, 제1 층간절연막(32)과 제2 층간절연막(33)의 식각선택비를 이용하여 제1 층간절연막(32)에 언더컷(under cut)이 형성되도록 하기 위하여 불소계 플라즈마를 이용하여 식각을 실시한다. 본 발명의 실시예에서는 SF6를 이용하여 플라즈마 식각한다.Next, as shown in FIG. 3B, a photosensitive film pattern 34 defining a copper metal wiring formation region is formed on the second interlayer insulating film 33, and then the second interlayer insulating film 33 and the first interlayer insulating film ( 32 is selectively etched to form vias 25 exposing the aluminum interconnect 31. In this case, etching is performed using fluorine-based plasma so that an under cut is formed in the first interlayer insulating layer 32 by using an etching selectivity between the first interlayer insulating layer 32 and the second interlayer insulating layer 33. do. In an embodiment of the present invention, plasma etching is performed using SF 6 .
다음으로, 도3c에 도시한 바와 같이 감광막 패턴(34)을 제거하고 알루미늄 배선(31), 비아(35) 측벽 및 제2 층간절연막(33) 상에 제1 확산장벽막(36)을 형성한 다음, 콜리메이티드(collimated) 물리 기상증착법(physical vapor deposition), 이온 플레이팅(ion plating) 또는 스퍼터링(sputtering) 방법 등의 물리기상증착법으로 구리막(37)을 증착한다. 이때, 구리막(37) 증착시 구리막(37)이 비아(35) 입구 부분에서 끊겨지면서 자연스럽게 비아(35) 내에 구리막(37) 패턴이 형성된다.Next, as shown in FIG. 3C, the photoresist layer pattern 34 is removed, and the first diffusion barrier layer 36 is formed on the aluminum wiring 31, the sidewalls of the vias 35, and the second interlayer insulating layer 33. Next, the copper film 37 is deposited by physical vapor deposition such as collimated physical vapor deposition, ion plating, or sputtering. At this time, when the copper film 37 is deposited, the copper film 37 is cut off at the inlet portion of the via 35 so that the copper film 37 pattern is naturally formed in the via 35.
다음으로, 도3d에 도시한 바와 같이 제2 확산장벽막(38)을 형성하여 비아(35)를 매립한다.Next, as shown in FIG. 3D, a second diffusion barrier film 38 is formed to fill the via 35.
다음으로, 도3e에 도시한 바와 같이 상기 제2 층간연막(33)이 노출될 때까지 CMP 공정을 실시하여 평탄화를 이룸으로써 구리 금속배선 형성 공정을 완료한다.Next, as shown in FIG. 3E, the CMP process is performed until the second interlayer film 33 is exposed to planarize to complete the copper metal wiring forming process.
전술한 본 발명의 실시예는 금속배선 형성 과정 중 구리 금속배선 형성을 예로서 설명한 것이며, 구리막(37)을 대신하여 Ag, Pt, Au 또는 Co 등으로 형성할 수도 있다. 또한, 상기 알루미늄 배선(31)은 알루미늄 합금막으로 형성될 수도 있으며, 상기 제1 확산장벽막(36) 및 상기 제2 확산장벽막(38)은 화학기상증착법으로 형성된 TiN, CrN, TiW 또는 WN이다.In the above-described embodiment of the present invention, copper metal wiring formation is described as an example of the metal wiring formation process, and may be formed of Ag, Pt, Au, or Co in place of the copper film 37. In addition, the aluminum wiring 31 may be formed of an aluminum alloy film, and the first diffusion barrier film 36 and the second diffusion barrier film 38 may be formed by chemical vapor deposition (TiN, CrN, TiW, or WN). to be.
상기와 같이 이루어지는 본 발명은 비교적 간단한 공정을 금속배선을 형성할 수 있어 EM(electron migration), SM(stress migration), 소자의 RC 지연 등을 감소시키는 등 전기적 특성을 향상시킬 수 있으며 소자의 신뢰성을 향상시킬 수 있다.According to the present invention, a metal wire can be formed in a relatively simple process, thereby improving electrical characteristics such as reducing electron migration (SM), stress migration (SM), RC delay of the device, and the like. Can be improved.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.
도1은 종래 기술에 따른 구리 금속배선 형성 공정 단면도,1 is a cross-sectional view of a copper metal wiring forming process according to the prior art,
도2a 내지 도2c는 본 발명의 일실시예에 따른 반도체 소자의 금속 배선 형성 공정 단면도,2A through 2C are cross-sectional views of a metal wiring forming process of a semiconductor device according to an embodiment of the present invention;
도3a 내지 도3e는 본 발명의 다른 실시예에 따른 반도체 소자의 금속 배선 형성 공정 단면도.3A to 3E are cross-sectional views of a metal wiring forming process of a semiconductor device in accordance with another embodiment of the present invention.
* 도면의 주요 부분에 대한 도면 부호의 설명* Explanation of reference numerals for the main parts of the drawings
20, 30: 반도체 기판 21, 31: 알루미늄 배선20, 30: semiconductor substrate 21, 31: aluminum wiring
22, 32, 33: 층간절연막 23, 34: 감광막 패턴22, 32, 33: interlayer insulating film 23, 34: photoresist pattern
24, 35: 비아 25, 36: 제1 확산장벽막24, 35: via 25, 36: first diffusion barrier
26, 37: 구리막 27, 38: 제2 확산장벽막26, 37: copper film 27, 38: second diffusion barrier film
Claims (6)
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| KR10-1998-0045311A KR100471404B1 (en) | 1998-10-28 | 1998-10-28 | Method for forming metal wiring of semiconductor device using chemical mechanical polishing process |
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| KR10-1998-0045311A KR100471404B1 (en) | 1998-10-28 | 1998-10-28 | Method for forming metal wiring of semiconductor device using chemical mechanical polishing process |
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| KR100471404B1 true KR100471404B1 (en) | 2005-05-27 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01241845A (en) * | 1988-03-23 | 1989-09-26 | Nec Corp | Manufacture of semiconductor device |
| JPH04158533A (en) * | 1990-10-22 | 1992-06-01 | Mitsubishi Electric Corp | Fabrication of compound semiconductor device |
| JPH06120219A (en) * | 1992-10-06 | 1994-04-28 | Nec Corp | Forming method of metal wiring |
| JPH06275612A (en) * | 1993-03-19 | 1994-09-30 | Fujitsu Ltd | Manufacture of integrated circuit device |
| KR0169283B1 (en) * | 1993-10-29 | 1999-02-01 | 사토 후미오 | Semiconductor device and method for manufacturing thereof |
-
1998
- 1998-10-28 KR KR10-1998-0045311A patent/KR100471404B1/en not_active IP Right Cessation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01241845A (en) * | 1988-03-23 | 1989-09-26 | Nec Corp | Manufacture of semiconductor device |
| JPH04158533A (en) * | 1990-10-22 | 1992-06-01 | Mitsubishi Electric Corp | Fabrication of compound semiconductor device |
| JPH06120219A (en) * | 1992-10-06 | 1994-04-28 | Nec Corp | Forming method of metal wiring |
| JPH06275612A (en) * | 1993-03-19 | 1994-09-30 | Fujitsu Ltd | Manufacture of integrated circuit device |
| KR0169283B1 (en) * | 1993-10-29 | 1999-02-01 | 사토 후미오 | Semiconductor device and method for manufacturing thereof |
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