JPH06120219A - Forming method of metal wiring - Google Patents

Forming method of metal wiring

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Publication number
JPH06120219A
JPH06120219A JP26696692A JP26696692A JPH06120219A JP H06120219 A JPH06120219 A JP H06120219A JP 26696692 A JP26696692 A JP 26696692A JP 26696692 A JP26696692 A JP 26696692A JP H06120219 A JPH06120219 A JP H06120219A
Authority
JP
Japan
Prior art keywords
film
groove
copper
wiring
barrier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP26696692A
Other languages
Japanese (ja)
Other versions
JP2970255B2 (en
Inventor
Akira Isobe
晶 礒部
Original Assignee
Nec Corp
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corp, 日本電気株式会社 filed Critical Nec Corp
Priority to JP26696692A priority Critical patent/JP2970255B2/en
Publication of JPH06120219A publication Critical patent/JPH06120219A/en
Application granted granted Critical
Publication of JP2970255B2 publication Critical patent/JP2970255B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To facilitate microminiaturization, and reduce the number of times of barrier film formation, by forming wiring by burying a barrier film and copper in a trench which is formed in an insulating film and has a wiring pattern. CONSTITUTION:A Cr film 3 and a Cu film 4 are formed in order on the surface containing a trench which is formed in the upper surface of a silicon oxide film 2 and has a wiring pattern. The Cu film 4 is buried in the trench by laser irradiation. By a chemical-mechanical polishing method, the Cr film 3 and the Cu film 4 on the part except the inside of the trench are eliminated, and the surface is flattened. A silicon nitride film 5 is deposited on the whole surface. Copper wiring whose periphery is covered with barrier films (the Cr film 3 and the silicon nitride film 5) can be precisely formed with a small number of times of barrier film formation.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は金属配線の形成方法に関
し、特にLSIの金属配線の形成方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wiring, and more particularly to a method for forming metal wiring for LSI.

【0002】[0002]

【従来の技術】LSIの配線材料としてはこれまでAl
系合金が広く使われてきた。ところが、配線の微細化が
進むにつれ、エレクトロマイグレーションやストレスマ
イグレーション等に対するAl系合金の耐性が限界に近
付きつつあり、より信頼性の高い配線材料の検討が盛ん
になってきている。
2. Description of the Related Art Al has been used as a wiring material for LSI until now.
Series alloys have been widely used. However, with the progress of miniaturization of wirings, the resistance of Al-based alloys against electromigration, stress migration, etc. is approaching the limit, and studies of wiring materials with higher reliability have become active.

【0003】そうしたAl配線にとって代る材料の一つ
の候補としてCuがある。しかし、Cu配線を実用化す
る上で大きな問題が二つある。一つはCuの加工が困難
である事。これは、Cuのハロゲン化物の蒸気圧が低い
為に、Al系合金等で用いられている反応性イオンエッ
チングが困難である事によっている。もう一つの問題点
は、Cuは容易に酸化シリコン膜中を拡散する為、絶縁
耐圧や、トランジスター特性を劣化させる原因となるこ
とである。
Cu is one candidate for a material to replace such Al wiring. However, there are two major problems in putting Cu wiring to practical use. One is that it is difficult to process Cu. This is because the vapor pressure of the halide of Cu is low, so that reactive ion etching used in Al-based alloys and the like is difficult. Another problem is that Cu easily diffuses in the silicon oxide film, which causes deterioration of withstand voltage and transistor characteristics.

【0004】加工方法としては、(A)ウェットエッチ
ングによる方法、(B)リフトオフ法による方法、例え
ば、プロシーディング・オブ・ザ・インターナショナル
・VLSI・マルチレベル・インターコネクション・コ
ンファレンス(Proceeding of the
international VLSI multil
evel interconnection conf
erence)1991年,137〜143頁に記載さ
れた方法、(C)イオンミリングによる方法、例えば、
プロシーディング・オブ・ザ・インターナショナル・V
LSI・マルチレベル・インターコネクション・コンフ
ァレンス(Proceeding of the in
ternatinal VLSI multileve
l interconnection confere
nce)1991年,99〜108頁に記載されている
方法、が知られているが、ウェットエッチングによる方
法では微細化が困難で、高集積度のLSIには適用でき
ない。
The processing method includes (A) a wet etching method and (B) a lift-off method, for example, Proceeding of the International VLSI Multilevel Interconnection Conference (Proceeding of the).
international VLSI multi
Eve interconnection conf
erence), 1991, pp. 137-143, (C) a method by ion milling, for example,
Proceeding of the International V
LSI Multi-level Interconnection Conference (Proceeding of the in
ternary VLSI multipleve
l interconnection confere
The method described in pp. 99-108, 1991, is difficult to miniaturize by the method by wet etching, and cannot be applied to a highly integrated LSI.

【0005】図3(a)〜(c)及び図4(a),
(b)はリフトオフ法を用いた従来の金属配線の形成方
法の第1の例を説明するための工程順に示した半導体チ
ップの断面図である。
3 (a) to 3 (c) and FIG. 4 (a),
(B) is sectional drawing of the semiconductor chip shown in order of process for demonstrating the 1st example of the conventional metal wiring formation method using the lift-off method.

【0006】まず、図3(a)に示すように、半導体基
板1の上に設けた酸化シリコン膜2の上にポリイミド膜
7を形成し、ポリイミド膜7の上に第1のフォトレジス
ト膜8,SOG膜9,第2のフォトレジスト膜10から
なる3層レジスト膜を形成する。次に、フォトレジスト
膜10を露光現像してパターニングし、これをマスクと
してSOG膜9をパターニングする。
First, as shown in FIG. 3A, a polyimide film 7 is formed on a silicon oxide film 2 provided on a semiconductor substrate 1, and a first photoresist film 8 is formed on the polyimide film 7. , A SOG film 9, and a second photoresist film 10 are formed to form a three-layer resist film. Next, the photoresist film 10 is exposed and developed and patterned, and the SOG film 9 is patterned using this as a mask.

【0007】次に、図3(b)に示すように、SOG膜
9をマスクとして酸素を含むドライエッチングによりフ
ォトレジスト膜8及びポリイミド膜7を順次エッチング
して配線形成用の溝を形成し、この際に含まれる酸素ラ
ジカルによる等方性エッチングにより、フォトレジスト
膜8,10及びポリイミド膜7をSOG膜9より後退さ
せる。
Next, as shown in FIG. 3B, the photoresist film 8 and the polyimide film 7 are sequentially etched by dry etching containing oxygen using the SOG film 9 as a mask to form a groove for wiring formation, The photoresist films 8 and 10 and the polyimide film 7 are made to recede from the SOG film 9 by isotropic etching using oxygen radicals contained at this time.

【0008】次に、図3(c)に示すように、溝を含む
表面にCr膜3,Cu膜4,Cr膜6を蒸着法により順
次堆積して溝内に配線を形成する。ここで、SOG膜9
がひさし状になっている為フォトレジスト膜8の側面に
はCr膜,Cu膜は付着しない。なお、Cr膜3,6は
ポリイミド膜7及び半導体基板1とCu膜4の反応を防
ぐためのバリアメタルである。
Next, as shown in FIG. 3C, a Cr film 3, a Cu film 4, and a Cr film 6 are sequentially deposited on the surface including the groove by a vapor deposition method to form wiring in the groove. Here, the SOG film 9
Since it has an eaves shape, the Cr film and the Cu film do not adhere to the side surface of the photoresist film 8. The Cr films 3 and 6 are barrier metals for preventing the reaction between the polyimide film 7 and the semiconductor substrate 1 and the Cu film 4.

【0009】次に、図4(a)に示すように、3層レジ
スト膜を剥離除去する事により、3層レジスト膜上に堆
積したCu膜4及びCr膜3,6が除去され、溝内の配
線が残る。このままでは配線側面とポリイミド膜の反応
が起きるので全面にプラズマCVD法により窒化シリコ
ン膜5を形成し、さらにその上にポリイミド膜11を堆
積して層間絶縁膜を形成する。
Next, as shown in FIG. 4A, the Cu film 4 and the Cr films 3 and 6 deposited on the three-layer resist film are removed by peeling and removing the three-layer resist film, and the inside of the groove is removed. Wiring remains. Since the reaction between the side surface of the wiring and the polyimide film occurs as it is, the silicon nitride film 5 is formed on the entire surface by the plasma CVD method, and the polyimide film 11 is further deposited thereon to form the interlayer insulating film.

【0010】図5(a)〜(d)はイオンミリング法を
用いた従来の金属配線の形成方法の第2の例を説明する
ための工程順に示した半導体チップの断面図である。
FIGS. 5A to 5D are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a second example of the conventional method of forming a metal wiring using the ion milling method.

【0011】まず、図5(a)に示すように、半導体基
板1の上に設けた酸化シリコン膜2の上にMo膜12,
Cu膜4,Mo膜13を順次堆積し、Mo膜13の上に
フォトレジスト膜14を塗布してパターニングする。こ
こでMo膜12,13はバイアメタルである。
First, as shown in FIG. 5A, a Mo film 12 is formed on the silicon oxide film 2 provided on the semiconductor substrate 1.
A Cu film 4 and a Mo film 13 are sequentially deposited, and a photoresist film 14 is applied on the Mo film 13 and patterned. Here, the Mo films 12 and 13 are via metals.

【0012】次に、図5(b)に示すように、イオンミ
リングによりフォトレジスト膜14をマスクとしてMo
膜13,Cu膜4,Mo膜12を順次エッチングし、配
線を形成する。
Next, as shown in FIG. 5B, Mo is formed by ion milling using the photoresist film 14 as a mask.
The film 13, the Cu film 4, and the Mo film 12 are sequentially etched to form wiring.

【0013】次に、図5(c)に示すように、フォトレ
ジスト膜14を除去した後、全面にMo膜15を成膜す
る。
Next, as shown in FIG. 5C, after removing the photoresist film 14, a Mo film 15 is formed on the entire surface.

【0014】次に、図5(d)に示すように、異方性の
反応性イオンエッチングによりエッチバックして、配線
の側面以外のMo膜15を除去し、Mo膜12,13,
15で被覆されたCu配線が得られる。
Next, as shown in FIG. 5 (d), the Mo film 15 other than the side surface of the wiring is removed by etching back by anisotropic reactive ion etching to remove the Mo films 12, 13,
The Cu wiring covered with 15 is obtained.

【0015】[0015]

【発明が解決しようとする課題】以上説明した従来の金
属配線形成方法は、リフトオフ法を用いる第1の例では
微細な配線を形成しようとすると、溝の幅が狭くなっ
て、レジスト膜をマスクとする溝内部へのCu膜の付着
量が少なくなり、所望の精度の配線幅、配線形状を得る
事が困難になってくる。また、リフトオフ時にレジスト
膜上のCu膜がパーティクルの原因となりやすいという
問題点もある。更に、基板やポリイミド膜との反応を防
止する為のバリア膜を3回にわたって形成するので、工
程が長くなるという問題点を有する。
In the conventional metal wiring forming method described above, in the first example using the lift-off method, when a fine wiring is formed, the width of the groove becomes narrow and the resist film is masked. Since the amount of the Cu film attached to the inside of the groove becomes small, it becomes difficult to obtain the desired wiring width and wiring shape. There is also a problem that the Cu film on the resist film is likely to cause particles during lift-off. Further, since the barrier film for preventing the reaction with the substrate or the polyimide film is formed three times, there is a problem that the process becomes long.

【0016】また、イオンミリング法を用いる第2の例
では、レジスト膜の後退により台形状の断面形状となる
為、微細化が難しい。また、やはり3回にわたってバリ
ア膜を形成する必要が有り、工程が長くなるという問題
点を有する。
Further, in the second example using the ion milling method, it is difficult to miniaturize since the resist film recedes to form a trapezoidal cross-sectional shape. In addition, it is necessary to form the barrier film three times, which causes a problem that the process becomes long.

【0017】[0017]

【課題を解決するための手段】本発明の金属配線の形成
方法は、半導体基板上に設けた絶縁膜の上面に配線形成
用パターンを有する溝を形成する工程と、前記溝を含む
表面にバリアメタル膜を形成して前記溝の底面及び側面
を被覆する工程と、前記溝を含むバリアメタル膜の表面
に銅膜又は銅合金膜を堆積して前記溝内に埋込む工程
と、化学−機械研磨法により前記溝内以外の銅膜又は銅
合金膜及びバリアメタル膜を除去して表面を平坦化する
工程と、前記銅膜又は銅合金膜を含む表面に銅と反応し
ない絶縁膜を堆積する工程とを含んで構成される。
A method of forming a metal wiring according to the present invention comprises a step of forming a groove having a wiring forming pattern on an upper surface of an insulating film provided on a semiconductor substrate, and a barrier on a surface including the groove. Forming a metal film to cover the bottom and side surfaces of the groove; depositing a copper film or a copper alloy film on the surface of the barrier metal film including the groove and burying it in the groove; A step of removing the copper film or the copper alloy film and the barrier metal film other than in the groove by a polishing method to flatten the surface; and depositing an insulating film that does not react with copper on the surface including the copper film or the copper alloy film. And a process.

【0018】[0018]

【実施例】次に、本発明の実施例について図面を参照し
て説明する。
Embodiments of the present invention will now be described with reference to the drawings.

【0019】図1(a)〜(d)は本発明の第1の実施
例を説明するための工程順に示した半導体チップの断面
図である。
FIGS. 1A to 1D are cross-sectional views of a semiconductor chip shown in the order of steps for explaining the first embodiment of the present invention.

【0020】まず、図1(a)に示すように、半導体基
板1の上に酸化シリコン膜2を形成した後、酸化シリコ
ン膜2の表面にリソグラフィー技術及びエッチング技術
を用いて、深さ0.5μmの配線形成用パターンを有す
る溝を形成する。
First, as shown in FIG. 1A, after a silicon oxide film 2 is formed on a semiconductor substrate 1, the surface of the silicon oxide film 2 is etched to a depth of 0. A groove having a wiring forming pattern of 5 μm is formed.

【0021】次に、図1(b)に示すように、溝を含む
酸化シリコン膜2の上にスパッタ法により厚さ0.1μ
mのCr膜3及び厚さ0.7μmのCu膜4を順次堆積
して形成する。
Next, as shown in FIG. 1B, a thickness of 0.1 μm is formed on the silicon oxide film 2 including the groove by a sputtering method.
m Cr film 3 and 0.7 μm thick Cu film 4 are sequentially deposited.

【0022】次に、図1(c)に示すように、Cu膜4
の表面を約1.5J/cm2 のエネルギーを持つエキシ
マレーザビームで照射し、Cu膜4を流動せしめ、溝の
内部に埋め込み表面を平坦化する。
Next, as shown in FIG. 1C, the Cu film 4 is formed.
Is irradiated with an excimer laser beam having an energy of about 1.5 J / cm 2 to cause the Cu film 4 to flow and to flatten the embedded surface inside the groove.

【0023】次に、図1(d)に示すように、Cu膜4
の上面を化学−機械研磨法により研磨し、溝部以外のC
u膜4及びCr膜3を順次除去して酸化シリコン膜2の
上面を露出させ、表面を平坦化する。次に、プラズマC
VD法により窒化シリコン膜5を0.3μmの厚さに成
膜する。
Next, as shown in FIG. 1D, the Cu film 4 is formed.
The upper surface of the C was polished by a chemical-mechanical polishing method to remove C except the groove.
The u film 4 and the Cr film 3 are sequentially removed to expose the upper surface of the silicon oxide film 2 and flatten the surface. Next, plasma C
A silicon nitride film 5 is formed to a thickness of 0.3 μm by the VD method.

【0024】ここで、Cu膜4の代りにTiを含むCu
合金膜を用いても良い。
Here, instead of the Cu film 4, Cu containing Ti is used.
An alloy film may be used.

【0025】図2(a)〜(d)は本発明の第2の実施
例を説明するための工程順に示した半導体チップの断面
図である。
2 (a) to 2 (d) are sectional views of the semiconductor chip in the order of steps for explaining the second embodiment of the present invention.

【0026】図2(a)に示すように、第1の実施例と
同様の工程で半導体基板1の上に設けた酸化シリコン膜
2の上面に、深さ0.5μmの配線形成用パターンを有
する溝を設けた後スパッタ法によりCr膜3及びCu膜
4を順次堆積して形成する。次に、Cu膜4の上面をエ
キシマレーザビームで照射し、Cu膜を流動せしめて溝
内部に埋め込んだ後、化学−機械研磨法により研磨し、
溝部以外のCu膜4及びCr膜3を除去して表面を平坦
化する。
As shown in FIG. 2A, a wiring forming pattern having a depth of 0.5 μm is formed on the upper surface of the silicon oxide film 2 provided on the semiconductor substrate 1 in the same process as in the first embodiment. After forming the groove, the Cr film 3 and the Cu film 4 are sequentially deposited by the sputtering method. Next, the upper surface of the Cu film 4 is irradiated with an excimer laser beam to flow the Cu film to fill the inside of the groove, and then polished by a chemical-mechanical polishing method.
The Cu film 4 and the Cr film 3 other than the groove are removed to planarize the surface.

【0027】次に、図2(b)に示すように、イオンミ
リングにより溝内部のCu膜4及びCr膜3の表面が酸
化シリコン膜2の表面より0.1μm低くなるようにエ
ッチングする。
Next, as shown in FIG. 2B, etching is carried out by ion milling so that the surfaces of the Cu film 4 and the Cr film 3 inside the groove are lower than the surface of the silicon oxide film 2 by 0.1 μm.

【0028】次に、図2(c)に示すように、全面に厚
さ0.1μmのCr膜6をスパッタ法により成膜する。
Next, as shown in FIG. 2C, a Cr film 6 having a thickness of 0.1 μm is formed on the entire surface by a sputtering method.

【0029】次に、図2(d)に示すように、再び上面
を化学−機械研磨法により研磨して溝部以外のCr膜6
を除去する。
Next, as shown in FIG. 2D, the upper surface is polished again by the chemical-mechanical polishing method to form the Cr film 6 other than the groove portion.
To remove.

【0030】第2の実施例では層間絶縁膜に誘電率の高
い窒化シリコン膜を用いる事無く銅配線をバリア膜で覆
う事が出来るので、層間容量に起因するデバイスの動作
速度の低下が問題とならない。
In the second embodiment, since the copper wiring can be covered with the barrier film without using a silicon nitride film having a high dielectric constant as the interlayer insulating film, there is a problem that the operating speed of the device is lowered due to the interlayer capacitance. I won't.

【0031】ここで、銅の成膜、埋め込み方法として、
スパッタ法とレーザー熱処理による方法を用いて説明し
たが、ブランケットCVD法や鍍金法を用いても、同様
な工程を経る事によりバリア膜で覆われた加工精度の良
い銅配線を得る事が出来る。
Here, as a method for forming and filling copper,
Although the method using the sputtering method and the laser heat treatment has been described, a blanket CVD method or a plating method can also be used to obtain a copper wiring covered with a barrier film and having a high processing accuracy by the same steps.

【0032】[0032]

【発明の効果】以上説明したように本発明では、絶縁膜
に形成した溝を含む表面にCu膜を堆積した後溝内以外
のCu膜を化学−機械研磨により除去し、溝内にCu膜
を埋め込む事により配線を形成している為、ドライエッ
チングの困難なCu膜自身をエッチングする工程を無く
して、加工精度良く銅配線を形成する事が出来、配線の
微細化にも対応できるという効果を有する。また、これ
までは、下層、上層、側面と少なくとも3回必要であっ
たバリア膜の形成が2回で済むので工程が短縮され、製
造コストが下がるという利点もある。
As described above, according to the present invention, after depositing a Cu film on the surface including the groove formed in the insulating film, the Cu film other than the inside of the groove is removed by chemical-mechanical polishing to form the Cu film in the groove. Since the wiring is formed by embedding the copper wire, the step of etching the Cu film itself, which is difficult to dry-etch, can be eliminated, and the copper wiring can be formed with high processing accuracy, and the wiring can be miniaturized. Have. In addition, the barrier film, which has been required at least three times for the lower layer, the upper layer, and the side surface until now, can be formed only twice, so that the process can be shortened and the manufacturing cost can be reduced.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例を説明するための工程順
に示した断面図。
1A to 1D are cross-sectional views showing a process sequence for explaining a first embodiment of the present invention.

【図2】本発明の第2の実施例を説明するための工程順
に示した断面図。
2A to 2D are sectional views showing a process sequence for explaining a second embodiment of the present invention.

【図3】従来の金属配線の形成方法の第1の例を説明す
るための工程順に示した断面図。
3A to 3C are sectional views showing a first example of a conventional method for forming a metal wiring in the order of steps for explaining the first example.

【図4】従来の金属配線の形成方法の第1の例を説明す
るための工程順に示した断面図。
4A to 4C are sectional views showing the first example of the conventional method for forming a metal wiring in the order of processes for explaining the first example.

【図5】従来の金属配線の形成方法の第2の例を説明す
るための工程順に示した断面図。
5A to 5C are cross-sectional views showing the second example of the conventional method for forming a metal wiring in the order of steps for explaining the second example.

【符号の説明】[Explanation of symbols]

1 半導体基板 2 酸化シリコン膜 3,6 Cr膜 4 Cu膜 5 窒化シリコン膜 7,11 ポリイミド膜 8,10,14 フォトレジスト膜 9 SOG膜 12,13,15 Mo膜 1 Semiconductor Substrate 2 Silicon Oxide Film 3,6 Cr Film 4 Cu Film 5 Silicon Nitride Film 7,11 Polyimide Film 8,10,14 Photoresist Film 9 SOG Film 12,13,15 Mo Film

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板上に設けた絶縁膜の上面に配
線形成用パターンを有する溝を形成する工程と、前記溝
を含む表面にバリアメタル膜を形成して前記溝の底面及
び側面を被覆する工程と、前記溝を含むバリアメタル膜
の表面に銅膜又は銅合金膜を堆積して前記溝内に埋込む
工程と、化学−機械研磨法により前記溝内以外の銅膜又
は銅合金膜及びバリアメタル膜を除去して表面を平坦化
する工程と、前記銅膜又は銅合金膜を含む表面に銅と反
応しない絶縁膜を堆積する工程とを含むことを特徴とす
る金属配線の形成方法。
1. A step of forming a groove having a wiring forming pattern on an upper surface of an insulating film provided on a semiconductor substrate, and a barrier metal film is formed on a surface including the groove to cover a bottom surface and a side surface of the groove. And a step of depositing a copper film or a copper alloy film on the surface of the barrier metal film including the groove and burying it in the groove, and a copper film or a copper alloy film other than in the groove by a chemical-mechanical polishing method. And a step of flattening the surface by removing the barrier metal film, and a step of depositing an insulating film which does not react with copper on the surface including the copper film or the copper alloy film. .
【請求項2】 溝を含むバリアメタル膜の表面に堆積し
た銅膜又は銅合金にレーザビームを照射して流動化し前
記溝内に埋込む工程を含む請求項1記載の金属配線の形
成方法。
2. The method for forming metal wiring according to claim 1, further comprising the step of irradiating a copper film or a copper alloy deposited on the surface of the barrier metal film including a groove with a laser beam to fluidize the metal film and bury the metal film in the groove.
【請求項3】 化学−機械研磨法により溝内以外の銅膜
又は銅合金膜及びバリアメタル膜を除去して表面を平坦
化した後反応性イオンエッチング又はイオンミリングに
より前記銅膜又は銅合金膜の上面を薄く除去して前記溝
周囲の絶縁膜の上面よりも低くする工程を含む請求項1
又は請求項2記載の金属配線の形成方法。
3. The copper film or copper alloy film is removed by reactive ion etching or ion milling after removing the copper film or copper alloy film and the barrier metal film other than in the groove by chemical-mechanical polishing to flatten the surface. 2. A step of thinly removing the upper surface of the insulating film to make it lower than the upper surface of the insulating film around the groove.
Alternatively, the method for forming a metal wiring according to claim 2.
JP26696692A 1992-10-06 1992-10-06 Method of forming metal wiring Expired - Fee Related JP2970255B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26696692A JP2970255B2 (en) 1992-10-06 1992-10-06 Method of forming metal wiring

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26696692A JP2970255B2 (en) 1992-10-06 1992-10-06 Method of forming metal wiring

Publications (2)

Publication Number Publication Date
JPH06120219A true JPH06120219A (en) 1994-04-28
JP2970255B2 JP2970255B2 (en) 1999-11-02

Family

ID=17438185

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26696692A Expired - Fee Related JP2970255B2 (en) 1992-10-06 1992-10-06 Method of forming metal wiring

Country Status (1)

Country Link
JP (1) JP2970255B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10154709A (en) * 1996-09-25 1998-06-09 Toshiba Corp Manufacture of semiconductor device
US5793112A (en) * 1996-04-11 1998-08-11 Mitsubishi Denki Kabushiki Kaisha Multilevel embedded wiring system
KR19990003485A (en) * 1997-06-25 1999-01-15 김영환 Metal wiring formation method of semiconductor device
JP2001274159A (en) * 2000-03-28 2001-10-05 Toshiba Corp Method of manufacturing semiconductor device
KR100471404B1 (en) * 1998-10-28 2005-05-27 주식회사 하이닉스반도체 Method for forming metal wiring of semiconductor device using chemical mechanical polishing process

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5793112A (en) * 1996-04-11 1998-08-11 Mitsubishi Denki Kabushiki Kaisha Multilevel embedded wiring system
US6184124B1 (en) 1996-04-11 2001-02-06 Mitsubishi Denki Kabushiki Kaisha Method of making embedded wiring system
JPH10154709A (en) * 1996-09-25 1998-06-09 Toshiba Corp Manufacture of semiconductor device
KR19990003485A (en) * 1997-06-25 1999-01-15 김영환 Metal wiring formation method of semiconductor device
KR100471404B1 (en) * 1998-10-28 2005-05-27 주식회사 하이닉스반도체 Method for forming metal wiring of semiconductor device using chemical mechanical polishing process
JP2001274159A (en) * 2000-03-28 2001-10-05 Toshiba Corp Method of manufacturing semiconductor device

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