KR20040077307A - Method for forming of damascene metal wire - Google Patents

Abstract

PURPOSE: A method for forming a damascene metal line is provided to improve step coverage of an inner wall of an aperture by forming a sidewall spacer on an undercut of an inner wall of an aperture. CONSTITUTION: The first diffusion barrier(14) is formed on a lower metal line(12). An interlayer dielectric(16) is formed on the first diffusion barrier. An aperture is formed on the interlayer dielectric. The residual buffer layer is removed from the aperture by performing a wet-etch process. A sidewall spacer is formed on an undercut of an inner wall of the aperture. A barrier layer liner is coated on the lower metal line of the bottom of the aperture and the sidewall spacer of the inner wall of the aperture. A copper seed liner(40) is coated on the barrier layer liner.

Description

Method for forming damascene metal wiring {METHOD FOR FORMING OF DAMASCENE METAL WIRE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to metallization of semiconductor integrated circuit devices, and more particularly, to a method of forming metallization of semiconductor devices by a dual damascene process.

As the degree of integration of semiconductor devices increases, the metal wiring layer having a multilayer wiring structure also increases, so that the gap between the metal wirings is gradually narrowed. Accordingly, parasitic resistance and capacitance components present between the metal wiring layers adjacent to each other on the same layer or between the wiring layers adjacent to each other up and down have become the most important problems.

Parasitic resistance and capacitance components in metal wiring systems degrade the device's operating characteristics due to the delay induced by RC. In addition, parasitic resistance and capacitance components present between the wiring layers increase the total power consumption of the chip and increase the signal leakage. Therefore, it is very important to develop a multi-layered wiring technology with a small RC in an ultra-high density semiconductor integrated circuit device.

In order to form a high performance multilayer wiring structure with small RC, it is necessary to form a wiring layer using a metal having a low resistivity or to use an insulating film having a low dielectric constant. In order to reduce the resistance in a metal wiring layer, the research which uses the metal with low specific resistance, for example, copper as a metal material which forms a metal wiring layer, is currently active actively.

Copper wiring is difficult to obtain by direct patterning by photolithography. Therefore, the damascene process is mainly used to form copper wiring.

The damascene process first forms an interlayer insulating film and then forms vias and grooves in the interlayer insulating film by a photolithography technique. Subsequently, metal is deposited on the interlayer insulating film, and only the metal embedded in the via and the groove is left, and the remaining metal is removed by chemical mechanical polishing to form metal wiring. Therefore, the metal etching process is avoided.

Cu wiring by the damascene process requires a dual damascene process to overcome the high cost and performance degradation of the single damascene process. In the dual damascene process, a via first is formed rather than a trench first, which is advantageous in the photolithography technique.

When the low dielectric constant film is used as the interlayer insulating film in the via first method, the etching selectivity of the diffusion barrier exposed on the bottom of the via must be taken into consideration when trench etching.

For this reason, a method of etching a trench using an organic film such as BARC (BOTTOM ANTI REFLECT COAT) as a via filling material is used.

However, due to the etching selectivity of the interlayer insulating film and the organic film, a high dielectric material such as a polymer is formed as a via fence on the inner wall of the via, which adversely increases parasitic capacitance.

Therefore, the SOF (SPIN ON GLASS) -based inorganic film having similar selectivity to the interlayer insulating film is used to cope with the via fan problem.

However, when inorganic films are used, the method of removing the buried material after trench formation generally uses a chemical strip method using a wet chemical such as hydrofluoric acid (HF). There is a problem that occurs.

Such undercuts in the trench and via inner walls serve as a factor in generating coating defects or voids in subsequent barrier layer and copper seed liner formation processes.

An object of the present invention is to form a sidewall spacer on the inner wall of the opening after the wet strip process to solve the problems of the prior art by coating the undercut portion to form a damascene metal wiring method that can solve the delamination problem due to the undercut. To provide.

1 to 11 is a view showing a preferred embodiment of the damascene metal wiring method according to the present invention.

* Brief description of symbols for the main parts of the drawings *

10: insulating film 12: lower copper-based metal wiring

14 first diffusion barrier 16: interlayer insulating film

18: etch stop film 20: interlayer insulating film

22: via open pattern 24: opening

26: inorganic filler 28: trench open pattern

30: trench 32: left inorganic filler

34: second diffusion barrier 36: via

38: wetting liner 40: copper seed liner

42: upper copper metal wiring

In the method of the present invention, in the method for forming a copper damascene metal wiring in which a lower metal wiring is covered with a first diffusion preventing film, an interlayer insulating film is formed thereon, and an opening is formed in the interlayer insulating film, the buffer film remaining in the opening is removed by a wet strip, An undercut of the inner wall of the opening is coated with sidewall spacers, a barrier layer liner is coated on the bottom metallization exposed to the bottom of the opening and a spacer of the opening sidewall, and a copper seed liner is coated on the barrier layer liner.

In the present invention, the interlayer insulating film includes an interlayer insulating film, an etch stop film, and an interlayer insulating film for the dual damascene process.

In the present invention, the diffusion barrier film, the etch stop film, or the etch stop film is a non-oxide-based insulating film containing H, C, or N, and a nitride film such as SiN or BN or a carbon film such as SiC.

In the present invention, an interlayer dielectric film (INTRA IMD; INTER METAL DIELECTRIC) is a doped oxide-based low dielectric constant film containing H, C, or CHx. Here, the interlayer insulating film means an insulating film which insulates adjacent wirings in the same layer. That is, metal wiring is formed in the interlayer insulating film.

In the present invention, an interlayer insulating film (INTER IMD) or ILD (INTER LAYER DIELECTRIC) uses a low dielectric constant film such as SiON. Here, the interlayer insulating film means an insulating film for insulating between upper and lower metal wiring layers. Vias are formed in the interlayer insulating film.

In the present invention, the buffer layer uses an SOD (SPIN ON DIELECTRIC) film such as HSQ (HYDROGEN SILSESQUIOXANES) or MSQ (METHYL SILSESQUIOXANES), Fox (Flowable oxide) film or SOG (Spin-On Glass) film as the inorganic filler.

The sidewall spacer uses the same or similar material as the diffusion barrier or the etch stop layer. Silicon nitride films are preferred.

In the present invention, the opening includes vias or trenches and vias.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the following embodiments are provided to those skilled in the art to fully understand the present invention, and may be modified in various forms, and the scope of the present invention is described in the following embodiments. It is not limited. In the following description, when a layer is described as being on top of another layer, it may be present directly on top of another layer, with a third layer interposed therebetween. In the drawings, the thickness or size of each layer is exaggerated for clarity and convenience of explanation. Like numbers refer to like elements in the figures.

<Example>

Embodiments of the invention use a dual damascene process.

Referring to FIG. 1, a lower copper based wiring layer 12 is formed on an insulating film 10 on a semiconductor substrate (not shown), and a diffusion barrier 14 or an insulating film 10 is formed on an insulating film 10 on which a lower copper based wiring layer 12 is formed. An etch stop film is deposited. The diffusion barrier 14 is a non-oxide insulating film formed of a SiN, BN or SiC film.

Subsequently, the interlayer insulating film 16, the etch stop film 18, and the interlayer insulating film 20 are sequentially deposited. The interlayer insulating film 16 uses an inorganic low dielectric constant film such as SiON. The etch stop layer 18 is a nitride layer that prevents etching of the lower interlayer insulating layer 16 during trench etching. The interlayer insulating film 20 is a doped oxide low dielectric constant film containing H, C, or CHx.

Referring to FIG. 2, a via open pattern 22 made of photoresist is formed on a layered insulating film 20 by a conventional photolithography process.

Referring to FIG. 3, an opening 24 is formed by sequentially etching the interlayer insulating film 20, the etch stop film 18, and the interlayer insulating film 16 using the via open pattern 22 as an etching mask. The diffusion barrier 14 is exposed at the bottom of the opening 24. Subsequently, the via open pattern 22 is removed by an ashing process.

Referring to FIG. 4, an inorganic film such as a spin on die (SOD) film, a flowable oxide (SOW) film, or a spin-on glass (SOG) film, such as a HYDROGEN SILSESQUIOXANES (HSQ) or a METHYL SILSESQUIOXANES (MSQ), may be formed on the resultant. The buffer film 26 is deposited to fill the opening 24. The surface of the deposited buffer film 26 is processed to have a flat surface by chemical mechanical polishing, and is left to a certain thickness on the interlayer insulating film 20.

Referring to FIG. 5, a trench open pattern 28 made of photoresist is formed on the buffer layer 26 by a normal photolithography process.

Referring to FIG. 6, the trench 30 is formed by selectively etching the exposed interlayer insulating layer 20 and the buffer layer 26 using the trench open pattern 28 as an etching mask. The exposed interlayer insulating film 20 and the buffer film 26 are removed until the etch stop film 18 is exposed. The buffer layer 32 and the etch stop layer 18 remaining in the opening 28 are exposed at the bottom of the trench 30.

Next, the trench open pattern 28 is removed by an ashing process.

Referring to FIG. 7, the buffer film 32 exposed on the bottom of the trench 30 and the buffer film 32 left on the interlayer insulating film 20 are interlayer insulating film 16, etch stop film 18, and interlayer insulating film. Wet strip with HF with high selectivity for (20).

When etching with HF, the undercut 33 is generated along the interface of the dissimilar material. This undercut 33 causes poor step coverage of the subsequent barrier layer liner.

Referring to FIG. 8, a silicon nitride film 34 is deposited to a uniform thickness along the profile of the trench 30 and the remaining openings 24 on the entire surface of the resultant.

Referring to FIG. 9, when the silicon nitride film 34 is anisotropically etched, the silicon nitride film 34 remains only on the sidewalls of the trench 30 and the opening 24. The remaining silicon nitride film acts as a diffusion barrier 34 to prevent copper diffusion into the interlayer insulating film and the interlayer insulating film.

Subsequently, the diffusion barrier layer 14 continuously exposed to the bottom is removed to expose the top surface of the lower copper based wiring layer 12 to complete the via 36.

Referring to FIG. 10, barrier layer liners 38, such as Ta or TaN, and copper seed liners 40 are sequentially formed along the resulting profile.

Preferably, barrier layer liner 38 may be deposited using CVD techniques or physical vapor deposition (PVD) techniques. Barrier layer liner 38 may have a thickness of about 30 kPa to about 500 kPa, preferably about 50 kPa to about 300 kPa.

Next, a copper seed liner 40 is deposited on the barrier layer liner 38. Copper seed liner 40 is preferably deposited using CVD techniques, but may be deposited using electroless techniques or other substantial deposition techniques. Many CVD techniques and electroless techniques are apparent to those skilled in the art of forming copper seed liner 40. The thickness of the copper seed liner 40 may be from about 50 kPa to about 500 kPa, more preferably from about 100 kPa to about 300 kPa.

Referring to FIG. 11, when the copper is deposited by electroplating and the surface is planarized to expose the interlayer insulating film 20 by chemical mechanical polishing, the upper copper-based metallization layer 42 and vias are formed in the trench 30. Contacts are formed at the same time. The upper wiring layer 42 and the lower wiring layer 12 are formed by via contacts.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Therefore, as described above, in the present invention, embedding of the buffer film for protecting the diffusion barrier film exposed at the bottom of the opening during trench formation is inevitable. In the process of wet stripping the residual buffer layer in the opening after trench formation, step coverage of the inner wall of the opening may be improved by coating an undercut generated along the interface of the dissimilar material on the inner wall of the opening with the sidewall spacer. Thus, subsequent barrier layer liners and copper seed liners can be formed to a uniform thickness without discontinuity.

Claims (5)

In the copper damascene metal wiring formation method which covered the lower metal wiring with a 1st diffusion prevention film, formed the interlayer insulation film on it, and formed the opening in the interlayer insulation film, Removing the remaining buffer film in the opening with a wet strip; Coating an undercut of the inner wall of the opening with sidewall spacers; Coating a barrier layer liner on the spacers of the lower sidewalls and the opening sidewalls exposed to the bottom of the openings; And Forming a copper seed liner on the barrier layer liner. The method of claim 1, wherein the sidewall spacers Depositing a silicon nitride film with a uniform thickness along the profile of the opening; And And anisotropically etching the deposited silicon nitride film. The method of claim 1, wherein the barrier layer liner is tantalum or tantalum nitride. The method of claim 1, wherein the damascene process is a dual damascene process. The method of claim 4, wherein the opening is formed of a first via and a post trench.