KR100755112B1 - Method for manufacturing inductor of semiconductor device - Google Patents

Abstract

A method for manufacturing inductor of a semiconductor device is provided to reduce the generation of etching residues formed on a via hole and a trench sidewall by separating a dry etching process for forming the via hole and a trench. A lower wire(104) of an inductor is formed on a lower structure(100) of a semiconductor substrate. A first etch stop layer(106) and a second interlayer dielectric(108) are sequentially formed on an upper surface of a first interlayer dielectric(102) having the lower wire. Parts of the second interlayer dielectric and the first etch stop layer are selectively etched to form a via hole. A gap-fill layer(112) gap-fills the via hole. A second etch stop layer(114) and a third interlayer dielectric(116) are sequentially formed on the whole surface of the second interlayer dielectric and the gap-fill layer. Parts of the third interlayer dielectric and the second etch stop layer are selectively etched to form a trench(118) defining an upper wire region of the inductor. The gap-fill layer in the via hole is removed.

Description

METHODS FOR MANUFACTURING INDUCTOR OF SEMICONDUCTOR DEVICE

1A through 1D are process flowcharts sequentially illustrating an inductor manufacturing process of a semiconductor device according to the prior art;

2A to 2F are process flowcharts sequentially illustrating an inductor manufacturing process of a semiconductor device according to the present invention.

<Description of the code | symbol about the principal part of drawing>

100: lower structure of semiconductor substrate 102: first interlayer insulating film

104: lower wiring 106: first etching stop film

108: second interlayer insulating film 110: via hole

112: gap peel film 114: second etching stop film

116: third interlayer insulating film 118: trench

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing an inductor of a semiconductor device suitable for greatly reducing polymer generation in an inductor wiring manufacturing process.

In connection with the shrinking of the semiconductor device, the current density increases due to the reduction in the cross-sectional area of the wiring, which causes a serious problem in the reliability of the metal wiring by EM (electromigration). Therefore, copper (Cu), which is lower in specific resistance than aluminum (Al) and has excellent reliability, is used as a material for metal wiring.

However, since copper is difficult to form a highly volatile compound, there is a difficulty in a dry etching process for forming a fine pattern. The damascene process was introduced to solve the problem of patterning copper wiring. The damascene process first deposits an interlayer insulating film and patterns the interlayer insulating film through a photolithography process to form trenches, which are wiring regions, gap-fill copper in the trenches, and then chemical mechanical polishing (CMP) processes. It is planarized to form copper wiring. In addition, the dual damascene process has the advantage of simultaneously forming via and copper wiring in a single chemical mechanical polishing (CMP) process.

Meanwhile, inductors widely used as passive devices in semiconductor devices are also manufactured by copper wiring using a damascene process or a dual damascene process.

1A to 1D are process flowcharts sequentially illustrating an inductor manufacturing process of a semiconductor device according to the prior art. Hereinafter, an example of an inductor manufacturing process of a semiconductor device according to the prior art will be described with reference to these drawings.

As shown in FIG. 1A, a BPSG is deposited as a first interlayer insulating film 12 by a chemical vapor deposition (CVD) process on a lower structure 10 of a semiconductor substrate on which a MOS transistor or the like is formed and dried or wetted. Etching forms a trench that defines the lower wiring area of the inductor. The lower gap 14 is formed by gap-filling copper in the trench by electroplating or physical vapor deposition (PVD), and planarizing it in a chemical mechanical polishing (CMP) process.

Then, a silicon nitride film (Si ₃ N ₄ ) is deposited on the lower wiring 14 and the upper surface of the first interlayer insulating film 12 as a first etching stop film 16 by a chemical vapor deposition (CVD) process. A silicon oxide film (SiO ₂ ) is deposited on the substrate as the second interlayer insulating film 18 by chemical vapor deposition (CVD).

Next, a photoresist process is performed on the second interlayer insulating layer 18 to form a photoresist pattern (not shown) defining a via hole region for vertically connecting the upper and lower interconnections of the inductor. Subsequently, as shown in FIG. 1B, after forming a groove 20 defining a via hole region by dry or wet etching a predetermined thickness of the second interlayer insulating layer 18, the photoresist pattern is removed by an etching process.

Subsequently, as illustrated in FIG. 1C, a silicon nitride film (Si ₃ N ₄ ) is deposited on the entire surface of the second interlayer insulating film 18 as the second etching stop film 22. A silicon oxide film (SiO ₂ ) is deposited on the upper surface of the second etch stop layer 22 as a third interlayer insulating film 24 by chemical vapor deposition (CVD).

A photoresist pattern is formed on the third interlayer insulating layer 24 to form a photoresist pattern (not shown) defining a trench region for vertically connecting the upper wiring of the inductor.

Subsequently, as shown in FIG. 1D, a dry etching process (eg, a reactive ion etching (RIE) process) may be performed to form a part of the third interlayer insulating film 24 and the second etching stop layer 22. The trench 26 defining the upper wiring region of the inductor is formed on the lower wiring by etching the rest of the second etch stop film 22 and the first etch stop film 16 along the groove of the second interlayer insulating film 18. (14) After forming the via holes 28 whose surfaces are exposed, the photoresist pattern is removed by an etching process.

Then, although not shown in the drawings, the copper is gapfilled in the trench 26 and the via hole 28 by an electroplating or physical vapor deposition (PVD) process, and the copper surface is planarized by a chemical mechanical polishing (CMP) process. By forming a via and an upper wiring (not shown) which are connected to the lower wiring 14 vertically, an inductor of a semiconductor device is manufactured.

However, in the method of manufacturing an inductor of a semiconductor device according to the related art, since the third interlayer insulating film 24 to the first etch stop layer 16 are etched at one time, the amount of etching is large, resulting in etching residues on the trench and via hole sidewalls. For example, the polymer 30 is thick. The etching residue 30 is not completely removed even by etching or wet etching, and when the etching residue 30 remains, not only causes the electrical performance of the inductor, but also the etching residue 30 during the etching process. ), It becomes difficult to secure critical dimensions (CD) of trenches and via holes.

Disclosure of Invention An object of the present invention is to solve the problems of the prior art as described above, the method of manufacturing an inductor of a semiconductor device that can easily secure the critical dimensions of the trench and via holes while reducing the generation of etching residues during the trench and via hole etching process. To provide.

In order to achieve the above object, the present invention provides a method of manufacturing an inductor for a semiconductor device, the method comprising the steps of forming a lower wiring of the inductor in the lower structure of the semiconductor substrate, and the first surface on the upper surface of the first interlayer insulating film having the lower wiring Sequentially forming an etch stop film and a second interlayer insulating film, selectively etching a portion of the second interlayer insulating film and the first etch stop film to form a via hole, gap filling a gap fill film in the via hole, a second interlayer insulating film, Sequentially forming a second etch stop layer and a third interlayer insulating layer on the gap fill layer, and selectively etching a portion of the third interlayer insulating layer and the second etch stop layer to form a trench defining an upper wiring region of the inductor And removing the gapfill film gapfilled in the via hole of the first etch stop film.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

2A to 2F are process flowcharts sequentially illustrating an inductor manufacturing process of a semiconductor device according to the present invention. The inductor manufacturing process of the semiconductor device according to the exemplary embodiment of the present invention will be described below with reference to these drawings.

As shown in FIG. 2A, a BPSG is deposited as a first interlayer insulating film 102 by a chemical vapor deposition (CVD) process on a lower structure 100 of a semiconductor substrate on which a MOS transistor or the like is formed and dried or wet etched to form an inductor. A trench defining a lower wiring region is formed. The lower gap 104 is formed by gap-filling copper in the trench by an electroplating or physical vapor deposition (PVD) process and planarizing it in a chemical mechanical polishing (CMP) process.

A silicon nitride film (Si ₃ N ₄ ) is deposited on the lower wiring 104 and the upper surface of the first interlayer insulating film 102 as a first etching stop film 106 by a chemical vapor deposition (CVD) process. A silicon oxide film (SiO ₂ ) is deposited on the substrate as the second interlayer insulating film 108 by a chemical vapor deposition (CVD) process.

Next, a photoresist process is performed on the second interlayer insulating layer 108 to form a photoresist pattern (not shown) that defines a via hole region for vertically connecting the upper and lower interconnections of the inductor. Subsequently, as shown in FIG. 2B, the second interlayer insulating layer 108 and the first etch stop layer 106 are etched by a dry etching (eg, reactive ion etching (RIE)) process to form the lower wiring 104. After the exposed via hole 110 is formed, the photoresist pattern is removed by an etching process.

Subsequently, as shown in FIG. 2C, the via holes of the second interlayer insulating layer 108 and the first etch stop layer 106 are filled with a material such as a gap fill layer 112, for example, a novolac, and etched. The novolac on the second interlayer insulating film 108 is removed by a process or the like.

As shown in FIG. 2D, the silicon nitride layer Si ₃ N ₄ is formed as the second etch stop layer 114 by a chemical vapor deposition (CVD) process on the entire surface of the second interlayer insulating layer 108 and the gap fill layer 112. Deposit about 2000Å. A silicon oxide film (SiO ₂ ) is deposited on the upper surface of the second etch stop film 114 as a third interlayer insulating film 116 by chemical vapor deposition (CVD).

Then, a photoresist process is performed on the third interlayer insulating layer 116 to form a photoresist pattern (not shown) defining a trench region for vertically connecting the upper wiring of the inductor.

Next, as shown in FIG. 2E, a dry etching (eg, reactive ion etching (RIE)) process is performed to etch the third interlayer insulating layer 116 and the second etching stop layer 114 to form an upper portion of the inductor. The trench 118 defining the wiring area is formed.

As shown in FIG. 2F, the gap fill layer 112, which is a material such as novolac, is gap-filled in the via hole of the second interlayer insulating layer 108 and the first etching stop layer 106 by a wet etching or etching process. do. In this case, the photoresist pattern for forming the trench may also be removed.

Then, although not shown in the drawings, the copper is gapfilled in the trench 118 and the via hole 110 by an electroplating or physical vapor deposition (PVD) process, and the copper surface is planarized by a chemical mechanical polishing (CMP) process. By forming a via and an upper wiring (not shown) that is vertically connected to the lower wiring 104, to manufacture an inductor of a semiconductor device according to the present invention.

In the method of manufacturing an inductor of a semiconductor device according to the present invention, a via hole is formed in the second interlayer insulating layer 108 and the first etch stop layer 106 by a dry etching process, and a gap fill layer 112 made of a material such as novolac in the via hole. After the gap fill gap), the third interlayer insulating film 116 and the second etch stop layer 114 are dry etched to form the trench 118 defining the upper wiring region of the inductor, and then the gap fill film 112 gap-filled in the via hole. ).

Therefore, the present invention can greatly reduce the production of etch residues formed in the via holes and trench sidewalls by separating the dry etching process for the via holes and trench formation.

In the foregoing description of the present invention, only one embodiment has been described, but it is obvious that the technology of the present invention can be easily modified by those skilled in the art. Such modified embodiments should be included in the technical spirit described in the claims of the present invention.

As described above, in the present invention, after the via holes are formed in the second interlayer insulating film and the first etch stop film by a dry etching process, and the gap fill film made of a material such as novolac is gap-filled in the via hole, the third interlayer insulating film and the second etch stop are finished Dry etching the film to form a trench defining the upper wiring region of the inductor and then removing the gapfill film gap-filled in the via hole.

Therefore, the present invention can greatly reduce the generation of etch residues formed in the via holes and the trench sidewalls by separating the dry etching process for the via hole and the trench formation during the inductor manufacturing process, thereby accurately securing the critical dimensions of the trenches and via holes. There is an advantage to that.

Claims (5)

delete In the method of manufacturing an inductor of a semiconductor device, Forming a lower wiring of the inductor on the lower structure of the semiconductor substrate; Sequentially forming a first etch stop layer and a second interlayer insulating layer on an upper surface of the first interlayer insulating layer having the lower wiring; Forming a via hole by selectively etching a portion of the second interlayer insulating layer and the first etch stop layer, and gap filling a gap fill layer in the via hole; Sequentially forming a second etch stop layer and a third interlayer insulating layer on the entire surface of the second interlayer insulating layer and the gap fill layer; Selectively etching a portion of the third interlayer insulating layer and the second etch stop layer to form a trench defining an upper wiring region of the inductor; Removing a gapfill film gapped in the via hole of the first etch stop film Wherein the gap filling of the gap fill layer comprises gap filling the via hole with a novolac and removing the novolac on the second interlayer insulating layer by an etch process. The method of claim 2, The removing of the gap fill layer may include a wet etching or etching process. The method of claim 2, The via hole may be formed through a reactive ion etching process. The method of claim 2, The trench is a method of manufacturing an inductor of a semiconductor device, characterized in that formed through a reactive ion etching process.

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