KR100315453B1 - Method for forming metal line dielectric layer of semiconductor devices - Google Patents
Method for forming metal line dielectric layer of semiconductor devices Download PDFInfo
- Publication number
- KR100315453B1 KR100315453B1 KR1019990021194A KR19990021194A KR100315453B1 KR 100315453 B1 KR100315453 B1 KR 100315453B1 KR 1019990021194 A KR1019990021194 A KR 1019990021194A KR 19990021194 A KR19990021194 A KR 19990021194A KR 100315453 B1 KR100315453 B1 KR 100315453B1
- Authority
- KR
- South Korea
- Prior art keywords
- metal wiring
- film
- oxide film
- vapor deposition
- chemical vapor
- Prior art date
Links
- 239000002184 metal Substances 0.000 title claims abstract description 44
- 238000000034 method Methods 0.000 title abstract description 24
- 239000004065 semiconductor Substances 0.000 title abstract description 18
- 239000010408 film Substances 0.000 claims abstract description 53
- 239000010409 thin film Substances 0.000 claims abstract description 20
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 17
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims abstract description 11
- 238000000151 deposition Methods 0.000 claims abstract description 10
- 239000000126 substance Substances 0.000 claims abstract description 6
- 238000007517 polishing process Methods 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 5
- 238000005530 etching Methods 0.000 abstract description 5
- 238000005498 polishing Methods 0.000 abstract description 2
- 230000008021 deposition Effects 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 238000001465 metallisation Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000010410 layer Substances 0.000 description 3
- 238000004904 shortening Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000000313 electron-beam-induced deposition Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
Abstract
HDP 화학 기상 증착에 의한 산화막으로 금속 배선 패턴 사이 갭을 충분히 매입할 수 있도록 함과 동시에 낮은 고주파 RF 파워가 인가되도록 하여 안테나 손상 및 ESC의 수명 단축을 방지하기 위하여, 하부 박막 상부에 금속 배선 패턴을 형성하고, 하부 박막 전면에 TEOS 라이너막을 증착하며, 낮은 Ar 가스 공급량에 의한 HDP 화학 기상 증착으로 산화막을 증착하여 금속 배선 패턴 사이의 갭을 매입한 후, 산화막 상부에 절연막을 증착하고, 화학 기계적 연마 공정에 의해 평탄화하여 반도체 소자의 금속 배선 절연막을 형성하는 것으로, 종래의 HDP 화학 기상 증착에 비해 상대적으로 낮은 Ar 가스량을 이용하여 식각 효과는 떨어뜨리고 금속 배선 패턴 사이 갭의 충분한 매입 효과를 얻을 수 있으며, 이에 따라 ESC에 인가되는 고주파 RF 파워를 상태적으로 감소시킬 수 있어 ESC의 수명을 연장시킬 수 있을 뿐만 아니라 플라즈마에 의한 안테나 손상을 방지할 수 있어 공정의 신뢰성을 향상시킬 수 있다.In order to sufficiently fill the gaps between the metal wiring patterns with the oxide film by HDP chemical vapor deposition and to apply low high frequency RF power to prevent antenna damage and shorten the life of the ESC, a metal wiring pattern is formed on the upper part of the lower thin film. Forming, depositing TEOS liner film on the lower thin film, depositing the oxide film by HDP chemical vapor deposition by low Ar gas supply amount, filling the gap between the metal wiring pattern, and then depositing an insulating film on the oxide film, chemical mechanical polishing By forming the metal wiring insulating film of the semiconductor element by planarization by the process, using the relatively low amount of Ar gas compared to the conventional HDP chemical vapor deposition, the etching effect can be reduced, and sufficient gap effect between the metal wiring patterns can be obtained. Therefore, when the state of the high frequency RF power applied to the ESC is reduced It can only be able to extend the life of the ESC as it is possible to prevent damage to the antenna due to the plasma may improve the reliability of the process.
Description
본 발명은 반도체 소자를 제조하는 공정에 관한 것으로, 더욱 상세하게는 반도체 집적 회로에서의 배선을 다층화하여 웨이퍼 내에 배치된 각 반도체 소자간의 조합에 자유도를 주어 고밀도의 반도체 소자를 제조할 경우 각 금속 배선의 절연막을 형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a process for manufacturing a semiconductor device, and more particularly, in order to fabricate a high density semiconductor device by providing a degree of freedom in a combination of semiconductor devices arranged in a wafer by multilayering wirings in a semiconductor integrated circuit. It relates to a method of forming an insulating film.
일반적으로 반도체 소자의 제조 공정에서 실리콘웨이퍼 상에 1층만의 배선에서는 배선 패턴 설계상의 자유도가 작아, 실질적인 배선이 길어짐으로써 웨이퍼 내 소자의 레이아웃에도 큰 제약이 가해진다. 이것에 반해서 금속 배선을 다층화하면 아주 효율이 높은 설계가 가능하다. 즉, 칩 위에 배선을 통과시키는 스페이서를 고려하지 않고 각 소자가 레이아웃되기 때문에 집적도 및 밀도가 향상되어 칩 사이즈가 축소된다. 그리고, 배선의 자유도가 증가하고, 패턴 설계가 용이해짐과 함께 배선 저항이나 전류 용량 등의 설정을 여유를 가지고 할 수 있게 된다.In general, only one layer of wiring on a silicon wafer in the manufacturing process of a semiconductor device has a small degree of freedom in designing a wiring pattern, and since the actual wiring is long, a great restriction is placed on the layout of the devices in the wafer. On the other hand, multi-layered metal wiring enables a highly efficient design. That is, since each device is laid out without considering the spacers that allow wiring to pass on the chip, the degree of integration and density are improved and the chip size is reduced. This increases the degree of freedom in wiring, facilitates pattern design, and allows setting of wiring resistance, current capacity, and the like with a margin.
이러한 금속 배선의 다층화에서는 폴리 실리콘과 금속 박막 또는 금속 박막과 금속 박막 사이의 절연을 위한 절연막 표면의 요곡이 현저해지기 때문에 표면에서의 배선의 오픈이나 쇼트 등이 발생하게 되는 데, 이를 방지하기 위하여 금속 배선 패턴 사이의 갭(gap)을 SOG(spin on glass)막으로 매입하여 금속 배선 절연막의 평탄화 정도를 좋게 하였다.In the multilayering of the metal wirings, the curvature of the surface of the insulating film for insulation between the polysilicon and the metal thin film or the metal thin film and the metal thin film becomes remarkable, so that opening or shorting of the wiring on the surface occurs. A gap between the metal wiring patterns was buried in a spin on glass (SOG) film to improve the planarization degree of the metal wiring insulating film.
그러나, SOG막은 수분 함유량이 많아 금속 박막 등의 부식에 의해 반도체 소자의 수명이 단축되는 등 박막 특성이 나쁘므로 현재에는 HDP(high density plasma) 화학 기상 증착(chemical vapor deposition, CVD)을 이용한 산화막으로 금속 배선 패턴 사이의 갭을 매입하여 금속 배선 절연막의 평탄화 정도를 좋게 하고 있다.However, the SOG film has a high moisture content and thus has a poor thin film characteristic such as shortening the life of a semiconductor device due to corrosion of a metal thin film. Therefore, the SOG film is an oxide film using HDP (high density plasma) chemical vapor deposition (CVD). The gap between the metal wiring patterns is embedded to improve the planarization degree of the metal wiring insulating film.
그러면, 도 1a 내지 도 1c를 참조하여 HDP 화학 기상 증착을 이용한 반도체 소자의 금속 배선 절연막을 형성하는 방법을 개략적으로 설명한다.1A to 1C, a method of forming a metallization insulating film of a semiconductor device using HDP chemical vapor deposition is schematically described.
먼저 도 1a에 도시한 바와 같이, 콘택(contact)이나 비아(via)가 형성된 하부 층간 절연막과 같은 하부 박막(1) 상부에 전자선 증착 방법 또는 스퍼터(sputter) 방법에 의해 금속 박막을 증착한 다음, 금속 배선 형성을 위하여 금속 박막을 패터닝(patterning)하여 금속 박막 패턴(2)을 형성한다. 그리고, 하부 박막(1) 전면에 TEOS(tetraethylorthosilicate) 라이너(liner) 막(3)을 500Å 정도의 두께로 증착한다.First, as shown in FIG. 1A, a metal thin film is deposited on the lower thin film 1, such as a lower interlayer insulating film having a contact or via, by an electron beam deposition method or a sputtering method. The metal thin film pattern 2 is patterned to form a metal thin film pattern 2 to form a metal wiring. Then, a TEOS (tetraethylorthosilicate) liner film 3 is deposited on the lower thin film 1 to a thickness of about 500 GPa.
그 다음 도 1b에 도시한 바와 같이, 금속 배선 패턴 사이의 갭에 의해 후속 공정에서 금속 배선을 절연하기 위한 절연막의 증착시 발생되는 요곡을 최소화하기 위하여 TEOS 라이너막(3) 상부에 HDP 화학 기상 증착을 이용하여 SiH4근원의 산화막(4)을 증착하여 금속 배선 패턴 사이의 갭을 매입한다. 이때, HDP 화학 기상 증착은 SiH495sccm, Ar 390sccm, O2150sccm, 고주파(high frequency) RF(radio frequency) 3400W, 저주파(low frequency) RF 3500W, 웨이퍼 후면(back side) He 압력 8Torr의 조건으로 E/D(etch/deposition) 비(ratio)가 0.34 정도가 되도록 조절한다. E/D 비는 저주파 RF 파워에 의한 산화막의 증착율에 대한 고주파 RF 파워에 의한 산화막의 식각율을 나타낸 것이며, HDP 화학 기상 증착은 고주파 RF에 의한 식각과 저주파 RF에 의한 증착이 반복되면서 산화막이 증착된다.Then, as shown in FIG. 1B, HDP chemical vapor deposition on the TEOS liner film 3 to minimize the distortion caused during the deposition of the insulating film for insulating the metal wiring in a subsequent process by the gap between the metal wiring patterns. The oxide film 4 of the SiH 4 source is deposited using the method to fill the gap between the metal wiring patterns. At this time, HDP chemical vapor deposition is performed under conditions of SiH 4 95sccm, Ar 390sccm, O 2 150sccm, high frequency radio frequency (RF) 3400W, low frequency RF 3500W, wafer back side He pressure 8Torr Adjust so that the E / D (etch / deposition) ratio is about 0.34. The E / D ratio shows the etching rate of the oxide film by the high frequency RF power against the deposition rate of the oxide film by the low frequency RF power. do.
그 다음 도 1c에 도시한 바와 같이, HDP 화학 기상 증착된 산화막(4) 상부에 절연막(또는 층간 절연막)(5) 즉, 캡핑(capping)용 TEOS막을 증착한 후, 후속 콘택 홀 또는 비아 홀의 사진 식각 공정을 원활하게 하기 위하여 화학 기계적 연마(chemical mechanical polishing, CMP) 공정에 의해 평탄화함으로써 반도체 소자의 금속 배선 절연막을 완성한다.Then, as shown in FIG. 1C, an insulating film (or interlayer insulating film) 5, that is, a capping TEOS film is deposited on the HDP chemical vapor deposited oxide film 4, and then photographs of subsequent contact holes or via holes. In order to smooth the etching process, the metal wiring insulating film of the semiconductor device is completed by planarization by a chemical mechanical polishing (CMP) process.
이와 같은 종래의 방법에서는 금속 배선 패턴 사이 갭의 종횡비(aspec ratio)가 2.5:1 이하일 경우, 금속 배선 패턴 사이의 갭을 충분히 매입하기 위해서는 HDP 화학 기상 증착의 E/D 비를 0.3 이상이 되도록 조절하여야 하므로 높은 고주파 RF 파워가 인가되어야 한다. 따라서, 웨이퍼가 놓이는 ESC(electro static chuck)에 높은 고주파 RF 파워가 인가되므로 플라즈마 손상에 의한 반도체 소자의 게이트 산화막이 열화되는 안테나(antenna) 손상이 발생하며, ESC에 높은 고주파 RF 파워가 인가되므로 ESC의 수명이 단축되는 문제점이 있다.In such a conventional method, when the aspect ratio of the gap between the metal wiring patterns is 2.5: 1 or less, the E / D ratio of the HDP chemical vapor deposition is adjusted to 0.3 or more to sufficiently fill the gap between the metal wiring patterns. High frequency RF power should be applied. Therefore, high frequency RF power is applied to the ESC (electro static chuck) on which the wafer is placed, thereby causing antenna damage to the gate oxide film of the semiconductor device due to plasma damage, and high frequency RF power is applied to the ESC. There is a problem that the life of the shortening.
본 발명은 이와 같은 문제점을 해결하기 위한 것으로, 그 목적은 HDP 화학 기상 증착에 의한 산화막으로 금속 배선 패턴 사이 갭을 충분히 매입할 수 있도록 함과 동시에 낮은 고주파 RF 파워가 인가되도록 하여 안테나 손상 및 ESC의 수명 단축을 방지하는 데 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and its object is to sufficiently fill the gap between the metal wiring patterns with the oxide film by HDP chemical vapor deposition, and to apply low frequency RF power to the antenna damage and ESC. To prevent shortening of life.
도 1a 내지 도 1c는 종래 반도체 소자의 금속 배선 절연막을 형성하는 방법을 개략적으로 도시한 공정도이고,1A to 1C are process diagrams schematically showing a method of forming a metallization insulating film of a conventional semiconductor device,
도 2a 내지 도 2c는 본 발명에 따라 반도체 소자의 금속 배선 절연막을 형성하는 방법을 개략적으로 도시한 공정도이고,2A to 2C are process diagrams schematically showing a method of forming a metallization insulating film of a semiconductor device according to the present invention;
도 3a는 종래 방법에 의해 금속 배선 사이의 갭을 매입한 상태를 개략적으로 도시한 SEM사진이고,3A is a SEM photograph schematically showing a state where a gap between metal wirings is embedded by a conventional method,
도 3b는 본 발명에 의해 금속 배선 사이의 갭을 매입한 상태를 개략적으로 도시한 SEM사진이다.3B is a SEM photograph schematically showing a state where a gap between metal wirings is embedded according to the present invention.
상기와 같은 목적을 달성하기 위하여, 본 발명은 하부 박막 상부에 금속 배선 패턴을 형성하고, 하부 박막 전면에 TEOS 라이너막을 증착하며, 낮은 Ar 가스 공급량에 의한 HDP 화학 기상 증착으로 산화막을 증착하여 금속 배선 패턴 사이의 갭을 매입한 후, 산화막 상부에 절연막을 증착하고, 화학 기계적 연마 공정에 의해 평탄화하는 것을 특징으로 한다.In order to achieve the above object, the present invention forms a metal wiring pattern on the lower thin film, deposit a TEOS liner film on the lower thin film, and deposit the oxide film by HDP chemical vapor deposition by a low Ar gas supply amount After filling the gap between the patterns, an insulating film is deposited on the oxide film and planarized by a chemical mechanical polishing process.
이하, 첨부된 도면을 참조하여 본 발명에 따른 바람직한 일 실시예를 설명한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.
도 2a 내지 도 2d는 본 발명에 따라 반도체 소자의 금속 배선 절연막을 형성하는 방법을 개략적으로 도시한 공정도이다.2A to 2D are process diagrams schematically illustrating a method of forming a metallization insulating film of a semiconductor device according to the present invention.
먼저 도 2a에 도시한 바와 같이, 콘택이나 비아가 형성된 하부 층간 절연막과 같은 하부 박막(11) 상부에 전자선 증착 방법 또는 스퍼터 방법에 의해 금속 박막을 증착한 후, 금속 배선 형성을 위하여 금속 박막을 패터닝하여 금속 박막 패턴(12)을 형성한다. 그리고, 하부 박막(11) 전면에 TEOS 라이너막(13)을 500Å 정도의 두께로 증착한다.First, as shown in FIG. 2A, a metal thin film is deposited on the lower thin film 11, such as a lower interlayer insulating film on which a contact or via is formed, by an electron beam deposition method or a sputtering method, and then the metal thin film is patterned to form a metal wiring. The metal thin film pattern 12 is formed. Then, the TEOS liner film 13 is deposited on the entire surface of the lower thin film 11 to a thickness of about 500 GPa.
그 다음 도 1b에 도시한 바와 같이, 금속 배선 패턴 사이의 갭에 의해 후속 공정에서 금속 배선을 절연하기 위한 절연막의 증착시 발생되는 요곡을 최소화하기 위하여 TEOS 라이너막(13) 상부에 HDP 화학 기상 증착을 이용하여 SiH4근원의 산화막(14)을 증착하여 금속 배선 패턴 사이의 갭을 매입한다. 이때, HDP 화학 기상 증착은 SiH470sccm 내지 90sccm, Ar 40sccm 내지 60sccm, O2110sccm 내지 130sccm, 고주파 RF 2600W 내지 3000W, 저주파 RF 2700W 내지 3300W, 웨이퍼 후면 He 압력 5Torr 내지 6Torr의 조건으로 E/D 비가 0.20 내지 0.24 정도가 되도록 조절한다.Then, as shown in FIG. 1B, HDP chemical vapor deposition on the TEOS liner film 13 to minimize the distortion caused during the deposition of the insulating film for insulating the metal wiring in a subsequent process by the gap between the metal wiring patterns. The oxide film 14 of the SiH 4 source is deposited using the method to fill the gap between the metal wiring patterns. At this time, HDP chemical vapor deposition is SiH 4 70sccm to 90sccm, Ar 40sccm to 60sccm, O 2 110sccm to 130sccm, high frequency RF 2600W to 3000W, low frequency RF 2700W to 3300W, wafer back side He pressure 5Torr to 6Torr E / D ratio Adjust to about 0.20 to 0.24.
그러며, 종래 HDP 화학 기상 증착에서의 Ar 가스 공급량 390sccm에 비해 Ar 가스 공급량이 40sccm 내지 60sccm으로 낮기 때문에 식각율 감소로 인해 E/D 비가 상대적으로 작게 된다. 그리고, E/D 비가 상대적으로 작기 때문에 ESC에 가하는 고주파 RF 파워를 상대적으로 낮게 할 수 있어 플라즈마 손상에 의해 반도체 소자의게이트 산화막이 열화되는 안테나 손상을 방지할 수 있으며, 상대적으로 낮은 고주파 RF 파워 인가에 따라 ESC의 수명을 연장시킬 수 있다.Therefore, since the Ar gas supply amount is 40 sccm to 60 sccm, compared to the Ar gas supply amount of 390 sccm in the conventional HDP chemical vapor deposition, the E / D ratio is relatively small due to the reduction of the etching rate. In addition, since the E / D ratio is relatively small, the high frequency RF power applied to the ESC can be relatively low, thereby preventing antenna damage from deteriorating the gate oxide film of the semiconductor device due to plasma damage, and applying a relatively low high frequency RF power. This can extend the life of the ESC.
더구나, 종래의 상대적으로 높은 Ar 공급량으로 갭 매입을 하였을 경우의 SEM(scanning electron microscope) 사진과 본 발명에 따라 상대적으로 낮은 Ar 공급량으로 갭 매입을 하였을 경우의 SEM 사진을 비교하여 볼때, 금속 배선 패턴 사이 갭 매입 효과 측면에서는 차이가 없이 충분히 갭을 매입할 수 있다. 즉, 도 3a의 'A' 부분과 도 3b의 'B' 부분을 비교하면, 양측 모두 보이드의 발생없이 충분히 갭을 매입하고 있다.Moreover, when comparing the conventional SEM (scanning electron microscope) photograph when the gap was purchased with a relatively high Ar supply amount and the SEM photograph when the gap was purchased with a relatively low Ar supply amount according to the present invention, the metal wiring pattern The gap can be sufficiently purchased without any difference in terms of the gap purchase effect. That is, when comparing the portion 'A' of FIG. 3A and the portion 'B' of FIG. 3B, both sides sufficiently fill the gap without generating voids.
그 다음 도 2c에 도시한 바와 같이, HDP 화학 기상 증착된 산화막(14) 상부에 절연막(또는 층간 절연막)(15) 즉, 캡핑용 TEOS막을 증착한 후, 후속 콘택 홀 또는 비아 홀의 사진 식각 공정을 원활하게 하기 위하여 화학 기계적 연마 공정에 의해 평탄화함으로써 반도체 소자의 금속 배선 절연막을 완성한다.Next, as shown in FIG. 2C, an insulating film (or interlayer insulating film) 15, that is, a capping TEOS film is deposited on the HDP chemical vapor deposition oxide layer 14, and then a subsequent photo-etch process of a subsequent contact hole or via hole is performed. In order to facilitate the smoothing, the metal wiring insulating film of the semiconductor element is completed by planarization by a chemical mechanical polishing process.
상기의 실시예에서는 금속 배선을 절연하기 위한 절연막 형성 방법에 대해 설명하였지만, 이와는 달리 반도체 소자의 금속 배선층 형성 이후 반도체 소자를 보호하기 위한 보호막(passivation) 형성 공정 등 다양한 응용이 가능하다.In the above-described embodiment, the insulating film forming method for insulating the metal wiring has been described. However, various applications such as a passivation process for protecting the semiconductor device may be performed after the metal wiring layer of the semiconductor device is formed.
이와 같이 본 발명은 종래의 HDP 화학 기상 증착에 비해 상대적으로 낮은 Ar 가스량을 이용하여 식각 효과는 떨어뜨리고 금속 배선 패턴 사이 갭의 충분한 매입 효과를 얻을 수 있으며, 이에 따라 ESC에 인가되는 고주파 RF 파워를 상태적으로 감소시킬 수 있어 ESC의 수명을 연장시킬 수 있을 뿐만 아니라 플라즈마에 의한 안테나 손상을 방지할 수 있어 공정의 신뢰성을 향상시킬 수 있다.As described above, the present invention can reduce the etching effect by using a relatively low amount of Ar gas compared to the conventional HDP chemical vapor deposition, and obtain a sufficient embedding effect of the gap between the metal wiring patterns, thereby increasing the high frequency RF power applied to the ESC. It can be reduced in a state to extend the life of the ESC as well as to prevent the antenna damage by the plasma can improve the reliability of the process.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990021194A KR100315453B1 (en) | 1999-06-08 | 1999-06-08 | Method for forming metal line dielectric layer of semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990021194A KR100315453B1 (en) | 1999-06-08 | 1999-06-08 | Method for forming metal line dielectric layer of semiconductor devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20010001768A KR20010001768A (en) | 2001-01-05 |
| KR100315453B1 true KR100315453B1 (en) | 2001-11-26 |
Family
ID=19590840
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019990021194A KR100315453B1 (en) | 1999-06-08 | 1999-06-08 | Method for forming metal line dielectric layer of semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100315453B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030058015A (en) * | 2001-12-29 | 2003-07-07 | 주식회사 하이닉스반도체 | Method of forming high density plasm oxide layer for semiconductor device |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100717823B1 (en) * | 2004-12-28 | 2007-05-11 | 주식회사 하이닉스반도체 | Method for forming inter metal dielectric layer in semiconductor device |
-
1999
- 1999-06-08 KR KR1019990021194A patent/KR100315453B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030058015A (en) * | 2001-12-29 | 2003-07-07 | 주식회사 하이닉스반도체 | Method of forming high density plasm oxide layer for semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20010001768A (en) | 2001-01-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6268274B1 (en) | Low temperature process for forming inter-metal gap-filling insulating layers in silicon wafer integrated circuitry | |
| JPH11204645A (en) | Interlayer insulating film of semiconductor device and manufacture thereof | |
| US20030137051A1 (en) | Semiconductor device and a method of producing the same | |
| JP2000332106A (en) | Semiconductor device for its manufacture | |
| KR100315453B1 (en) | Method for forming metal line dielectric layer of semiconductor devices | |
| US20050026341A1 (en) | Method of forming isolation dummy fill structures | |
| KR100652317B1 (en) | Method for manufacturing metal pad of the semiconductor device | |
| KR100440261B1 (en) | Method of manufacturing a metal line in semiconductor device | |
| JPH1140669A (en) | Multilayered wiring structure and its manufacture | |
| KR100664339B1 (en) | Method for forming metal line of semiconductor device | |
| KR100307827B1 (en) | Metal wiring contact formation method of semiconductor device | |
| KR20100076548A (en) | Method for forming semiconductor device | |
| US20070145598A1 (en) | Method of forming a metal interconnection in a semiconductor device | |
| US20060138667A1 (en) | Method for forming an intermetal dielectric layer in a semiconductor device using HDP-CVD, and a semiconductor device manufactured thereby | |
| KR100713896B1 (en) | method for forming a inter metal dielectic layer | |
| KR100352304B1 (en) | Semiconductor device and method of manufacturing the same | |
| KR100497206B1 (en) | Method for smoothing inter-metal dielectric layer of semiconductor device | |
| KR100260512B1 (en) | Planation method of insulation film between layers | |
| KR0166826B1 (en) | Method of interlayer insulating film in a semiconductor device | |
| KR100325597B1 (en) | Method for forming contact hole in semiconductor device | |
| KR100299332B1 (en) | Method for manufacturing intermetal dielectric layer of semiconductor devices | |
| KR100613381B1 (en) | Metal line formation method of semiconductor device | |
| KR0186081B1 (en) | Interconnections structure of semiconductor device and method for manufacturing thereof | |
| KR100457740B1 (en) | A method for manufacturing a multi-layer metal line of a semiconductor device | |
| KR100406733B1 (en) | manufacturing method of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20080930 Year of fee payment: 8 |
|
| LAPS | Lapse due to unpaid annual fee |