KR100299332B1 - Method for manufacturing intermetal dielectric layer of semiconductor devices - Google Patents
Method for manufacturing intermetal dielectric layer of semiconductor devices Download PDFInfo
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- KR100299332B1 KR100299332B1 KR1019990035412A KR19990035412A KR100299332B1 KR 100299332 B1 KR100299332 B1 KR 100299332B1 KR 1019990035412 A KR1019990035412 A KR 1019990035412A KR 19990035412 A KR19990035412 A KR 19990035412A KR 100299332 B1 KR100299332 B1 KR 100299332B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 238000000034 method Methods 0.000 title abstract description 12
- 239000010410 layer Substances 0.000 claims abstract description 28
- 239000002184 metal Substances 0.000 claims abstract description 26
- 239000011229 interlayer Substances 0.000 claims abstract description 25
- 238000005530 etching Methods 0.000 claims abstract description 23
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 9
- 239000000126 substance Substances 0.000 claims abstract description 4
- 239000010408 film Substances 0.000 claims description 62
- 239000010409 thin film Substances 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 claims description 2
- 238000007517 polishing process Methods 0.000 claims description 2
- 238000001020 plasma etching Methods 0.000 abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000001465 metallisation Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000011521 glass Substances 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 230000008021 deposition Effects 0.000 description 2
- 239000003960 organic solvent Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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Abstract
금속 배선층 사이를 전기적으로 접속하는 접촉구를 형성하기 위한 플라즈마 식각 공정에서 발생되는 플라즈마 손상을 최소화할 수 있도록 하는 반도체 소자의 층간 절연막 제조 방법을 제공하기 위하여, 금속 배선층이 형성된 하부 박막 상부에 산화막과의 식각 선택비가 큰 라이너 절연막을 형성하고, 라이너 절연막 상부에 화학 기상 증착으로 라이너 산화막을 증착하고, 라이너 산화막 상부에 SOG막을 형성하고, SOG막 상부에 화학 기상 증착으로 산화막을 증착한 후, 화학 기계적 연마 공정에 의해 평탄화하여 반도체 소자의 층간 절연막을 형성하는 것으로, 산화막 구조 하부에 산화막과의 식각 선택비가 큰 라이너 절연막을 형성하여 층간 절연막을 형성함으로써, 산화막의 과도 식각시 금속 배선 패턴이 드러나지 않으므로 플라즈마 손상을 방지할 수 있으며, 산화막의 과도 식각 이후 라이너 절연막을 식각하므로 플라즈마 손상을 최소화할 수 있어 반도체 소자의 신뢰성 및 수율을 향상시킬 수 있다.In order to provide a method for manufacturing an interlayer insulating film of a semiconductor device capable of minimizing plasma damage generated in a plasma etching process for forming a contact hole for electrically connecting metal wiring layers, an oxide film and After forming a liner insulating film having a large etch selectivity of, the liner oxide film is deposited by chemical vapor deposition on the liner insulating film, the SOG film is formed on the liner oxide film, and the oxide film is deposited by chemical vapor deposition on the SOG film, and then chemical mechanical The planarization is performed to form an interlayer insulating film of a semiconductor device. A liner insulating film having a large etching selectivity with an oxide film is formed under the oxide film structure to form an interlayer insulating film so that the metal wiring pattern is not exposed during the over etching of the oxide film. Prevent damage And, after the excessive etching of the oxide film because the insulating film etching the liner it is possible to minimize the damage to the plasma may improve the reliability and yield of semiconductor devices.
Description
본 발명은 반도체 소자를 제조하는 공정에 관한 것으로, 더욱 상세하게는 반도체 소자의 제조 공정 중 금속 배선층과 금속 배선층 사이를 전기적으로 절연하기 위한 층간 절연막을 제조하는 방법에 관한 것이다.The present invention relates to a process for manufacturing a semiconductor device, and more particularly, to a method for manufacturing an interlayer insulating film for electrically insulating between a metal wiring layer and a metal wiring layer during a semiconductor device manufacturing process.
일반적으로 반도체 소자의 제조 공정에서 실리콘웨이퍼 상부에 1층만으로 형성한 배선에서는 패턴 설계상의 자유도가 작아, 실질적인 배선이 길어짐으로써 실리콘웨이퍼 내 소자의 레이아웃에도 큰 제약이 가해진다. 이것에 반해서 금속 배선을 다층화하면 아주 효율이 높은 설계가 가능하다. 즉, 반도체 칩 위에 배선을 통과시키는 스페이스를 고려하지 않고 각 소자가 레이아웃되기 때문에 집적도 및 밀도가 향상되어 반도체 칩 사이즈가 축소된다. 그리고, 배선의 자유도가 증가하고, 패턴 설계가 용이해짐과 함께 배선 저항이나 전류 용량 등의 설정을 여유를 가지고 할 수 있게 된다.In general, the wiring formed with only one layer on the silicon wafer in the manufacturing process of the semiconductor device has a small degree of freedom in designing the pattern, and since the actual wiring is long, a great restriction is placed on the layout of the device in the silicon wafer. On the other hand, multi-layered metal wiring enables a highly efficient design. That is, since each element is laid out without considering the space for passing wiring over the semiconductor chip, the degree of integration and density are improved, and the size of the semiconductor chip is reduced. This increases the degree of freedom in wiring, facilitates pattern design, and allows setting of wiring resistance, current capacity, and the like with a margin.
이러한 금속 배선의 다층화에서는 금속 배선층과 금속 배선층 사이의 절연을 위한 층간 절연막 표면의 요곡이 현저해지기 때문에 표면에서의 배선의 오픈이나 쇼트 등이 발생하게 되는 데, 이를 방지하기 위하여 층간 절연막 제조시 표면을 평탄화하고 있다.In the multilayering of the metal wirings, the curvature of the interlayer insulating film surface for the insulation between the metal wiring layer and the metal wiring layer becomes remarkable, so that opening or shorting of the wiring occurs on the surface. Is flattening.
그러면, 도 1을 참조하여 종래 반도체 소자의 층간 절연막을 제조하는 방법을 설명한다.Next, a method of manufacturing an interlayer insulating film of a conventional semiconductor device will be described with reference to FIG. 1.
금속 배선 패턴(2)이 형성된 하부 박막(1) 상부에 화학 기상 증착법(chemical vapor deposition, CVD)으로 라이너 산화막(3)을 증착한 다음, 각 금속 배선 패턴(2) 사이의 갭(gap)에 의해 후속 공정에서 산화막 증착시 발생되는 요곡을 최소화하기 위하여 SOG(spin on glass)에 의해 유기 용제로 녹인 유리를 회전 도포하고 열처리하여 SOG 박막(4)을 형성한다.The liner oxide film 3 is deposited on the lower thin film 1 on which the metallization pattern 2 is formed by chemical vapor deposition (CVD), and then a gap is formed between the metallization patterns 2. As a result, the SOG thin film 4 is formed by rotationally applying and heat-treating a glass melted with an organic solvent by spin on glass (SOG) in order to minimize the curvature generated during oxide film deposition in a subsequent process.
이후, SOG 박막(4) 상부에 화학 기상 증착법으로 산화막(5)을 두껍게 증착한 다음, 화학 기계적 연마 공정(chemical mechanical polishing, CMP)에 의해 평탄화하여 전체 두께가 8㎛ 내지 12㎛ 정도인 층간 절연막(3, 4, 5)을 완성한다.Subsequently, an oxide film 5 is thickly deposited on the SOG thin film 4 by chemical vapor deposition, and then planarized by chemical mechanical polishing (CMP) to form an interlayer insulating film having a total thickness of about 8 μm to 12 μm. Complete (3, 4, 5).
이와 같이 제조된 전체가 산화막 구조인 반도체 소자의 층간 절연막(3, 4,5)에서 금속 배선층과 금속 배선층을 전기적으로 연결하기 위하여 플라즈마 식각에 의해 접촉구(6)를 형성하게 된다. 이때, 플라즈마 식각은 층간 절연막(3, 4, 5)을 메인 식각(main etch)하여 금속 배선층과 금속 배선층을 전기적으로 접속시키기 위한 접촉구(6)를 형성한 후, 접촉구(6)의 금속 배선 패턴(2) 상부에 부분적으로 잔류하는 층간 절연막 즉, 산화막을 제거하기 위해 메인 식각 시간의 30% 내지 50% 정도의 시간으로 과도 식각(over etch)을 실시하여 실리콘웨이퍼 전면에 걸친 고른 식각 균일성을 얻는다.The contact holes 6 are formed by plasma etching in order to electrically connect the metal wiring layer and the metal wiring layer in the interlayer insulating films 3, 4, and 5 of the semiconductor device having the entire oxide structure. In this case, the plasma etching is performed by main etching the interlayer insulating films 3, 4, and 5 to form a contact hole 6 for electrically connecting the metal wiring layer and the metal wiring layer, and then the metal of the contact hole 6. Even etch uniformity over the entire surface of the silicon wafer by overetching by 30% to 50% of the main etching time in order to remove the interlayer insulating film, that is, the oxide film partially remaining on the wiring pattern 2. Get the castle.
그러나, 이러한 층간 절연막에서의 접촉구 형성을 위한 플라즈마 식각은 종래 기술에서는 특별한 문제를 발생시키지 않지만, 현재 또는 장래에 저 전력, 고속 동작을 요구하는 반도체 소자에서는 게이트 산화막의 두께가 100Å보다 적어지게 됨에 따라 과도 식각이 진행되는 동안 산화막(층간 절연막) 식각이 완료되어 드러난 금속 배선 패턴에는 플라즈마에 의한 손상(damage)이 가해진다. 그리고, 플라즈마 손상의 영향으로 금속 배선 패턴이 안테나의 역할을 하여 게이트 산화막까지 플라즈마 손상이 가해지게 되므로 게이트 산화막의 성능 저하 및 게이트 산화막의 절연 내압을 변동시켜 반도체 소자의 전기적 신뢰도 및 수율의 저하를 가져오게 된다.However, the plasma etching for forming the contact holes in the interlayer insulating film does not cause any particular problem in the prior art, but the thickness of the gate oxide film becomes less than 100 kV in semiconductor devices requiring low power and high speed operation in the present or future. As a result, damage caused by plasma is applied to the metallization pattern that is exposed by the completion of the etching of the oxide film (interlayer insulating film) during the transient etching. In addition, since the metal wiring pattern acts as an antenna and plasma damage is applied to the gate oxide film due to the plasma damage, the performance of the gate oxide film and the dielectric breakdown voltage of the gate oxide film are varied, resulting in a decrease in electrical reliability and yield of the semiconductor device. Come.
본 발명은 이와 같은 문제점을 해결하기 위한 것으로, 그 목적은 금속 배선층 사이를 전기적으로 접속하는 접촉구를 형성하기 위한 플라즈마 식각 공정에서 발생되는 플라즈마 손상을 최소화할 수 있도록 하는 반도체 소자의 층간 절연막 제조 방법을 제공하는 데 있다.SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object thereof is a method of manufacturing an interlayer insulating film of a semiconductor device, which can minimize plasma damage generated in a plasma etching process for forming contact holes for electrically connecting metal wiring layers. To provide.
도 1은 종래의 방법에 의해 제조된 반도체 소자의 층간 절연막에 접촉구를 형성한 상태를 도시한 것이고,1 illustrates a state in which contact holes are formed in an interlayer insulating film of a semiconductor device manufactured by a conventional method.
도 2는 본 발명의 일 실시예에 따라 제조된 반도체 소자의 층간 절연막을 도시한 것이고,2 illustrates an interlayer insulating film of a semiconductor device manufactured according to an embodiment of the present invention.
도 3a와 도 3b는 본 발명의 일 실시예에 따라 제조된 반도체 소자의 층간 절연막에서 접촉구를 식각하는 공정을 도시한 것이다.3A and 3B illustrate a process of etching contact holes in an interlayer insulating film of a semiconductor device manufactured according to an embodiment of the present invention.
상기와 같은 목적을 달성하기 위하여, 본 발명은 산화막으로 이루어진 층간 절연막 하부에 산화막과의 식각 선택비가 큰 라이너 절연막을 형성하여 접촉구 형성을 위한 플라즈마 식각이 진행되는 동안 금속 배선 패턴이 플라즈마에 노출되는 것을 최소화하는 것을 특징으로 한다.In order to achieve the above object, the present invention forms a liner insulating film having a large etching selectivity with respect to the oxide film under the interlayer insulating film made of an oxide film so that the metal wiring pattern is exposed to the plasma during plasma etching for forming the contact hole. It is characterized in that to minimize.
이하, 첨부된 도면을 참조하여 본 발명에 따른 바람직한 일 실시예를 설명한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.
도 2는 본 발명의 일 실시예에 따라 제조된 반도체 소자의 층간 절연막을 도시한 것으로, 이를 참조하여 본 발명의 일 실시예에 따른 반도체 소자의 층간 절연막 제조 방법을 설명한다.2 illustrates an interlayer insulating film of a semiconductor device manufactured according to an exemplary embodiment of the present invention, and a method of manufacturing the interlayer insulating film of the semiconductor device according to an exemplary embodiment of the present invention will be described with reference to this.
금속 배선 패턴(12)이 형성된 하부 박막(11) 상부에 산화막과의 식각 선택비가 큰 라이너 절연막(13), 바람직하게는 라이너 질화막을 형성한 후, 라이너 절연막(13) 상부에 화학 기상 증착법으로 라이너 산화막(14)을 증착한다.After forming the liner insulating film 13, preferably the liner nitride film having a large etching selectivity with the oxide film on the lower thin film 11 on which the metal wiring pattern 12 is formed, the liner by chemical vapor deposition on the liner insulating film 13 An oxide film 14 is deposited.
그리고, 각 금속 배선 패턴(12) 사이의 갭에 의해 후속 공정에서 산화막 증착시 발생되는 요곡을 최소화하기 위하여 SOG에 의해 유기 용제로 녹인 유리를 회전 도포하고 열처리하여 SOG 박막(15)을 형성한다.The SOG thin film 15 is formed by rotationally applying and heat-treating the glass melted with an organic solvent by SOG in order to minimize the curvature generated during the deposition of the oxide film in a subsequent process due to the gap between the metal wiring patterns 12.
이후, SOG 박막(15) 상부에 화학 기상 증착법으로 산화막(16)을 두껍게 증착하고, 화학 기계적 연마 공정에 의해 증착된 산화막(16)을 평탄화함으로써 산화막과의 식각 선택비가 큰 라이너 절연막(13) 및 라이너 절연막(13) 상부의 산화막 구조(14, 15, 16)로 이루어진 8㎛ 내지 12㎛ 정도의 두께를 가진 층간 절연막(13, 14, 15, 16)을 완성한다.Subsequently, the oxide film 16 is thickly deposited on the SOG thin film 15 by chemical vapor deposition, and the oxide film 16 deposited by the chemical mechanical polishing process is planarized so that the etch selectivity with the oxide film is large. The interlayer insulating films 13, 14, 15, and 16 having a thickness of about 8 µm to 12 µm having the oxide film structures 14, 15, and 16 formed on the liner insulating layer 13 are completed.
이와 같이 본 발명의 일 실시예에 따라 제조된 반도체 소자의 층간 절연막에서 금속 배선층과 금속 배선층 사이를 전기적으로 접속하기 위한 접촉구를 식각하는 공정을 도 3a와 도 3b를 참조하여 설명한다.As described above, a process of etching a contact hole for electrically connecting the metal wiring layer and the metal wiring layer in the interlayer insulating film of the semiconductor device manufactured according to the exemplary embodiment of the present invention will be described with reference to FIGS. 3A and 3B.
먼저 도 3a에 도시한 바와 같이, 층간 절연막(13, 14, 15, 16) 상부에 접촉구 형성을 위한 감광막 패턴(미도시)을 형성한 후, 감광막 패턴을 마스크로 드러난 산화막(16), SOG 박막(15), 라이너 산화막(14)의 산화막 구조(14, 15, 16)를 플라즈마 식각하여 접촉구(17)를 형성한다. 이때, 플라즈마 식각은 산화막(14, 15, 16)과 라이너 절연막(13)의 식각 선택비 차이를 이용하여 라이너 절연막(13)을 식각 정지막으로 하여 메인 식각한 후, 접촉구(17)의 라이너 절연막(13) 상부에 잔류하는 산화막을 완전히 제거하기 위하여 메인 식각 시간의 30% 내지 50% 정도의 시간으로 과도 식각을 실시하여 실리콘웨이퍼 전면에 걸쳐 고른 식각 균일성을 갖도록 한다. 따라서, 종래와는 달리 과도 식각을 진행하는 동안에 금속 배선 패턴(12)이 플라즈마에 노출되지 않으므로 플라즈마 손상을 받지 않는다.First, as shown in FIG. 3A, a photoresist pattern (not shown) for forming a contact hole is formed on the interlayer insulating layers 13, 14, 15, and 16, and then the oxide layer 16 and SOG having the photoresist pattern exposed as a mask. The contact holes 17 are formed by plasma etching the thin film 15 and the oxide film structures 14, 15, and 16 of the liner oxide film 14. In this case, the plasma etching is performed by main etching using the liner insulating layer 13 as an etch stop layer by using the difference in etching selectivity between the oxide layers 14, 15, and 16 and the liner insulating layer 13, and then the liner of the contact hole 17. In order to completely remove the oxide film remaining on the insulating film 13, the excessive etching is performed at a time of about 30% to 50% of the main etching time to have an even etching uniformity over the entire surface of the silicon wafer. Therefore, unlike the related art, since the metallization pattern 12 is not exposed to the plasma during the excessive etching, the plasma is not damaged.
그 다음 도 3b에 도시한 바와 같이, 플라즈마 식각에 의해 접촉구(17)의 드러난 라이너 절연막(13)을 식각하여 제거하고, 층간 절연막(13, 14, 15, 16) 상부에 잔류하는 감광막 패턴을 제거함으로써 금속 배선층과 금속 배선층을 전기적으로 접속하기 위한 접촉구(17)를 완성한다. 이때, 얇은 라이너 절연막(13)의 식각 진행 동안에 금속 배선 패턴(12)이 종래의 라이너 산화막 식각시의 과도 식각 진행에 비해 플라즈마에 적게 노출되므로 플라즈마 손상으로 인한 게이트 산화막의 손상을 최소화 할 수 있어 게이트 산화막의 성능을 향상시키게 된다.3B, the exposed liner insulating layer 13 of the contact hole 17 is etched and removed by plasma etching, and the photoresist pattern remaining on the interlayer insulating layers 13, 14, 15, and 16 is removed. By removing, the contact hole 17 for electrically connecting a metal wiring layer and a metal wiring layer is completed. At this time, since the metal wiring pattern 12 is less exposed to the plasma during the etching process of the thin liner insulating layer 13, the damage of the gate oxide layer due to the plasma damage can be minimized because the metal wiring pattern 12 is less exposed to the plasma etching process. The performance of the oxide film is improved.
이와 같이 본 발명은 산화막 구조 하부에 산화막과의 식각 선택비가 큰 라이너 절연막을 형성하여 층간 절연막을 형성함으로써, 산화막의 과도 식각시 금속 배선 패턴이 드러나지 않으므로 플라즈마 손상을 방지할 수 있으며, 산화막의 과도 식각 이후 라이너 절연막을 식각하므로 플라즈마 손상을 최소화할 수 있어 반도체 소자의 신뢰성 및 수율을 향상시킬 수 있다.As such, the present invention forms an interlayer insulating film by forming a liner insulating film having a large etching selectivity with the oxide film under the oxide film structure, thereby preventing plasma damage since the metal wiring pattern is not exposed during the excessive etching of the oxide film, and the excessive etching of the oxide film Since the liner insulating layer is etched, plasma damage can be minimized, thereby improving the reliability and yield of the semiconductor device.
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