KR0166508B1 - Metal wiring forming method of semiconductor device - Google Patents
Metal wiring forming method of semiconductor device Download PDFInfo
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- KR0166508B1 KR0166508B1 KR1019950017487A KR19950017487A KR0166508B1 KR 0166508 B1 KR0166508 B1 KR 0166508B1 KR 1019950017487 A KR1019950017487 A KR 1019950017487A KR 19950017487 A KR19950017487 A KR 19950017487A KR 0166508 B1 KR0166508 B1 KR 0166508B1
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- metal wiring
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- etching process
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- 238000000034 method Methods 0.000 title claims abstract description 56
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 42
- 239000002184 metal Substances 0.000 title claims abstract description 42
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 238000005530 etching Methods 0.000 claims abstract description 51
- 239000006227 byproduct Substances 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 239000000463 material Substances 0.000 claims abstract description 7
- 239000010410 layer Substances 0.000 claims description 27
- 229920002120 photoresistant polymer Polymers 0.000 claims description 17
- 239000011229 interlayer Substances 0.000 claims description 9
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 8
- 229910052721 tungsten Inorganic materials 0.000 claims description 8
- 239000010937 tungsten Substances 0.000 claims description 8
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 230000001052 transient effect Effects 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 239000007789 gas Substances 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 230000010354 integration Effects 0.000 abstract description 4
- 230000004888 barrier function Effects 0.000 description 5
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Abstract
본 발명은 반도체소자의 금속배선 형성방법에 관한 것으로, 반도체기판 상부에 물질층과 절연막을 형성하고 그 상부에 금속배선층을 형성한 다음, 금속배선을 형성하기 위하여 금속배선 마스크를 이용한 식각공정으로 상기 금속배선층을 식각하되, 과도식각을 수반하여 상기 금속배선층이 식각되는 부분에 많은 식각부산물을 형성하고 전체표면상부에 평탄화층을 형성함으로써 보이드의 발생을 방지하여 반도체소자의 특성 및 신뢰성을 향상시키고 반도체소자의 고집적화를 가능하게 하는 기술이다.The present invention relates to a method for forming a metal wiring of a semiconductor device, by forming a material layer and an insulating film on the semiconductor substrate, and a metal wiring layer formed on the semiconductor substrate, the etching process using a metal wiring mask to form a metal wiring. Etch the metal wiring layer, but by forming a large number of etching by-products on the portion where the metal wiring layer is etched along with the excessive etching and forming a planarization layer on the entire surface to prevent the generation of voids to improve the characteristics and reliability of the semiconductor device It is a technology that enables high integration of devices.
Description
제1a도 내지 제1d도는 본 발명의 실시예에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도.1A to 1D are cross-sectional views illustrating a method for forming metal wirings in a semiconductor device according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 반도체기판 13 : 산화막11 semiconductor substrate 13 oxide film
15 : 장벽금속층 17 : 텅스텐15 barrier metal layer 17 tungsten
19 : 반사방지막 21 : 감광막패턴19: antireflection film 21: photosensitive film pattern
23 : 식각부산물 25 : 층간절연막23 etching by-product 25 interlayer insulating film
본 발명은 반도체소자의 금속배선 형성방법에 관한 것으로, 특히 금속배선 형성공정시 발생되는 식각부산물로 상기 금속배선 사이를 매립하고 그 상부에 평탄화층을 형성함으로써 후공정을 용이하게 하여 반도체소자의 신뢰성 및 특성을 향상시키고 반도체소자의 고집적화를 가능하게 하는 기술에 따른 것이다.The present invention relates to a method for forming a metal wiring of a semiconductor device, and in particular, by embedding the metal wiring with an etching by-product generated during the metal wiring forming process and forming a planarization layer thereon, thereby facilitating post-processing and reliability of the semiconductor device. And techniques for improving properties and enabling high integration of semiconductor devices.
일반적으로, 반도체기판 상부에 물질층을 형성하고 그 상부를 평탄화시키는 평탄화층을 형성한 다음 후속공정을 실시한다. 디램(DRAM)에서는 반도체기판 상부에 트랜지스터와 캐패시터를 형성하고 그 상부에 평탄화시키고 그 상부에 다수의 금속배선층을 형성한다. 이때, 상기 금속배선층은 각각 금속배선층 사이에 평탄화된 층간절연막이 존재하여 소자의 동작특성을 향상시킨다. 여기서, 상기 층간절연막은 상기 층간절연막 상부에 형성되는 금속배선층을 균일하게 형성하기 위하여 평탄화된 상태로 형성되어야 한다.In general, a material layer is formed on the semiconductor substrate and a planarization layer is formed to planarize the upper portion thereof, and then a subsequent process is performed. In DRAM, transistors and capacitors are formed on a semiconductor substrate, and planarized on the semiconductor substrate, and a plurality of metal wiring layers are formed on the semiconductor substrate. In this case, each of the metal wiring layers has a planarized interlayer insulating film between the metal wiring layers, thereby improving operation characteristics of the device. Here, the interlayer insulating film must be formed in a flattened state to uniformly form a metal wiring layer formed on the interlayer insulating film.
종래 기술은 반도체기판 상부에 물질층 및 평탄화된 산화막을 형성하고 그 상부에 금속배선을 형성한다. 그리고, 그 상부에 층간절연막인 산화막을 증착하고 후공정을 실시한다. 그러나, 상기 금속배선 간의 간격이 좁을 경우 상기 산화막이 오버행(over hang)의 형상을 이루어 보이드(void)가 발생됨으로써 반도체소자의 신뢰성 및 특성이 저하되고 반도체소자의 고집적화가 어려운 문제점이 있다.The prior art forms the material layer and the planarized oxide film on the semiconductor substrate and the metal wiring on the semiconductor substrate. Then, an oxide film, which is an interlayer insulating film, is deposited on the upper portion, and a post-process is performed. However, when the gap between the metal wires is narrow, the oxide film forms an overhang, causing voids, thereby deteriorating reliability and characteristics of the semiconductor device and making it difficult to integrate the semiconductor device.
따라서, 본 발명은 종래 기술의 문제점을 해결하기 위하여, 금속배선 식각공정시 발생되는 부산물을 이용하여 평탄화된 층간절연막을 형성함으로써 반도체소자의 특성 및 신뢰성을 향상시키고 반도체소자의 고집적화를 가능하게 하는 반도체소자의 금속배선 형성방법을 제공하는데 그 목적이 있다.Accordingly, the present invention is to solve the problems of the prior art, by forming a planarized interlayer insulating film using by-products generated during the metallization etching process to improve the characteristics and reliability of the semiconductor device and to enable high integration of the semiconductor device It is an object of the present invention to provide a method for forming metal wirings of a device.
이상의 목적을 달성하기 위한 본 발명인 반도체소자의 금속배선 형성방법의 특징은, 반도체기판 상부에 물질층을 형성하는 공정과, 상기 물질층 상부에 절연막을 형성하는 공정과, 상기 제1절연막 상부에 금속배선층을 형성하는 공정과, 상기 금속배선층 상부에 감광막패턴을 형성하는 공정과, 상기 감광막패턴을 마스크로하는 식각공정으로 상기 금속배선층을 식각하되, 상기 식각공정시 수반되는 과도식각공정으로 식각부산물이 상기 식각된 부분에 형성되는 공정과, 상기 감광막패턴을 제거하는 공정과, 전체표면상부에 층간절연막을 형성하여 평탄화시키는 공정을 포함하는데 있다.The metal wiring forming method of the semiconductor device of the present invention for achieving the above object is a step of forming a material layer on the semiconductor substrate, a step of forming an insulating film on the material layer, and a metal on the first insulating film Etching the metal wiring layer by a process of forming a wiring layer, a process of forming a photoresist pattern on top of the metal wiring layer, and an etching process using the photoresist pattern as a mask, the etching by-products in the transient etching process during the etching process And forming the interlayer insulating film over the entire surface, and removing the photoresist pattern.
또한, 상기 금속배선층은 Ti/TiN/W/TiN의 적층구조로 형성되는 것과, 상기 감광막패턴은 금속배선 마스크를 이용한 식각공정으로 형성되는 것과, 상기 식각공정은 MERIE를 이용한 건식이방성 식각공정으로 실시되는 것과, 상기 MERIE 식각공정은 SF6계 가스를 사용하여 실시되는 것과, 상기 식각공정은 상기 텅스텐이 상기 감광막패턴과 식각선택비 차이가 적은 조건에서 실시됨으로써 식각부산물이 많이 발생되도록 실시되는 것과, 상기 감광막패턴은 산소플라즈마를 이용하여 제거하고 상기 식각공정에서 발생된 상기 감광막패턴의 부산물은 습식방법으로 제거되는 것과, 상기 식각부산물은 상기 과도식각 정도에 따라 조절되는 것이다.In addition, the metal wiring layer is formed of a stacked structure of Ti / TiN / W / TiN, the photosensitive film pattern is formed by an etching process using a metal wiring mask, the etching process is performed by a dry anisotropic etching process using MERIE And, the MERIE etching process is performed using a SF6-based gas, the etching process is performed so that the etching by-products are generated a lot by etching the tungsten in the condition that the difference in etching selectivity with the photosensitive film pattern, The photoresist pattern is removed by using an oxygen plasma, and the by-products of the photoresist pattern generated in the etching process are removed by a wet method, and the etching by-products are controlled according to the degree of transient etching.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제1a도 내지 제1d도는 본 발명의 실시예에 따른 반도체소자의 금속배선 형성공정을 도시한 단면도이다.1A to 1D are cross-sectional views illustrating a metal wiring forming process of a semiconductor device according to an embodiment of the present invention.
제1a도를 참조하면, 반도체기판(11) 상부에 산화막(13) 상부에 장벽금속층(15)을 형성한다. 이때, 상기 장벽금속층(15)은 티타늄과 티타늄질화막의 적층구조로 형성된 것이다. 그 다음에, 상기 장벽금속층(15) 상부에 텅스텐(17)을 일정두께 형성한다. 그리고, 상기 텅스텐(17) 상부에 반사방지막(19)을 일정두께 형성한다. 상기 반사방지막(19)은 티타늄질화막으로 형성된 것이다. 그 다음에, 상기 반사방지막(19) 상부에 감광막패턴(21)을 형성한다. 상기 감광막패턴(21) 금속배선을 형성하기 위한 마스크(도시안됨)을 이용한 식각공정으로 형성한 것이다.Referring to FIG. 1A, the barrier metal layer 15 is formed on the oxide substrate 13 on the semiconductor substrate 11. At this time, the barrier metal layer 15 is formed of a laminated structure of titanium and titanium nitride film. Next, tungsten 17 is formed on the barrier metal layer 15 at a predetermined thickness. In addition, an anti-reflection film 19 is formed on the tungsten 17 at a predetermined thickness. The anti-reflection film 19 is formed of a titanium nitride film. Next, the photoresist pattern 21 is formed on the anti-reflection film 19. The photoresist pattern 21 is formed by an etching process using a mask (not shown) for forming metal wiring.
제1b도를 참조하면, 상기 감광막패턴(21)을 마스크로 하여 상기 반사방지막(19), 텅스텐(17) 및 장벽금속층(15)을 식각한다. 이때, 상기 식각공정은 과도식각공정을 수반하여 상기 식각공정시 식각부산물(23)이 상기 식각된 부분에 남도록 실시한 것이다. 여기서, 상기 식각부산물(23)은 C, F, 및 O가 주성분을 이루며 상기 과도식각 정도에 따라 두께가 조절된다.Referring to FIG. 1B, the anti-reflection film 19, tungsten 17, and barrier metal layer 15 are etched using the photoresist pattern 21 as a mask. At this time, the etching process is carried out so that the etching by-products 23 remain in the etched portion during the etching process in accordance with the transient etching process. Here, the etching by-product (23) is a main component of C, F, and O and the thickness is adjusted according to the degree of the excessive etching.
그리고, 상기 식각공정은 자기장을 이용한 반응성 이온식각 장비에서 SF6/Cl2/N2 가스를 이용하여 건식이방성 식각방법으로 실시된 것이다.In addition, the etching process is performed by dry anisotropic etching method using SF6 / Cl2 / N2 gas in a reactive ion etching equipment using a magnetic field.
제1c도를 참조하면, 상기 감광막패턴(21)을 제거한다. 이때, 상기 감광막패턴(21)은 건식 또는 습식방법으로 제거된 것이다. 그리고, 상기 건식방법은 산소플라즈마를 이용한 식각공정으로 실시된 것이다. 그리고, 상기 건식식각방법은 상기 텅스텐(17) 및 감광막패턴(21)과의 식각선택비 차이가 낮은 조건에서 실시된 것이다.Referring to FIG. 1C, the photosensitive film pattern 21 is removed. At this time, the photoresist pattern 21 is removed by a dry or wet method. In addition, the dry method is performed by an etching process using oxygen plasma. The dry etching method is performed under a condition where the difference in etching selectivity between the tungsten 17 and the photoresist pattern 21 is low.
제1d도를 참조하면, 전체표면상부에 층간절연막(25)을 형성함으로써 상층구조를 평탄화시킨다.Referring to FIG. 1D, the upper layer structure is planarized by forming the interlayer insulating film 25 over the entire surface.
본 발명의 실시예는 금속배선을 형성하는 상기 텅스텐(17) 대신에 식각부산물(23)이 많이 발생되는 다른 금속으로 상기 금속배선을 형성할 수 있다.In an embodiment of the present invention, the metal wiring may be formed of another metal in which an etching byproduct 23 is generated in place of the tungsten 17 forming the metal wiring.
이상에서 설명한 바와 같이 본 발명인 반도체소자의 금속배선 형성방법은, 금속배선층 식각공정시 발생되는 식각부산물을 이용한 평탄화공정으로 보이드의 발생을 방지함으로써 반도체소자의 신뢰성 및 특성을 향상시키고 반도체소자의 고집적화를 가능하게 하는 잇점이 있다.As described above, the method for forming metal wiring of the semiconductor device of the present invention improves the reliability and characteristics of the semiconductor device by preventing voids in the planarization process using the etching by-product generated during the metal wiring layer etching process, and improves the integration of the semiconductor device. There is an advantage to this.
Claims (8)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950017487A KR0166508B1 (en) | 1995-06-26 | 1995-06-26 | Metal wiring forming method of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950017487A KR0166508B1 (en) | 1995-06-26 | 1995-06-26 | Metal wiring forming method of semiconductor device |
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| KR970003488A KR970003488A (en) | 1997-01-28 |
| KR0166508B1 true KR0166508B1 (en) | 1999-02-01 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100454626B1 (en) * | 1997-05-07 | 2005-01-05 | 주식회사 하이닉스반도체 | Method for forming metal interconnection of semiconductor device to control bowing phenomenon and form metal interconnection of uniform cd |
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| KR100549333B1 (en) * | 1998-10-02 | 2006-04-06 | 주식회사 하이닉스반도체 | Metal wiring formation method of semiconductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100454626B1 (en) * | 1997-05-07 | 2005-01-05 | 주식회사 하이닉스반도체 | Method for forming metal interconnection of semiconductor device to control bowing phenomenon and form metal interconnection of uniform cd |
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| KR970003488A (en) | 1997-01-28 |
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