KR100507869B1 - Contact hole formation method of semiconductor device - Google Patents
Contact hole formation method of semiconductor device Download PDFInfo
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- KR100507869B1 KR100507869B1 KR10-1998-0024678A KR19980024678A KR100507869B1 KR 100507869 B1 KR100507869 B1 KR 100507869B1 KR 19980024678 A KR19980024678 A KR 19980024678A KR 100507869 B1 KR100507869 B1 KR 100507869B1
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- contact hole
- pattern
- forming
- film
- etch stop
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 238000000034 method Methods 0.000 title claims abstract description 23
- 230000015572 biosynthetic process Effects 0.000 title description 2
- 238000005530 etching Methods 0.000 claims description 21
- 150000004767 nitrides Chemical class 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 14
- 229920002120 photoresistant polymer Polymers 0.000 claims description 8
- 230000004888 barrier function Effects 0.000 claims description 4
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 229910052731 fluorine Inorganic materials 0.000 claims description 2
- 239000011737 fluorine Substances 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 2
- 229920005591 polysilicon Polymers 0.000 claims description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims 1
- 230000002265 prevention Effects 0.000 claims 1
- 239000010410 layer Substances 0.000 abstract description 13
- 239000011229 interlayer Substances 0.000 abstract description 7
- 229910052751 metal Inorganic materials 0.000 abstract description 4
- 239000002184 metal Substances 0.000 abstract description 4
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 5
- 238000001039 wet etching Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- Condensed Matter Physics & Semiconductors (AREA)
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- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
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- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 콘택홀 측벽에 첨점의 발생 없이 콘택홀의 입구 부분을 확장시킬 수 있는 반도체 소자의 콘택홀 형성 방법에 관한 것으로, 콘택홀 입구 부분에 층간절연막과 식각 성질이 다른 물질로 식각방지 패턴을 형성한 후 층간절연막을 식각하여 콘택홀 측벽에 첨점의 발생없이 콘택홀을 형성하는데 그 특징이 있다. 이에 의해 콘택홀의 입구를 확장시키면서도 콘택홀 측벽에 첨점이 발생하는 것을 방지할 수 있어 콘택홀 내에 보이드의 발생 없이 금속막을 매립할 수 있다.The present invention relates to a method for forming a contact hole in a semiconductor device capable of expanding the inlet portion of the contact hole without generating a peak on the sidewall of the contact hole. After that, the interlayer insulating layer is etched to form the contact holes on the sidewalls of the contact holes without generation of peaks. As a result, it is possible to prevent the occurrence of fine points on the sidewalls of the contact hole while expanding the inlet of the contact hole, thereby filling the metal film without generating voids in the contact hole.
Description
본 발명은 반도체 장치 제조 분야에 관한 것으로, 특히 반도체 소자의 콘택홀 형성 방법에 관한 것이다.TECHNICAL FIELD The present invention relates to the field of semiconductor device manufacturing, and more particularly, to a method for forming a contact hole in a semiconductor device.
반도체 소자의 집적도가 향상됨에 따라 좁은 콘택홀 내에 전도막을 효과적으로 매립시키기 위한 방법이 모색되고 있다.As the degree of integration of semiconductor devices is improved, a method for effectively embedding a conductive film in a narrow contact hole has been sought.
종래 기술에 따른 고집적 반도체 소자의 콘택홀 형성 방법은, 반도체 기판 상에 형성된 층간절연막 상에 식각마스크를 형성하고, 습식식각으로 층간절연막을 제거하여 식각마스크가 정의한 크기보다 콘택홀의 입구를 크게 형성하고, 반도체 기판이 노출될 때까지 건식식각으로 층간절연막을 제거하여 콘택홀을 형성하는 일련의 과정으로 이루어진다.According to the related art, the method for forming a contact hole of a highly integrated semiconductor device includes forming an etch mask on an interlayer insulating film formed on a semiconductor substrate, removing the interlayer insulating film by wet etching, and forming a larger contact opening than a size defined by the etch mask. In addition, a series of processes are performed to form contact holes by removing the interlayer insulating layer by dry etching until the semiconductor substrate is exposed.
도1은 전술한 바와 같이 콘택홀 형성이 완료된 후 알루미늄막(12)을 형성하여 반도체 기판(10)과 연결시킨 상태를 보이고 있다. 도1에서 도면 부호10은 반도체 기판, 11은 층간절연막, 12는 알루미늄막을 나타낸다.FIG. 1 illustrates a state in which an aluminum film 12 is formed and connected to the semiconductor substrate 10 after the contact hole is formed as described above. In Fig. 1, reference numeral 10 denotes a semiconductor substrate, 11 an interlayer insulating film, and 12 an aluminum film.
습식식각과 건식식각을 실시함으로 인하여 콘택홀 측벽에 첨점(A)이 발생하고, 알루미늄막(12)이 콘택홀 내부에 효과적으로 매립되지 못하고 보이드(void)가 발생한다.By performing wet etching and dry etching, a peak A is generated on the sidewalls of the contact hole, and the aluminum film 12 is not effectively embedded in the contact hole, and voids are generated.
보이드의 발생으로 이후의 공정에서 수분이 침투가 쉽게 일어나 부식이 유발되고 소자의 특성이 저하되는데, 보이드의 발생을 억제하기 위하여 매립 특성이 양호한 텅스텐막 또는 구리막을 증착하고 있으나, 텅스텐막의 경우는 높은 저항에 의하여 소자의 동작 속도가 떨어지고, 구리막의 경우는 식각이 용이하지 못한 단점이 있다.Due to the generation of voids, moisture easily penetrates in subsequent processes, causing corrosion and deteriorating the characteristics of the device. In order to suppress the generation of voids, a buried tungsten film or a copper film is deposited. The resistance of the device is reduced by the resistance, and the copper film has a disadvantage in that etching is not easy.
상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은 콘택홀 측벽에 첨점의 발생없이 콘택홀의 입구 부분을 확장시킬 수 있는 반도체 소자의 콘택홀 형성 방법을 제공하는데 그 목적이 있다.An object of the present invention is to provide a method for forming a contact hole in a semiconductor device capable of expanding an inlet portion of a contact hole without generating a peak on the sidewall of the contact hole.
상기 목적을 달성하기 위한 본 발명은 반도체 기판 상에 형성된 제1산화막 상에 식각방지막을 형성하는 단계; 상기 식각방지막을 선택적으로 식각하여 개구를 갖는 식각방지막패턴을 콘택홀 영역의 입구 주변에 잔류시키는 단계; 상기 식각방지막패턴을 포함한 상기 반도체 기판 상에 제2산화막을 형성하는 단계; 상기 제2산화막 상에 상기 식각방지막패턴의 개구보다 큰 개구를 갖는 감광막패턴을 형성하는 단계; 및 상기 감광막패턴을 식각마스크로 상기 제2산화막을 선택적으로 식각하여 상기 식각방지막패턴의 개구보다 큰 폭을 갖는 콘택홀 입구를 개방시키고 연속해서 상기 콘택홀 입구에 의해 노출된 상기 식각방지막패턴의 개구 아래 제1산화막을 선택적으로 식각하여 상기 반도체 기판을 노출시키는 콘택홀을 형성하되, 상기 제1,2산화막의 식각률과 상기 식각방지막패턴의 식각률을 다르게 하여 상기 식각방지막 패턴의 모서리를 완만하게 하는 단계를 포함하는 반도체 소자의 콘택홀 형성 방법을 제공한다.The present invention for achieving the above object is a step of forming an etch stop layer on the first oxide film formed on a semiconductor substrate; Selectively etching the etch stop layer to leave an etch stop pattern pattern having an opening around the entrance of the contact hole region; Forming a second oxide film on the semiconductor substrate including the etch stop pattern; Forming a photoresist pattern on the second oxide layer, the photoresist pattern having an opening larger than an opening of the etch stop layer pattern; And selectively etching the second oxide layer using the photoresist pattern as an etch mask to open a contact hole inlet having a width greater than that of the etch stop layer pattern, and subsequently to open an opening of the etch stop layer pattern exposed by the contact hole inlet. Selectively etching the first oxide layer below to form a contact hole exposing the semiconductor substrate, and varying the etching rate of the first and second oxide layers and the etching rate of the etch barrier pattern to smooth the edges of the etch barrier pattern It provides a method for forming a contact hole in a semiconductor device comprising a.
본 발명은 콘택홀 입구 부분에 층간절연막과 식각 성질이 다른 물질로 식각 방지 패턴을 형성한 후 층간절연막을 식각하여 콘택홀 측벽에 첨점의 발생없이 콘택홀을 형성하는 방법이다.The present invention is a method of forming a contact hole without forming a peak on the sidewall of the contact hole by etching the interlayer insulating film after forming an etch stop pattern of the material having a different etching property than the interlayer insulating film in the contact hole inlet.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 바람직한 실시예를 첨부된 도면 도 2a 내지 도 2e를 참조하여 설명한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. Will be explained.
먼저, 도 2a에 도시한 바와 같이 반도체 기판(20) 상에 형성된 제1 산화막(20) 상에 500 Å 내지 3000 Å 두께의 질화막(22)을 형성하고, 질화막(22) 상에 콘택홀의 입구를 둘러싸는 제1 감광막 패턴(31)을 형성한다.First, as shown in FIG. 2A, a nitride film 22 having a thickness of 500 GPa to 3000 GPa is formed on the first oxide film 20 formed on the semiconductor substrate 20, and the inlet of the contact hole is formed on the nitride film 22. The first photosensitive film pattern 31 that surrounds is formed.
다음으로, 도 2b에 도시한 바와 같이 불소가 함유된 가스를 이용한 건식식각으로 질화막(22)을 식각하여 콘택홀 영역의 제1 산화막(21)을 노출시키고 소정 크기의 개구(opening)를 갖는 질화막패턴(22)이 콘택홀 입구 부분에 남도록 한 후, 전체 구조 상에 평탄화를 위하여 제2 산화막(23)을 형성한다. 제2 산화막(23)은 BPSG(borophospho silicate glass)막으로 형성한다.Next, as illustrated in FIG. 2B, the nitride film 22 is etched by dry etching using a fluorine-containing gas to expose the first oxide film 21 in the contact hole region, and the nitride film has an opening having a predetermined size. After leaving the pattern 22 at the contact hole inlet, a second oxide film 23 is formed on the entire structure for planarization. The second oxide film 23 is formed of a borophospho silicate glass (BPSG) film.
이어서, 제2 산화막(21) 상에 콘택홀 영역을 노출하는 제2 감광막 패턴(32)을 형성한다. 제2 감광막 패턴(32)이 노출시키는 콘택홀 입구의 폭이 제1 감광막 패턴(31)이 노출시킨 콘택홀 입구의 폭, 즉 질화막패턴(22)의 개구 폭보다 크도록 한다.Subsequently, a second photosensitive film pattern 32 exposing the contact hole region is formed on the second oxide film 21. The width of the contact hole inlet exposed by the second photoresist pattern 32 is greater than the width of the contact hole inlet exposed by the first photoresist pattern 31, that is, the opening width of the nitride film pattern 22.
다음으로, 도 2c에 도시한 바와 같이 제2 산화막(23)을 건식식각하여 콘택홀 입구를 개방시켜, 질화막패턴(22)의 일부 및 질화막패턴(22)으로 둘러싸인 제1 산화막(23)을 노출시킨다.Next, as shown in FIG. 2C, the second oxide film 23 is dry-etched to open the contact hole inlet, thereby exposing a portion of the nitride film pattern 22 and the first oxide film 23 surrounded by the nitride film pattern 22. Let's do it.
다음으로, 도 2d에 도시한 바와 같이 계속적인 건식식각으로 질화막패턴(22)의 개구 아래 제1 산화막(21)을 식각하여 반도체 기판(20)을 노출시키는 콘택홀을 형성한다. 이때, 제1 산화막(21)이 식각되면서 질화막패턴(22)의 모서리도 식각되어 입구가 완만한 콘택홀이 형성된다.Next, as shown in FIG. 2D, the first oxide film 21 is etched under the opening of the nitride film pattern 22 by continuous dry etching to form a contact hole exposing the semiconductor substrate 20. At this time, as the first oxide layer 21 is etched, the edge of the nitride layer pattern 22 is also etched to form a contact hole with a gentle entrance.
다음으로, 도 2e에 도시한 바와 같이 전체 구조 상에 알루미늄막(24)을 형성한다. 이때, 콘택홀의 입구가 완만하여 알루미늄막(24)이 보이드의 발생없이 매립된다.Next, as shown in Fig. 2E, an aluminum film 24 is formed over the entire structure. At this time, the inlet of the contact hole is smooth, and the aluminum film 24 is buried without generation of voids.
전술한 본 발명의 일실시예에서 질화막패턴(22)을 대신하여 폴리실리콘막, TiN막, Ti막을 형성할 수도 있으며, 질화막패턴(22) 식각시 인산(H3PO4)을 이용한 습식식각을 실시할 수도 있다.In the above-described embodiment of the present invention, a polysilicon film, a TiN film, and a Ti film may be formed in place of the nitride film pattern 22, and wet etching using phosphoric acid (H 3 PO 4 ) may be used when the nitride film pattern 22 is etched. You can also carry out.
또한, 제2 산화막(23) 및 제1 산화막(21)을 건식식각하는 방법은 고밀도 플라즈마를 이용한 식각이나, 반응성 이온 식각(reactive ion etching) 등으로 실시될 수 있다. 고밀도 플라즈마 챔버에서 식각을 실시할 경우 탑(top) 전력은 1000 W 내지 3000 W를 인가하고, 바텀(bottom) 전력은 100 W 내지 2000 W를 인가하고, 식각 가스로는 20 sccm 내지 120 sccm의 C2F6, CF4 또는 CHF3를 공급한다. 반응성 이온 식각의 경우는 탑(top) 전력은 200 W 내지 2000 W를 인가하고, 바텀(bottom) 전력은 50 W 내지 300 W를 인가하고, 식각가스로는 20 sccm 내지 120 sccm의 C2F6, CF4 또는 CHF3를 공급한다. 그리고, 제2 산화막(23) 또는 제1 산화막(21)의 식각률이 질화막패턴(22)의 식각률의 4배가 넘는 조건 즉, 질화막패턴(22) 대 제1 산화막(21) 또는 제2 산화막(23)의 식각선택비가 1:4 이상인 조건으로 식각을 실시한다.In addition, the method of dry etching the second oxide film 23 and the first oxide film 21 may be performed by etching using high density plasma, reactive ion etching, or the like. When etching in the high density plasma chamber, the top power is applied from 1000 W to 3000 W, the bottom power is applied from 100 W to 2000 W, and the etching gas is C 2 of 20 sccm to 120 sccm. Feed F 6 , CF 4 or CHF 3 . In the case of reactive ion etching, top power is applied from 200 W to 2000 W, bottom power is applied from 50 W to 300 W, and as etching gas, 20 sccm to 120 sccm C 2 F 6 , Feed CF 4 or CHF 3 . The etch rate of the second oxide film 23 or the first oxide film 21 is more than four times the etch rate of the nitride film pattern 22, that is, the nitride film pattern 22 to the first oxide film 21 or the second oxide film 23. Etching is performed under the condition that the etching selectivity of
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.
상기와 같이 이루어지는 본 발명은 콘택홀의 입구를 확장시키면서도 콘택홀 측벽에 첨점이 발생하는 것을 방지할 수 있어 콘택홀 내에 보이드의 발생 없이 금속막을 매립할 수 있다.According to the present invention as described above, it is possible to prevent the occurrence of fine points on the sidewalls of the contact hole while expanding the inlet of the contact hole, thereby filling the metal film without generating voids in the contact hole.
도 1은 종래 기술에 따라 형성된 콘택홀 내에 금속막을 매립한 것을 보이는 단면도,1 is a cross-sectional view showing that a metal film is embedded in a contact hole formed according to the prior art;
도 2a 내지 도 2d는 본 발명의 일실시예에 따른 반도체 소자의 콘택홀 형성 공정 단면도,2A to 2D are cross-sectional views of a contact hole forming process of a semiconductor device according to an embodiment of the present invention;
도 2e는 도 2d와 같이 콘택홀 형성이 완료된 반도체 기판 상에 금속막을 증착한 상태를 보이는 단면도.FIG. 2E is a cross-sectional view of a metal film deposited on a semiconductor substrate on which contact hole formation is completed as shown in FIG. 2D; FIG.
* 도면의 주요 부분에 대한 도면 부호의 설명* Explanation of reference numerals for the main parts of the drawings
20: 반도체 기판 21: 제1 산화막20: semiconductor substrate 21: first oxide film
22: 질화막패턴 23: 제2 산화막22: nitride film pattern 23: second oxide film
24: 알루미늄막 31: 제1 감광막 패턴24: aluminum film 31: first photosensitive film pattern
32: 제2 감광막 패턴32: second photosensitive film pattern
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04260328A (en) * | 1991-02-15 | 1992-09-16 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH0794441A (en) * | 1993-09-21 | 1995-04-07 | Sony Corp | Semiconductor device and its manufacture |
| JPH09167808A (en) * | 1995-12-15 | 1997-06-24 | Sony Corp | Contact structure of semiconductor device, its forming method and semiconductor device |
| JPH09321139A (en) * | 1996-05-30 | 1997-12-12 | Nec Corp | Manufacture of semiconductor device |
| KR100230353B1 (en) * | 1992-11-05 | 1999-11-15 | 윤종용 | Method of forming a contact hole in a semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04260328A (en) * | 1991-02-15 | 1992-09-16 | Fujitsu Ltd | Manufacture of semiconductor device |
| KR100230353B1 (en) * | 1992-11-05 | 1999-11-15 | 윤종용 | Method of forming a contact hole in a semiconductor device |
| JPH0794441A (en) * | 1993-09-21 | 1995-04-07 | Sony Corp | Semiconductor device and its manufacture |
| JPH09167808A (en) * | 1995-12-15 | 1997-06-24 | Sony Corp | Contact structure of semiconductor device, its forming method and semiconductor device |
| JPH09321139A (en) * | 1996-05-30 | 1997-12-12 | Nec Corp | Manufacture of semiconductor device |
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