KR100230353B1 - Method of forming a contact hole in a semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a self-aligned contact in a semiconductor device so that there is no short circuit defect with surrounding wiring. A first step of patterning two first conductive layers at regular intervals, a second step of forming a second insulating layer evenly on the entire surface of the resultant, and forming an etch mask layer thereon; and between the first conductive layers A third process of removing the etch mask layer larger than a contact hole to be formed in the semiconductor substrate, and continuously removing the second insulating layer and the first insulating layer using the remaining etch mask layer and the first conductive layer as a mask; A fourth step of forming a third insulating layer and a fourth insulating layer on the substrate, and then planarizing the surface to expose the surface of the etching mask layer; and using the etching mask layer as a mask. A fifth process of forming an insulating spacer on the exposed sidewalls of the second insulating layer after removing a portion of the third and fourth insulating layers; and removing the remaining fourth insulating layer and the etching mask layer and etching the entire surface to contact the insulating spacers. And a sixth step of forming a hole and filling the second conductive layer.

According to the present invention, it is possible to form contacts in self-alignment without a short circuit defect with the wiring layer.

Description

Contact Forming Method in Semiconductor Device

1 (a) to 1 (e) are cross-sectional views showing a process of forming a contact hole according to the prior art.

2 (a) to 2 (f) is a cross-sectional view showing a process for forming a contact hole according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a contact hole in a semiconductor device, and more particularly, to a method of forming a contact hole in a self-aligned manner such that there is no short circuit defect with a peripheral wiring in a semiconductor device.

In general, as the degree of integration of semiconductor devices increases in semiconductor integrated circuits, it is more difficult to form contact holes for internal wiring between devices. In particular, the gap between the wirings becomes very narrow, and the formation of contact holes formed between the wiring layers becomes more problematic, and it is generally used to form spacers on the wiring sidewalls and form them in a self-aligning manner.

The formation of contact holes between wiring layers will be described with reference to FIGS. 1 (a) to 1 (e) to which a conventional general method is attached.

As shown in FIG. 1 (a), an insulating film 12 is formed on a silicon substrate 11, and a first conductive layer 13 made of a polysilicon layer or the like and a first insulating layer 14 such as nitride or oxide are formed thereon. ) Are sequentially stacked to form a pattern consisting of the first conductive layer 13 and the first insulating layer 14 by using a conventional photolithography technique.

Subsequently, as shown in FIG. 1 (b), the spacer 15 is formed on the sidewall of the pattern formed by applying the second insulating layer to the entire surface and etching back to form the first conductive layer and the first insulating layer. 1 The upper surface and sidewalls of the conductive layer 13 are isolated.

Subsequently, as shown in FIG. 1 (c), the third insulating layer 16 such as a BPSG film, an SOG film, an oxide film, or the like that can be flowed on the entire surface is applied to the entire surface, and then the surface is planarized by a normal planing method or flow After the photoresist 17 is applied to the entire surface, only the portion where the contact hole is to be formed is removed to form a photoresist pattern.

Subsequently, as shown in FIG. 1 (d), a contact hole is formed by an etching process using the photoresist pattern as an etching mask.

Subsequently, as shown in FIG. 1 (e), the second conductive layer 17 is coated on the entire surface, and then a pattern is formed by a normal photolithography process to complete metal wiring.

However, in the prior art, when the third insulating layer 16 and the insulating oxide film 12 for forming the contact holes are removed as shown in FIG. 1 (d), the first insulating layer 14 and A portion of the spacer 15 is excessively etched so that the reliability of the wiring is very low, such as an increase in leakage current or even short circuit between the first conductive layer 13 and the second conductive layer 17. do.

On the other hand, when a conventional insulating film such as a low temperature oxide (LTO) film is used in place of the BPSG film or SOG film that can flow the third insulating layer 16, problems such as the excessive etching when forming a contact are serious. Although it does not occur, the step coverage of the contact hole is very poor, and a problem occurs in that a stringer is formed by a severe step in the subsequent photolithography process for forming the second conductive layer 17. .

Accordingly, an object of the present invention is to provide a method for forming an excellent contact without leakage current and stringer in a self-matching manner by using a wiring layer formed first, in view of the problems of the prior art as described above.

A contact forming method according to the present invention for achieving the above object comprises a first step of forming a first conductive layer pattern on a semiconductor substrate having a first insulating layer formed on its surface, and a second insulating on the entire surface of the resultant A second process of forming the layer flat and forming an etch mask layer thereon; removing the etch mask layer larger than a contact hole to be formed between the first conductive layers, and leaving the etch mask layer and the first conductive layer Using the mask as a mask to continuously remove the second insulating layer and the first insulating layer, and subsequently forming a third insulating layer and a fourth insulating layer on the resultant, so that the surface of the etching mask layer is exposed. And forming an insulating spacer on the exposed sidewalls of the second insulating layer after removing a part of the third and fourth insulating layers using a fourth process of planarizing the surface and the etching mask layer as a mask. A fifth step of removing the fourth insulating layer and the etching mask film and the remaining characterized by having been made in the sixth step that the front etched to form a contact hole and to fill the second conductive layer.

Hereinafter, the present invention will be described in detail with reference to FIGS. 2 (a) to 2 (f).

FIG. 2 (a) shows that the first insulating layer 22 is formed on the silicon substrate 21, the conductive material is applied, and then the pattern 23 of any first conductive layer having a predetermined interval is formed. It is a cross section.

The first insulating layer 22 is a cumulative insulating oxide film, and the first conductive layer 23 has a polysilicon structure composed of a polysilicon layer or polysilicon and silicide.

FIG. 2 (b) is a cross-sectional view illustrating that the second insulating layer 24 is formed on the entire surface, and then planarized to form an etching mask layer 25.

The second insulating layer 24 may be planarized by a photoresist etchback method in the case of a silicon oxide film or a nitride film, or may be reflowed and planarized in the case of an insulating film capable of flow such as BPSG and SOG. In addition, the etching mask layer 25 may be formed of a material having a larger etching selectivity than the second insulating layer 24 such as polysilicon or titanium nitride (TiN).

FIG. 2 (c) shows that the etching mask layer 25 is removed using a conventional photolithography process, which is larger than the portion where the contact hole is to be formed between the first conductive layers 23, and then the remaining etching mask layer ( The second insulating layer 24 is removed using the mask 25 as a mask, and the second insulating layer 24 and the first insulating layer 22 thereunder are removed using the exposed first conductive layer 23 as a mask. The removal was performed continuously to form a contact site.

FIG. 2 (d) shows that the third insulating layer 26 and the fourth insulating layer 27 are continuously formed on the entire surface of the substrate for electrical separation between the first conductive layer 23 and the contact, and then planarized. The etching mask layer is exposed by removing the 3rd and 4th insulating layers except for the portion.

The third insulating layer 26 may be an oxide film or a nitride film, and the fourth insulating layer 27 may be formed using a flowable film such as a spin on glass (SOG) film, a photo resist (PR) film, a BPSG film, and the like. The insulating layer 26 and the fourth insulating layer 27 should be large enough to remove the fourth insulating layer 27 without losing the third insulating layer 26 due to the large etch selectivity. In fact, in the case of the oxide film and the SOG film, the etching selectivity is 20: 1 or more during wet etching, and about 1: 1 in dry etching.

The second insulating layer 24 is exposed after removing a part of the third and fourth insulating layers 26 and 27 at the contact region by using the etching mask layer 25 remaining as a mask as the second (e) again. It is shown that the insulating spacer 28 is formed on the side wall.

The insulating spacer 28 is an oxide film or a nitride film, and the spacer 28 is formed on the third insulating layer having the thickness of the oxide film or the like remaining on the first conductive layer 23 remaining under the contact portion. This is to prevent the first conductive layer 23 from being exposed during the entire surface etching for subsequent contact hole formation by keeping it thicker than the thickness of the oxide film or the like (26). Therefore, the length of the spacer 28 is adjusted to cover the first conductive layer 23. In addition, the spacer 28 may use a material having a large etching selectivity with respect to the second and third insulating layers so that the insulating film of the portion of the first conductive layer may remain unetched when the entire surface is etched.

In FIG. 2 (f), the fourth insulating layer 27 remaining in the contact portion is removed, the etch mask layer 25 is removed, and then the entire surface is etched to form a contact hole or the fourth insulating layer is removed. A cross-sectional view showing a state in which the second conductive layer 29 is formed by forming a contact hole by front etching, removing an etch stop layer, and filling a contact hole with a conductive material.

The removal of the fourth insulating layer 27 is selectively removed by using an etching selectivity difference between the third insulating layer 26 and the spacer 28. In addition, the second conductive layer 19 uses a polysilicon layer, a polyside structure, or aluminum.

As described above, according to the method for forming a contact according to the present invention, the insulation property between the first conductive layer and the second conductive layer is greatly improved, the leakage current is reduced, the reliability of the wiring is improved, and the first wiring layer is formed as an etch stop layer. Since the contacts can be formed by a self-aligning method, the contacts can be easily formed even when the wiring layers are very narrow.

Claims (10)

A first step of patterning first conductive layers on a semiconductor substrate having a first insulating layer formed on a surface thereof, and a second step of forming a second insulating layer flatly on the entire surface of the resultant and forming an etching mask film thereon And a third process of removing the etch mask layer larger than the gap between the first conductive layers and continuously removing the second insulating layer and the first insulating layer using the remaining etch mask layer and the first conductive layer as masks; Forming a third insulating layer and a fourth insulating layer sequentially on the resultant, and then planarizing the surface so that the surface of the etch mask layer is exposed; and removing a part of the third and fourth insulating layers. A fifth step of forming an insulating spacer on sidewalls of the insulating layer, and a sixth hole of removing the remaining fourth insulating layer and the etching mask layer and etching the entire surface to form contact holes and filling the second conductive layer. The method for forming the contact, characterized in that having been made in the. The method of claim 1, wherein the first conductive layer is a polysilicon layer or a polyside structure. The method of claim 1, wherein the second conductive layer is a polysilicon layer, a polyside structure, or an aluminum layer. The method of claim 1, wherein the second and third insulating layers are formed of an oxide film or a nitride film. The method of claim 1, wherein the spacer is formed of an oxide film or a nitride film. The contact forming method of claim 1, wherein the spacer has an etching selectivity greater than that of the second and third insulating layers. The method of claim 1, wherein the etching mask layer of the second process has an etching selectivity greater than that of the second insulating layer. 8. The method of claim 7, wherein the etching mask layer of the second process is made of polysilicon or titanium nitride. The method of claim 1, wherein an etching selectivity of the fourth insulating layer is greater than that of the third insulating layer and the insulating space. 10. The method of claim 9, wherein the fourth insulating layer is one of a BPSG film, an SOG film, and a PR film.